drivers/remoteproc/qcom_wcnss.c

   1 /*
   2  * Qualcomm Peripheral Image Loader
   3  *
   4  * Copyright (C) 2016 Linaro Ltd
   5  * Copyright (C) 2014 Sony Mobile Communications AB
   6  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/firmware.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/io.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/qcom_scm.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/remoteproc.h>
  31 #include <linux/soc/qcom/smem.h>
  32 #include <linux/soc/qcom/smem_state.h>
  33
  34 #include "qcom_mdt_loader.h"
  35 #include "remoteproc_internal.h"
  36 #include "qcom_wcnss.h"
  37
  38 #define WCNSS_CRASH_REASON_SMEM         422
  39 #define WCNSS_FIRMWARE_NAME             "wcnss.mdt"
  40 #define WCNSS_PAS_ID                    6
  41
  42 #define WCNSS_SPARE_NVBIN_DLND          BIT(25)
  43
  44 #define WCNSS_PMU_IRIS_XO_CFG           BIT(3)
  45 #define WCNSS_PMU_IRIS_XO_EN            BIT(4)
  46 #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP    BIT(5)
  47 #define WCNSS_PMU_IRIS_XO_CFG_STS       BIT(6) /* 1: in progress, 0: done */
  48
  49 #define WCNSS_PMU_IRIS_RESET            BIT(7)
  50 #define WCNSS_PMU_IRIS_RESET_STS        BIT(8) /* 1: in progress, 0: done */
  51 #define WCNSS_PMU_IRIS_XO_READ          BIT(9)
  52 #define WCNSS_PMU_IRIS_XO_READ_STS      BIT(10)
  53
  54 #define WCNSS_PMU_XO_MODE_MASK          GENMASK(2, 1)
  55 #define WCNSS_PMU_XO_MODE_19p2          0
  56 #define WCNSS_PMU_XO_MODE_48            3
  57
  58 static const struct rproc_ops wcnss_ops;
  59
  60 struct wcnss_data {
  61         size_t pmu_offset;
  62         size_t spare_offset;
  63
  64         const struct wcnss_vreg_info *vregs;
  65         size_t num_vregs;
  66 };
  67
  68 struct qcom_wcnss {
  69         struct device *dev;
  70         struct rproc *rproc;
  71
  72         void __iomem *pmu_cfg;
  73         void __iomem *spare_out;
  74
  75         bool use_48mhz_xo;
  76
  77         int wdog_irq;
  78         int fatal_irq;
  79         int ready_irq;
  80         int handover_irq;
  81         int stop_ack_irq;
  82
  83         struct qcom_smem_state *state;
  84         unsigned stop_bit;
  85
  86         struct mutex iris_lock;
  87         struct qcom_iris *iris;
  88
  89         struct regulator_bulk_data *vregs;
  90         size_t num_vregs;
  91
  92         struct completion start_done;
  93         struct completion stop_done;
  94
  95         phys_addr_t mem_phys;
  96         phys_addr_t mem_reloc;
  97         void *mem_region;
  98         size_t mem_size;
  99 };
 100
 101 static const struct wcnss_data riva_data = {
 102         .pmu_offset = 0x28,
 103         .spare_offset = 0xb4,
 104
 105         .vregs = (struct wcnss_vreg_info[]) {
 106                 { "vddmx",  1050000, 1150000, 0 },
 107                 { "vddcx",  1050000, 1150000, 0 },
 108                 { "vddpx",  1800000, 1800000, 0 },
 109         },
 110         .num_vregs = 3,
 111 };
 112
 113 static const struct wcnss_data pronto_v1_data = {
 114         .pmu_offset = 0x1004,
 115         .spare_offset = 0x1088,
 116
 117         .vregs = (struct wcnss_vreg_info[]) {
 118                 { "vddmx", 950000, 1150000, 0 },
 119                 { "vddcx", .super_turbo = true},
 120                 { "vddpx", 1800000, 1800000, 0 },
 121         },
 122         .num_vregs = 3,
 123 };
 124
 125 static const struct wcnss_data pronto_v2_data = {
 126         .pmu_offset = 0x1004,
 127         .spare_offset = 0x1088,
 128
 129         .vregs = (struct wcnss_vreg_info[]) {
 130                 { "vddmx", 1287500, 1287500, 0 },
 131                 { "vddcx", .super_turbo = true },
 132                 { "vddpx", 1800000, 1800000, 0 },
 133         },
 134         .num_vregs = 3,
 135 };
 136
 137 void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
 138                             struct qcom_iris *iris,
 139                             bool use_48mhz_xo)
 140 {
 141         mutex_lock(&wcnss->iris_lock);
 142
 143         wcnss->iris = iris;
 144         wcnss->use_48mhz_xo = use_48mhz_xo;
 145
 146         mutex_unlock(&wcnss->iris_lock);
 147 }
 148
 149 static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
 150 {
 151         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 152         phys_addr_t fw_addr;
 153         size_t fw_size;
 154         bool relocate;
 155         int ret;
 156
 157         ret = qcom_scm_pas_init_image(WCNSS_PAS_ID, fw->data, fw->size);
 158         if (ret) {
 159                 dev_err(&rproc->dev, "invalid firmware metadata\n");
 160                 return -EINVAL;
 161         }
 162
 163         ret = qcom_mdt_parse(fw, &fw_addr, &fw_size, &relocate);
 164         if (ret) {
 165                 dev_err(&rproc->dev, "failed to parse mdt header\n");
 166                 return ret;
 167         }
 168
 169         if (relocate) {
 170                 wcnss->mem_reloc = fw_addr;
 171
 172                 ret = qcom_scm_pas_mem_setup(WCNSS_PAS_ID, wcnss->mem_phys, fw_size);
 173                 if (ret) {
 174                         dev_err(&rproc->dev, "unable to setup memory for image\n");
 175                         return -EINVAL;
 176                 }
 177         }
 178
 179         return qcom_mdt_load(rproc, fw, rproc->firmware);
 180 }
 181
 182 static const struct rproc_fw_ops wcnss_fw_ops = {
 183         .find_rsc_table = qcom_mdt_find_rsc_table,
 184         .load = wcnss_load,
 185 };
 186
 187 static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
 188 {
 189         u32 val;
 190
 191         /* Indicate NV download capability */
 192         val = readl(wcnss->spare_out);
 193         val |= WCNSS_SPARE_NVBIN_DLND;
 194         writel(val, wcnss->spare_out);
 195 }
 196
 197 static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
 198 {
 199         u32 val;
 200
 201         /* Clear PMU cfg register */
 202         writel(0, wcnss->pmu_cfg);
 203
 204         val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN;
 205         writel(val, wcnss->pmu_cfg);
 206
 207         /* Clear XO_MODE */
 208         val &= ~WCNSS_PMU_XO_MODE_MASK;
 209         if (wcnss->use_48mhz_xo)
 210                 val |= WCNSS_PMU_XO_MODE_48 << 1;
 211         else
 212                 val |= WCNSS_PMU_XO_MODE_19p2 << 1;
 213         writel(val, wcnss->pmu_cfg);
 214
 215         /* Reset IRIS */
 216         val |= WCNSS_PMU_IRIS_RESET;
 217         writel(val, wcnss->pmu_cfg);
 218
 219         /* Wait for PMU.iris_reg_reset_sts */
 220         while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
 221                 cpu_relax();
 222
 223         /* Clear IRIS reset */
 224         val &= ~WCNSS_PMU_IRIS_RESET;
 225         writel(val, wcnss->pmu_cfg);
 226
 227         /* Start IRIS XO configuration */
 228         val |= WCNSS_PMU_IRIS_XO_CFG;
 229         writel(val, wcnss->pmu_cfg);
 230
 231         /* Wait for XO configuration to finish */
 232         while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
 233                 cpu_relax();
 234
 235         /* Stop IRIS XO configuration */
 236         val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
 237         val &= ~WCNSS_PMU_IRIS_XO_CFG;
 238         writel(val, wcnss->pmu_cfg);
 239
 240         /* Add some delay for XO to settle */
 241         msleep(20);
 242 }
 243
 244 static int wcnss_start(struct rproc *rproc)
 245 {
 246         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 247         int ret;
 248
 249         mutex_lock(&wcnss->iris_lock);
 250         if (!wcnss->iris) {
 251                 dev_err(wcnss->dev, "no iris registered\n");
 252                 ret = -EINVAL;
 253                 goto release_iris_lock;
 254         }
 255
 256         ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
 257         if (ret)
 258                 goto release_iris_lock;
 259
 260         ret = qcom_iris_enable(wcnss->iris);
 261         if (ret)
 262                 goto disable_regulators;
 263
 264         wcnss_indicate_nv_download(wcnss);
 265         wcnss_configure_iris(wcnss);
 266
 267         ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
 268         if (ret) {
 269                 dev_err(wcnss->dev,
 270                         "failed to authenticate image and release reset\n");
 271                 goto disable_iris;
 272         }
 273
 274         ret = wait_for_completion_timeout(&wcnss->start_done,
 275                                           msecs_to_jiffies(5000));
 276         if (wcnss->ready_irq > 0 && ret == 0) {
 277                 /* We have a ready_irq, but it didn't fire in time. */
 278                 dev_err(wcnss->dev, "start timed out\n");
 279                 qcom_scm_pas_shutdown(WCNSS_PAS_ID);
 280                 ret = -ETIMEDOUT;
 281                 goto disable_iris;
 282         }
 283
 284         ret = 0;
 285
 286 disable_iris:
 287         qcom_iris_disable(wcnss->iris);
 288 disable_regulators:
 289         regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
 290 release_iris_lock:
 291         mutex_unlock(&wcnss->iris_lock);
 292
 293         return ret;
 294 }
 295
 296 static int wcnss_stop(struct rproc *rproc)
 297 {
 298         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 299         int ret;
 300
 301         if (wcnss->state) {
 302                 qcom_smem_state_update_bits(wcnss->state,
 303                                             BIT(wcnss->stop_bit),
 304                                             BIT(wcnss->stop_bit));
 305
 306                 ret = wait_for_completion_timeout(&wcnss->stop_done,
 307                                                   msecs_to_jiffies(5000));
 308                 if (ret == 0)
 309                         dev_err(wcnss->dev, "timed out on wait\n");
 310
 311                 qcom_smem_state_update_bits(wcnss->state,
 312                                             BIT(wcnss->stop_bit),
 313                                             0);
 314         }
 315
 316         ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
 317         if (ret)
 318                 dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);
 319
 320         return ret;
 321 }
 322
 323 static void *wcnss_da_to_va(struct rproc *rproc, u64 da, int len)
 324 {
 325         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 326         int offset;
 327
 328         offset = da - wcnss->mem_reloc;
 329         if (offset < 0 || offset + len > wcnss->mem_size)
 330                 return NULL;
 331
 332         return wcnss->mem_region + offset;
 333 }
 334
 335 static const struct rproc_ops wcnss_ops = {
 336         .start = wcnss_start,
 337         .stop = wcnss_stop,
 338         .da_to_va = wcnss_da_to_va,
 339 };
 340
 341 static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
 342 {
 343         struct qcom_wcnss *wcnss = dev;
 344
 345         rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);
 346         return IRQ_HANDLED;
 347 }
 348
 349 static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
 350 {
 351         struct qcom_wcnss *wcnss = dev;
 352         size_t len;
 353         char *msg;
 354
 355         msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
 356         if (!IS_ERR(msg) && len > 0 && msg[0])
 357                 dev_err(wcnss->dev, "fatal error received: %s\n", msg);
 358
 359         rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);
 360
 361         if (!IS_ERR(msg))
 362                 msg[0] = '\0';
 363
 364         return IRQ_HANDLED;
 365 }
 366
 367 static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
 368 {
 369         struct qcom_wcnss *wcnss = dev;
 370
 371         complete(&wcnss->start_done);
 372
 373         return IRQ_HANDLED;
 374 }
 375
 376 static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
 377 {
 378         /*
 379          * XXX: At this point we're supposed to release the resources that we
 380          * have been holding on behalf of the WCNSS. Unfortunately this
 381          * interrupt comes way before the other side seems to be done.
 382          *
 383          * So we're currently relying on the ready interrupt firing later then
 384          * this and we just disable the resources at the end of wcnss_start().
 385          */
 386
 387         return IRQ_HANDLED;
 388 }
 389
 390 static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
 391 {
 392         struct qcom_wcnss *wcnss = dev;
 393
 394         complete(&wcnss->stop_done);
 395         return IRQ_HANDLED;
 396 }
 397
 398 static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
 399                                  const struct wcnss_vreg_info *info,
 400                                  int num_vregs)
 401 {
 402         struct regulator_bulk_data *bulk;
 403         int ret;
 404         int i;
 405
 406         bulk = devm_kcalloc(wcnss->dev,
 407                             num_vregs, sizeof(struct regulator_bulk_data),
 408                             GFP_KERNEL);
 409         if (!bulk)
 410                 return -ENOMEM;
 411
 412         for (i = 0; i < num_vregs; i++)
 413                 bulk[i].supply = info[i].name;
 414
 415         ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
 416         if (ret)
 417                 return ret;
 418
 419         for (i = 0; i < num_vregs; i++) {
 420                 if (info[i].max_voltage)
 421                         regulator_set_voltage(bulk[i].consumer,
 422                                               info[i].min_voltage,
 423                                               info[i].max_voltage);
 424
 425                 if (info[i].load_uA)
 426                         regulator_set_load(bulk[i].consumer, info[i].load_uA);
 427         }
 428
 429         wcnss->vregs = bulk;
 430         wcnss->num_vregs = num_vregs;
 431
 432         return 0;
 433 }
 434
 435 static int wcnss_request_irq(struct qcom_wcnss *wcnss,
 436                              struct platform_device *pdev,
 437                              const char *name,
 438                              bool optional,
 439                              irq_handler_t thread_fn)
 440 {
 441         int ret;
 442
 443         ret = platform_get_irq_byname(pdev, name);
 444         if (ret < 0 && optional) {
 445                 dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
 446                 return 0;
 447         } else if (ret < 0) {
 448                 dev_err(&pdev->dev, "no %s IRQ defined\n", name);
 449                 return ret;
 450         }
 451
 452         ret = devm_request_threaded_irq(&pdev->dev, ret,
 453                                         NULL, thread_fn,
 454                                         IRQF_TRIGGER_RISING | IRQF_ONESHOT,
 455                                         "wcnss", wcnss);
 456         if (ret)
 457                 dev_err(&pdev->dev, "request %s IRQ failed\n", name);
 458         return ret;
 459 }
 460
 461 static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
 462 {
 463         struct device_node *node;
 464         struct resource r;
 465         int ret;
 466
 467         node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
 468         if (!node) {
 469                 dev_err(wcnss->dev, "no memory-region specified\n");
 470                 return -EINVAL;
 471         }
 472
 473         ret = of_address_to_resource(node, 0, &r);
 474         if (ret)
 475                 return ret;
 476
 477         wcnss->mem_phys = wcnss->mem_reloc = r.start;
 478         wcnss->mem_size = resource_size(&r);
 479         wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
 480         if (!wcnss->mem_region) {
 481                 dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
 482                         &r.start, wcnss->mem_size);
 483                 return -EBUSY;
 484         }
 485
 486         return 0;
 487 }
 488
 489 static int wcnss_probe(struct platform_device *pdev)
 490 {
 491         const struct wcnss_data *data;
 492         struct qcom_wcnss *wcnss;
 493         struct resource *res;
 494         struct rproc *rproc;
 495         void __iomem *mmio;
 496         int ret;
 497
 498         data = of_device_get_match_data(&pdev->dev);
 499
 500         if (!qcom_scm_is_available())
 501                 return -EPROBE_DEFER;
 502
 503         if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
 504                 dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
 505                 return -ENXIO;
 506         }
 507
 508         rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
 509                             WCNSS_FIRMWARE_NAME, sizeof(*wcnss));
 510         if (!rproc) {
 511                 dev_err(&pdev->dev, "unable to allocate remoteproc\n");
 512                 return -ENOMEM;
 513         }
 514
 515         rproc->fw_ops = &wcnss_fw_ops;
 516
 517         wcnss = (struct qcom_wcnss *)rproc->priv;
 518         wcnss->dev = &pdev->dev;
 519         wcnss->rproc = rproc;
 520         platform_set_drvdata(pdev, wcnss);
 521
 522         init_completion(&wcnss->start_done);
 523         init_completion(&wcnss->stop_done);
 524
 525         mutex_init(&wcnss->iris_lock);
 526
 527         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
 528         mmio = devm_ioremap_resource(&pdev->dev, res);
 529         if (!mmio) {
 530                 ret = -ENOMEM;
 531                 goto free_rproc;
 532         };
 533
 534         ret = wcnss_alloc_memory_region(wcnss);
 535         if (ret)
 536                 goto free_rproc;
 537
 538         wcnss->pmu_cfg = mmio + data->pmu_offset;
 539         wcnss->spare_out = mmio + data->spare_offset;
 540
 541         ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs);
 542         if (ret)
 543                 goto free_rproc;
 544
 545         ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
 546         if (ret < 0)
 547                 goto free_rproc;
 548         wcnss->wdog_irq = ret;
 549
 550         ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
 551         if (ret < 0)
 552                 goto free_rproc;
 553         wcnss->fatal_irq = ret;
 554
 555         ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
 556         if (ret < 0)
 557                 goto free_rproc;
 558         wcnss->ready_irq = ret;
 559
 560         ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
 561         if (ret < 0)
 562                 goto free_rproc;
 563         wcnss->handover_irq = ret;
 564
 565         ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
 566         if (ret < 0)
 567                 goto free_rproc;
 568         wcnss->stop_ack_irq = ret;
 569
 570         if (wcnss->stop_ack_irq) {
 571                 wcnss->state = qcom_smem_state_get(&pdev->dev, "stop",
 572                                                    &wcnss->stop_bit);
 573                 if (IS_ERR(wcnss->state)) {
 574                         ret = PTR_ERR(wcnss->state);
 575                         goto free_rproc;
 576                 }
 577         }
 578
 579         ret = rproc_add(rproc);
 580         if (ret)
 581                 goto free_rproc;
 582
 583         return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
 584
 585 free_rproc:
 586         rproc_put(rproc);
 587
 588         return ret;
 589 }
 590
 591 static int wcnss_remove(struct platform_device *pdev)
 592 {
 593         struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);
 594
 595         of_platform_depopulate(&pdev->dev);
 596
 597         qcom_smem_state_put(wcnss->state);
 598         rproc_del(wcnss->rproc);
 599         rproc_put(wcnss->rproc);
 600
 601         return 0;
 602 }
 603
 604 static const struct of_device_id wcnss_of_match[] = {
 605         { .compatible = "qcom,riva-pil", &riva_data },
 606         { .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
 607         { .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
 608         { },
 609 };
 610
 611 static struct platform_driver wcnss_driver = {
 612         .probe = wcnss_probe,
 613         .remove = wcnss_remove,
 614         .driver = {
 615                 .name = "qcom-wcnss-pil",
 616                 .of_match_table = wcnss_of_match,
 617         },
 618 };
 619
 620 module_platform_driver(wcnss_driver);