drivers/spi/spi-s3c64xx.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics Ltd.
   3  *      Jaswinder Singh <jassi.brar@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/dmaengine.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/gpio.h>
  32 #include <linux/of.h>
  33 #include <linux/of_gpio.h>
  34
  35 #include <linux/platform_data/spi-s3c64xx.h>
  36
  37 #ifdef CONFIG_S3C_DMA
  38 #include <mach/dma.h>
  39 #endif
  40
  41 #define MAX_SPI_PORTS           3
  42 #define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
  43
  44 /* Registers and bit-fields */
  45
  46 #define S3C64XX_SPI_CH_CFG              0x00
  47 #define S3C64XX_SPI_CLK_CFG             0x04
  48 #define S3C64XX_SPI_MODE_CFG    0x08
  49 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  50 #define S3C64XX_SPI_INT_EN              0x10
  51 #define S3C64XX_SPI_STATUS              0x14
  52 #define S3C64XX_SPI_TX_DATA             0x18
  53 #define S3C64XX_SPI_RX_DATA             0x1C
  54 #define S3C64XX_SPI_PACKET_CNT  0x20
  55 #define S3C64XX_SPI_PENDING_CLR 0x24
  56 #define S3C64XX_SPI_SWAP_CFG    0x28
  57 #define S3C64XX_SPI_FB_CLK              0x2C
  58
  59 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  60 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  61 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  62 #define S3C64XX_SPI_CPOL_L              (1<<3)
  63 #define S3C64XX_SPI_CPHA_B              (1<<2)
  64 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  65 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  66
  67 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  68 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  69 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  70 #define S3C64XX_SPI_PSR_MASK            0xff
  71
  72 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  73 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  74 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  75 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  76 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  77 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  78 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  79 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  80 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  81 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  82 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  83
  84 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  85 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  86
  87 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  88 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  89 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  90 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  91 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  92 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  93 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  94
  95 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  96 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  97 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  98 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  99 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
 100 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
 101
 102 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
 103
 104 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
 105 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 106 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 107 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 108 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 109
 110 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 111 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 112 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 113 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 114 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 115 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 116 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 117 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 118
 119 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 120
 121 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 122 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 123                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 124 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 125 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 126                                         FIFO_LVL_MASK(i))
 127
 128 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 129 #define S3C64XX_SPI_TRAILCNT_OFF        19
 130
 131 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 132
 133 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 134 #define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
 135
 136 #define RXBUSY    (1<<2)
 137 #define TXBUSY    (1<<3)
 138
 139 struct s3c64xx_spi_dma_data {
 140         struct dma_chan *ch;
 141         enum dma_transfer_direction direction;
 142         unsigned int dmach;
 143 };
 144
 145 /**
 146  * struct s3c64xx_spi_info - SPI Controller hardware info
 147  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 148  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 149  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 150  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 151  * @clk_from_cmu: True, if the controller does not include a clock mux and
 152  *      prescaler unit.
 153  *
 154  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 155  * differ in some aspects such as the size of the fifo and spi bus clock
 156  * setup. Such differences are specified to the driver using this structure
 157  * which is provided as driver data to the driver.
 158  */
 159 struct s3c64xx_spi_port_config {
 160         int     fifo_lvl_mask[MAX_SPI_PORTS];
 161         int     rx_lvl_offset;
 162         int     tx_st_done;
 163         int     quirks;
 164         bool    high_speed;
 165         bool    clk_from_cmu;
 166 };
 167
 168 /**
 169  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 170  * @clk: Pointer to the spi clock.
 171  * @src_clk: Pointer to the clock used to generate SPI signals.
 172  * @master: Pointer to the SPI Protocol master.
 173  * @cntrlr_info: Platform specific data for the controller this driver manages.
 174  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 175  * @lock: Controller specific lock.
 176  * @state: Set of FLAGS to indicate status.
 177  * @rx_dmach: Controller's DMA channel for Rx.
 178  * @tx_dmach: Controller's DMA channel for Tx.
 179  * @sfr_start: BUS address of SPI controller regs.
 180  * @regs: Pointer to ioremap'ed controller registers.
 181  * @irq: interrupt
 182  * @xfer_completion: To indicate completion of xfer task.
 183  * @cur_mode: Stores the active configuration of the controller.
 184  * @cur_bpw: Stores the active bits per word settings.
 185  * @cur_speed: Stores the active xfer clock speed.
 186  */
 187 struct s3c64xx_spi_driver_data {
 188         void __iomem                    *regs;
 189         struct clk                      *clk;
 190         struct clk                      *src_clk;
 191         struct platform_device          *pdev;
 192         struct spi_master               *master;
 193         struct s3c64xx_spi_info  *cntrlr_info;
 194         struct spi_device               *tgl_spi;
 195         spinlock_t                      lock;
 196         unsigned long                   sfr_start;
 197         struct completion               xfer_completion;
 198         unsigned                        state;
 199         unsigned                        cur_mode, cur_bpw;
 200         unsigned                        cur_speed;
 201         struct s3c64xx_spi_dma_data     rx_dma;
 202         struct s3c64xx_spi_dma_data     tx_dma;
 203 #ifdef CONFIG_S3C_DMA
 204         struct samsung_dma_ops          *ops;
 205 #endif
 206         struct s3c64xx_spi_port_config  *port_conf;
 207         unsigned int                    port_id;
 208         unsigned long                   gpios[4];
 209         bool                            cs_gpio;
 210 };
 211
 212 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 213 {
 214         void __iomem *regs = sdd->regs;
 215         unsigned long loops;
 216         u32 val;
 217
 218         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 219
 220         val = readl(regs + S3C64XX_SPI_CH_CFG);
 221         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 222         writel(val, regs + S3C64XX_SPI_CH_CFG);
 223
 224         val = readl(regs + S3C64XX_SPI_CH_CFG);
 225         val |= S3C64XX_SPI_CH_SW_RST;
 226         val &= ~S3C64XX_SPI_CH_HS_EN;
 227         writel(val, regs + S3C64XX_SPI_CH_CFG);
 228
 229         /* Flush TxFIFO*/
 230         loops = msecs_to_loops(1);
 231         do {
 232                 val = readl(regs + S3C64XX_SPI_STATUS);
 233         } while (TX_FIFO_LVL(val, sdd) && loops--);
 234
 235         if (loops == 0)
 236                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 237
 238         /* Flush RxFIFO*/
 239         loops = msecs_to_loops(1);
 240         do {
 241                 val = readl(regs + S3C64XX_SPI_STATUS);
 242                 if (RX_FIFO_LVL(val, sdd))
 243                         readl(regs + S3C64XX_SPI_RX_DATA);
 244                 else
 245                         break;
 246         } while (loops--);
 247
 248         if (loops == 0)
 249                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 250
 251         val = readl(regs + S3C64XX_SPI_CH_CFG);
 252         val &= ~S3C64XX_SPI_CH_SW_RST;
 253         writel(val, regs + S3C64XX_SPI_CH_CFG);
 254
 255         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 256         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 257         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 258 }
 259
 260 static void s3c64xx_spi_dmacb(void *data)
 261 {
 262         struct s3c64xx_spi_driver_data *sdd;
 263         struct s3c64xx_spi_dma_data *dma = data;
 264         unsigned long flags;
 265
 266         if (dma->direction == DMA_DEV_TO_MEM)
 267                 sdd = container_of(data,
 268                         struct s3c64xx_spi_driver_data, rx_dma);
 269         else
 270                 sdd = container_of(data,
 271                         struct s3c64xx_spi_driver_data, tx_dma);
 272
 273         spin_lock_irqsave(&sdd->lock, flags);
 274
 275         if (dma->direction == DMA_DEV_TO_MEM) {
 276                 sdd->state &= ~RXBUSY;
 277                 if (!(sdd->state & TXBUSY))
 278                         complete(&sdd->xfer_completion);
 279         } else {
 280                 sdd->state &= ~TXBUSY;
 281                 if (!(sdd->state & RXBUSY))
 282                         complete(&sdd->xfer_completion);
 283         }
 284
 285         spin_unlock_irqrestore(&sdd->lock, flags);
 286 }
 287
 288 #ifdef CONFIG_S3C_DMA
 289 /* FIXME: remove this section once arch/arm/mach-s3c64xx uses dmaengine */
 290
 291 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
 292         .name = "samsung-spi-dma",
 293 };
 294
 295 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 296                                         unsigned len, dma_addr_t buf)
 297 {
 298         struct s3c64xx_spi_driver_data *sdd;
 299         struct samsung_dma_prep info;
 300         struct samsung_dma_config config;
 301
 302         if (dma->direction == DMA_DEV_TO_MEM) {
 303                 sdd = container_of((void *)dma,
 304                         struct s3c64xx_spi_driver_data, rx_dma);
 305                 config.direction = sdd->rx_dma.direction;
 306                 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 307                 config.width = sdd->cur_bpw / 8;
 308                 sdd->ops->config((enum dma_ch)sdd->rx_dma.ch, &config);
 309         } else {
 310                 sdd = container_of((void *)dma,
 311                         struct s3c64xx_spi_driver_data, tx_dma);
 312                 config.direction =  sdd->tx_dma.direction;
 313                 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 314                 config.width = sdd->cur_bpw / 8;
 315                 sdd->ops->config((enum dma_ch)sdd->tx_dma.ch, &config);
 316         }
 317
 318         info.cap = DMA_SLAVE;
 319         info.len = len;
 320         info.fp = s3c64xx_spi_dmacb;
 321         info.fp_param = dma;
 322         info.direction = dma->direction;
 323         info.buf = buf;
 324
 325         sdd->ops->prepare((enum dma_ch)dma->ch, &info);
 326         sdd->ops->trigger((enum dma_ch)dma->ch);
 327 }
 328
 329 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
 330 {
 331         struct samsung_dma_req req;
 332         struct device *dev = &sdd->pdev->dev;
 333
 334         sdd->ops = samsung_dma_get_ops();
 335
 336         req.cap = DMA_SLAVE;
 337         req.client = &s3c64xx_spi_dma_client;
 338
 339         sdd->rx_dma.ch = (struct dma_chan *)(unsigned long)sdd->ops->request(
 340                                         sdd->rx_dma.dmach, &req, dev, "rx");
 341         sdd->tx_dma.ch = (struct dma_chan *)(unsigned long)sdd->ops->request(
 342                                         sdd->tx_dma.dmach, &req, dev, "tx");
 343
 344         return 1;
 345 }
 346
 347 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 348 {
 349         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 350
 351         /*
 352          * If DMA resource was not available during
 353          * probe, no need to continue with dma requests
 354          * else Acquire DMA channels
 355          */
 356         while (!is_polling(sdd) && !acquire_dma(sdd))
 357                 usleep_range(10000, 11000);
 358
 359         return 0;
 360 }
 361
 362 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 363 {
 364         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 365
 366         /* Free DMA channels */
 367         if (!is_polling(sdd)) {
 368                 sdd->ops->release((enum dma_ch)sdd->rx_dma.ch,
 369                                         &s3c64xx_spi_dma_client);
 370                 sdd->ops->release((enum dma_ch)sdd->tx_dma.ch,
 371                                         &s3c64xx_spi_dma_client);
 372         }
 373
 374         return 0;
 375 }
 376
 377 static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
 378                                  struct s3c64xx_spi_dma_data *dma)
 379 {
 380         sdd->ops->stop((enum dma_ch)dma->ch);
 381 }
 382 #else
 383
 384 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 385                                         unsigned len, dma_addr_t buf)
 386 {
 387         struct s3c64xx_spi_driver_data *sdd;
 388         struct dma_slave_config config;
 389         struct dma_async_tx_descriptor *desc;
 390
 391         memset(&config, 0, sizeof(config));
 392
 393         if (dma->direction == DMA_DEV_TO_MEM) {
 394                 sdd = container_of((void *)dma,
 395                         struct s3c64xx_spi_driver_data, rx_dma);
 396                 config.direction = dma->direction;
 397                 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 398                 config.src_addr_width = sdd->cur_bpw / 8;
 399                 config.src_maxburst = 1;
 400                 dmaengine_slave_config(dma->ch, &config);
 401         } else {
 402                 sdd = container_of((void *)dma,
 403                         struct s3c64xx_spi_driver_data, tx_dma);
 404                 config.direction = dma->direction;
 405                 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 406                 config.dst_addr_width = sdd->cur_bpw / 8;
 407                 config.dst_maxburst = 1;
 408                 dmaengine_slave_config(dma->ch, &config);
 409         }
 410
 411         desc = dmaengine_prep_slave_single(dma->ch, buf, len,
 412                                         dma->direction, DMA_PREP_INTERRUPT);
 413
 414         desc->callback = s3c64xx_spi_dmacb;
 415         desc->callback_param = dma;
 416
 417         dmaengine_submit(desc);
 418         dma_async_issue_pending(dma->ch);
 419 }
 420
 421 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 422 {
 423         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 424         dma_filter_fn filter = sdd->cntrlr_info->filter;
 425         struct device *dev = &sdd->pdev->dev;
 426         dma_cap_mask_t mask;
 427         int ret;
 428
 429         if (!is_polling(sdd)) {
 430                 dma_cap_zero(mask);
 431                 dma_cap_set(DMA_SLAVE, mask);
 432
 433                 /* Acquire DMA channels */
 434                 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
 435                                    (void *)sdd->rx_dma.dmach, dev, "rx");
 436                 if (!sdd->rx_dma.ch) {
 437                         dev_err(dev, "Failed to get RX DMA channel\n");
 438                         ret = -EBUSY;
 439                         goto out;
 440                 }
 441
 442                 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
 443                                    (void *)sdd->tx_dma.dmach, dev, "tx");
 444                 if (!sdd->tx_dma.ch) {
 445                         dev_err(dev, "Failed to get TX DMA channel\n");
 446                         ret = -EBUSY;
 447                         goto out_rx;
 448                 }
 449         }
 450
 451         ret = pm_runtime_get_sync(&sdd->pdev->dev);
 452         if (ret < 0) {
 453                 dev_err(dev, "Failed to enable device: %d\n", ret);
 454                 goto out_tx;
 455         }
 456
 457         return 0;
 458
 459 out_tx:
 460         dma_release_channel(sdd->tx_dma.ch);
 461 out_rx:
 462         dma_release_channel(sdd->rx_dma.ch);
 463 out:
 464         return ret;
 465 }
 466
 467 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 468 {
 469         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 470
 471         /* Free DMA channels */
 472         if (!is_polling(sdd)) {
 473                 dma_release_channel(sdd->rx_dma.ch);
 474                 dma_release_channel(sdd->tx_dma.ch);
 475         }
 476
 477         pm_runtime_put(&sdd->pdev->dev);
 478         return 0;
 479 }
 480
 481 static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
 482                                  struct s3c64xx_spi_dma_data *dma)
 483 {
 484         dmaengine_terminate_all(dma->ch);
 485 }
 486 #endif
 487
 488 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 489                                 struct spi_device *spi,
 490                                 struct spi_transfer *xfer, int dma_mode)
 491 {
 492         void __iomem *regs = sdd->regs;
 493         u32 modecfg, chcfg;
 494
 495         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 496         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 497
 498         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 499         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 500
 501         if (dma_mode) {
 502                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 503         } else {
 504                 /* Always shift in data in FIFO, even if xfer is Tx only,
 505                  * this helps setting PCKT_CNT value for generating clocks
 506                  * as exactly needed.
 507                  */
 508                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 509                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 510                                         | S3C64XX_SPI_PACKET_CNT_EN,
 511                                         regs + S3C64XX_SPI_PACKET_CNT);
 512         }
 513
 514         if (xfer->tx_buf != NULL) {
 515                 sdd->state |= TXBUSY;
 516                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 517                 if (dma_mode) {
 518                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 519                         prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
 520                 } else {
 521                         switch (sdd->cur_bpw) {
 522                         case 32:
 523                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 524                                         xfer->tx_buf, xfer->len / 4);
 525                                 break;
 526                         case 16:
 527                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 528                                         xfer->tx_buf, xfer->len / 2);
 529                                 break;
 530                         default:
 531                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 532                                         xfer->tx_buf, xfer->len);
 533                                 break;
 534                         }
 535                 }
 536         }
 537
 538         if (xfer->rx_buf != NULL) {
 539                 sdd->state |= RXBUSY;
 540
 541                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 542                                         && !(sdd->cur_mode & SPI_CPHA))
 543                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 544
 545                 if (dma_mode) {
 546                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 547                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 548                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 549                                         | S3C64XX_SPI_PACKET_CNT_EN,
 550                                         regs + S3C64XX_SPI_PACKET_CNT);
 551                         prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
 552                 }
 553         }
 554
 555         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 556         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 557 }
 558
 559 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 560                                                 struct spi_device *spi)
 561 {
 562         struct s3c64xx_spi_csinfo *cs;
 563
 564         if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
 565                 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 566                         /* Deselect the last toggled device */
 567                         cs = sdd->tgl_spi->controller_data;
 568                         if (sdd->cs_gpio)
 569                                 gpio_set_value(cs->line,
 570                                         spi->mode & SPI_CS_HIGH ? 0 : 1);
 571                 }
 572                 sdd->tgl_spi = NULL;
 573         }
 574
 575         cs = spi->controller_data;
 576         if (sdd->cs_gpio)
 577                 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
 578
 579         /* Start the signals */
 580         writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 581 }
 582
 583 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
 584                                         int timeout_ms)
 585 {
 586         void __iomem *regs = sdd->regs;
 587         unsigned long val = 1;
 588         u32 status;
 589
 590         /* max fifo depth available */
 591         u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
 592
 593         if (timeout_ms)
 594                 val = msecs_to_loops(timeout_ms);
 595
 596         do {
 597                 status = readl(regs + S3C64XX_SPI_STATUS);
 598         } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
 599
 600         /* return the actual received data length */
 601         return RX_FIFO_LVL(status, sdd);
 602 }
 603
 604 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 605                                 struct spi_transfer *xfer, int dma_mode)
 606 {
 607         void __iomem *regs = sdd->regs;
 608         unsigned long val;
 609         int ms;
 610
 611         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 612         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 613         ms += 10; /* some tolerance */
 614
 615         if (dma_mode) {
 616                 val = msecs_to_jiffies(ms) + 10;
 617                 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 618         } else {
 619                 u32 status;
 620                 val = msecs_to_loops(ms);
 621                 do {
 622                         status = readl(regs + S3C64XX_SPI_STATUS);
 623                 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 624         }
 625
 626         if (dma_mode) {
 627                 u32 status;
 628
 629                 /*
 630                  * If the previous xfer was completed within timeout, then
 631                  * proceed further else return -EIO.
 632                  * DmaTx returns after simply writing data in the FIFO,
 633                  * w/o waiting for real transmission on the bus to finish.
 634                  * DmaRx returns only after Dma read data from FIFO which
 635                  * needs bus transmission to finish, so we don't worry if
 636                  * Xfer involved Rx(with or without Tx).
 637                  */
 638                 if (val && !xfer->rx_buf) {
 639                         val = msecs_to_loops(10);
 640                         status = readl(regs + S3C64XX_SPI_STATUS);
 641                         while ((TX_FIFO_LVL(status, sdd)
 642                                 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 643                                         && --val) {
 644                                 cpu_relax();
 645                                 status = readl(regs + S3C64XX_SPI_STATUS);
 646                         }
 647
 648                 }
 649
 650                 /* If timed out while checking rx/tx status return error */
 651                 if (!val)
 652                         return -EIO;
 653         } else {
 654                 int loops;
 655                 u32 cpy_len;
 656                 u8 *buf;
 657
 658                 /* If it was only Tx */
 659                 if (!xfer->rx_buf) {
 660                         sdd->state &= ~TXBUSY;
 661                         return 0;
 662                 }
 663
 664                 /*
 665                  * If the receive length is bigger than the controller fifo
 666                  * size, calculate the loops and read the fifo as many times.
 667                  * loops = length / max fifo size (calculated by using the
 668                  * fifo mask).
 669                  * For any size less than the fifo size the below code is
 670                  * executed atleast once.
 671                  */
 672                 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
 673                 buf = xfer->rx_buf;
 674                 do {
 675                         /* wait for data to be received in the fifo */
 676                         cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
 677                                                 (loops ? ms : 0));
 678
 679                         switch (sdd->cur_bpw) {
 680                         case 32:
 681                                 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 682                                         buf, cpy_len / 4);
 683                                 break;
 684                         case 16:
 685                                 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 686                                         buf, cpy_len / 2);
 687                                 break;
 688                         default:
 689                                 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 690                                         buf, cpy_len);
 691                                 break;
 692                         }
 693
 694                         buf = buf + cpy_len;
 695                 } while (loops--);
 696                 sdd->state &= ~RXBUSY;
 697         }
 698
 699         return 0;
 700 }
 701
 702 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 703                                                 struct spi_device *spi)
 704 {
 705         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 706
 707         if (sdd->tgl_spi == spi)
 708                 sdd->tgl_spi = NULL;
 709
 710         if (sdd->cs_gpio)
 711                 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
 712
 713         /* Quiese the signals */
 714         writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 715 }
 716
 717 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 718 {
 719         void __iomem *regs = sdd->regs;
 720         u32 val;
 721
 722         /* Disable Clock */
 723         if (sdd->port_conf->clk_from_cmu) {
 724                 clk_disable_unprepare(sdd->src_clk);
 725         } else {
 726                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 727                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 728                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 729         }
 730
 731         /* Set Polarity and Phase */
 732         val = readl(regs + S3C64XX_SPI_CH_CFG);
 733         val &= ~(S3C64XX_SPI_CH_SLAVE |
 734                         S3C64XX_SPI_CPOL_L |
 735                         S3C64XX_SPI_CPHA_B);
 736
 737         if (sdd->cur_mode & SPI_CPOL)
 738                 val |= S3C64XX_SPI_CPOL_L;
 739
 740         if (sdd->cur_mode & SPI_CPHA)
 741                 val |= S3C64XX_SPI_CPHA_B;
 742
 743         writel(val, regs + S3C64XX_SPI_CH_CFG);
 744
 745         /* Set Channel & DMA Mode */
 746         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 747         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 748                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 749
 750         switch (sdd->cur_bpw) {
 751         case 32:
 752                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 753                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 754                 break;
 755         case 16:
 756                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 757                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 758                 break;
 759         default:
 760                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 761                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 762                 break;
 763         }
 764
 765         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 766
 767         if (sdd->port_conf->clk_from_cmu) {
 768                 /* Configure Clock */
 769                 /* There is half-multiplier before the SPI */
 770                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 771                 /* Enable Clock */
 772                 clk_prepare_enable(sdd->src_clk);
 773         } else {
 774                 /* Configure Clock */
 775                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 776                 val &= ~S3C64XX_SPI_PSR_MASK;
 777                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 778                                 & S3C64XX_SPI_PSR_MASK);
 779                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 780
 781                 /* Enable Clock */
 782                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 783                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 784                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 785         }
 786 }
 787
 788 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 789
 790 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 791                                                 struct spi_message *msg)
 792 {
 793         struct device *dev = &sdd->pdev->dev;
 794         struct spi_transfer *xfer;
 795
 796         if (is_polling(sdd) || msg->is_dma_mapped)
 797                 return 0;
 798
 799         /* First mark all xfer unmapped */
 800         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 801                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 802                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 803         }
 804
 805         /* Map until end or first fail */
 806         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 807
 808                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 809                         continue;
 810
 811                 if (xfer->tx_buf != NULL) {
 812                         xfer->tx_dma = dma_map_single(dev,
 813                                         (void *)xfer->tx_buf, xfer->len,
 814                                         DMA_TO_DEVICE);
 815                         if (dma_mapping_error(dev, xfer->tx_dma)) {
 816                                 dev_err(dev, "dma_map_single Tx failed\n");
 817                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 818                                 return -ENOMEM;
 819                         }
 820                 }
 821
 822                 if (xfer->rx_buf != NULL) {
 823                         xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
 824                                                 xfer->len, DMA_FROM_DEVICE);
 825                         if (dma_mapping_error(dev, xfer->rx_dma)) {
 826                                 dev_err(dev, "dma_map_single Rx failed\n");
 827                                 dma_unmap_single(dev, xfer->tx_dma,
 828                                                 xfer->len, DMA_TO_DEVICE);
 829                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 830                                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 831                                 return -ENOMEM;
 832                         }
 833                 }
 834         }
 835
 836         return 0;
 837 }
 838
 839 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 840                                                 struct spi_message *msg)
 841 {
 842         struct device *dev = &sdd->pdev->dev;
 843         struct spi_transfer *xfer;
 844
 845         if (is_polling(sdd) || msg->is_dma_mapped)
 846                 return;
 847
 848         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 849
 850                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 851                         continue;
 852
 853                 if (xfer->rx_buf != NULL
 854                                 && xfer->rx_dma != XFER_DMAADDR_INVALID)
 855                         dma_unmap_single(dev, xfer->rx_dma,
 856                                                 xfer->len, DMA_FROM_DEVICE);
 857
 858                 if (xfer->tx_buf != NULL
 859                                 && xfer->tx_dma != XFER_DMAADDR_INVALID)
 860                         dma_unmap_single(dev, xfer->tx_dma,
 861                                                 xfer->len, DMA_TO_DEVICE);
 862         }
 863 }
 864
 865 static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
 866                                             struct spi_message *msg)
 867 {
 868         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 869         struct spi_device *spi = msg->spi;
 870         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 871         struct spi_transfer *xfer;
 872         int status = 0, cs_toggle = 0;
 873         u32 speed;
 874         u8 bpw;
 875
 876         /* If Master's(controller) state differs from that needed by Slave */
 877         if (sdd->cur_speed != spi->max_speed_hz
 878                         || sdd->cur_mode != spi->mode
 879                         || sdd->cur_bpw != spi->bits_per_word) {
 880                 sdd->cur_bpw = spi->bits_per_word;
 881                 sdd->cur_speed = spi->max_speed_hz;
 882                 sdd->cur_mode = spi->mode;
 883                 s3c64xx_spi_config(sdd);
 884         }
 885
 886         /* Map all the transfers if needed */
 887         if (s3c64xx_spi_map_mssg(sdd, msg)) {
 888                 dev_err(&spi->dev,
 889                         "Xfer: Unable to map message buffers!\n");
 890                 status = -ENOMEM;
 891                 goto out;
 892         }
 893
 894         /* Configure feedback delay */
 895         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 896
 897         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 898
 899                 unsigned long flags;
 900                 int use_dma;
 901
 902                 INIT_COMPLETION(sdd->xfer_completion);
 903
 904                 /* Only BPW and Speed may change across transfers */
 905                 bpw = xfer->bits_per_word;
 906                 speed = xfer->speed_hz ? : spi->max_speed_hz;
 907
 908                 if (xfer->len % (bpw / 8)) {
 909                         dev_err(&spi->dev,
 910                                 "Xfer length(%u) not a multiple of word size(%u)\n",
 911                                 xfer->len, bpw / 8);
 912                         status = -EIO;
 913                         goto out;
 914                 }
 915
 916                 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 917                         sdd->cur_bpw = bpw;
 918                         sdd->cur_speed = speed;
 919                         s3c64xx_spi_config(sdd);
 920                 }
 921
 922                 /* Polling method for xfers not bigger than FIFO capacity */
 923                 use_dma = 0;
 924                 if (!is_polling(sdd) &&
 925                         (sdd->rx_dma.ch && sdd->tx_dma.ch &&
 926                         (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
 927                         use_dma = 1;
 928
 929                 spin_lock_irqsave(&sdd->lock, flags);
 930
 931                 /* Pending only which is to be done */
 932                 sdd->state &= ~RXBUSY;
 933                 sdd->state &= ~TXBUSY;
 934
 935                 enable_datapath(sdd, spi, xfer, use_dma);
 936
 937                 /* Slave Select */
 938                 enable_cs(sdd, spi);
 939
 940                 spin_unlock_irqrestore(&sdd->lock, flags);
 941
 942                 status = wait_for_xfer(sdd, xfer, use_dma);
 943
 944                 if (status) {
 945                         dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 946                                 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 947                                 (sdd->state & RXBUSY) ? 'f' : 'p',
 948                                 (sdd->state & TXBUSY) ? 'f' : 'p',
 949                                 xfer->len);
 950
 951                         if (use_dma) {
 952                                 if (xfer->tx_buf != NULL
 953                                                 && (sdd->state & TXBUSY))
 954                                         s3c64xx_spi_dma_stop(sdd, &sdd->tx_dma);
 955                                 if (xfer->rx_buf != NULL
 956                                                 && (sdd->state & RXBUSY))
 957                                         s3c64xx_spi_dma_stop(sdd, &sdd->rx_dma);
 958                         }
 959
 960                         goto out;
 961                 }
 962
 963                 if (xfer->delay_usecs)
 964                         udelay(xfer->delay_usecs);
 965
 966                 if (xfer->cs_change) {
 967                         /* Hint that the next mssg is gonna be
 968                            for the same device */
 969                         if (list_is_last(&xfer->transfer_list,
 970                                                 &msg->transfers))
 971                                 cs_toggle = 1;
 972                 }
 973
 974                 msg->actual_length += xfer->len;
 975
 976                 flush_fifo(sdd);
 977         }
 978
 979 out:
 980         if (!cs_toggle || status)
 981                 disable_cs(sdd, spi);
 982         else
 983                 sdd->tgl_spi = spi;
 984
 985         s3c64xx_spi_unmap_mssg(sdd, msg);
 986
 987         msg->status = status;
 988
 989         spi_finalize_current_message(master);
 990
 991         return 0;
 992 }
 993
 994 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 995                                 struct spi_device *spi)
 996 {
 997         struct s3c64xx_spi_csinfo *cs;
 998         struct device_node *slave_np, *data_np = NULL;
 999         struct s3c64xx_spi_driver_data *sdd;
1000         u32 fb_delay = 0;
1001
1002         sdd = spi_master_get_devdata(spi->master);
1003         slave_np = spi->dev.of_node;
1004         if (!slave_np) {
1005                 dev_err(&spi->dev, "device node not found\n");
1006                 return ERR_PTR(-EINVAL);
1007         }
1008
1009         data_np = of_get_child_by_name(slave_np, "controller-data");
1010         if (!data_np) {
1011                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
1012                 return ERR_PTR(-EINVAL);
1013         }
1014
1015         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
1016         if (!cs) {
1017                 dev_err(&spi->dev, "could not allocate memory for controller data\n");
1018                 of_node_put(data_np);
1019                 return ERR_PTR(-ENOMEM);
1020         }
1021
1022         /* The CS line is asserted/deasserted by the gpio pin */
1023         if (sdd->cs_gpio)
1024                 cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
1025
1026         if (!gpio_is_valid(cs->line)) {
1027                 dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
1028                 kfree(cs);
1029                 of_node_put(data_np);
1030                 return ERR_PTR(-EINVAL);
1031         }
1032
1033         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
1034         cs->fb_delay = fb_delay;
1035         of_node_put(data_np);
1036         return cs;
1037 }
1038
1039 /*
1040  * Here we only check the validity of requested configuration
1041  * and save the configuration in a local data-structure.
1042  * The controller is actually configured only just before we
1043  * get a message to transfer.
1044  */
1045 static int s3c64xx_spi_setup(struct spi_device *spi)
1046 {
1047         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
1048         struct s3c64xx_spi_driver_data *sdd;
1049         struct s3c64xx_spi_info *sci;
1050         int err;
1051
1052         sdd = spi_master_get_devdata(spi->master);
1053         if (!cs && spi->dev.of_node) {
1054                 cs = s3c64xx_get_slave_ctrldata(spi);
1055                 spi->controller_data = cs;
1056         }
1057
1058         if (IS_ERR_OR_NULL(cs)) {
1059                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
1060                 return -ENODEV;
1061         }
1062
1063         if (!spi_get_ctldata(spi)) {
1064                 /* Request gpio only if cs line is asserted by gpio pins */
1065                 if (sdd->cs_gpio) {
1066                         err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
1067                                         dev_name(&spi->dev));
1068                         if (err) {
1069                                 dev_err(&spi->dev,
1070                                         "Failed to get /CS gpio [%d]: %d\n",
1071                                         cs->line, err);
1072                                 goto err_gpio_req;
1073                         }
1074                 }
1075
1076                 spi_set_ctldata(spi, cs);
1077         }
1078
1079         sci = sdd->cntrlr_info;
1080
1081         pm_runtime_get_sync(&sdd->pdev->dev);
1082
1083         /* Check if we can provide the requested rate */
1084         if (!sdd->port_conf->clk_from_cmu) {
1085                 u32 psr, speed;
1086
1087                 /* Max possible */
1088                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
1089
1090                 if (spi->max_speed_hz > speed)
1091                         spi->max_speed_hz = speed;
1092
1093                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
1094                 psr &= S3C64XX_SPI_PSR_MASK;
1095                 if (psr == S3C64XX_SPI_PSR_MASK)
1096                         psr--;
1097
1098                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
1099                 if (spi->max_speed_hz < speed) {
1100                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
1101                                 psr++;
1102                         } else {
1103                                 err = -EINVAL;
1104                                 goto setup_exit;
1105                         }
1106                 }
1107
1108                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
1109                 if (spi->max_speed_hz >= speed) {
1110                         spi->max_speed_hz = speed;
1111                 } else {
1112                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
1113                                 spi->max_speed_hz);
1114                         err = -EINVAL;
1115                         goto setup_exit;
1116                 }
1117         }
1118
1119         pm_runtime_put(&sdd->pdev->dev);
1120         disable_cs(sdd, spi);
1121         return 0;
1122
1123 setup_exit:
1124         /* setup() returns with device de-selected */
1125         disable_cs(sdd, spi);
1126
1127         gpio_free(cs->line);
1128         spi_set_ctldata(spi, NULL);
1129
1130 err_gpio_req:
1131         if (spi->dev.of_node)
1132                 kfree(cs);
1133
1134         return err;
1135 }
1136
1137 static void s3c64xx_spi_cleanup(struct spi_device *spi)
1138 {
1139         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
1140         struct s3c64xx_spi_driver_data *sdd;
1141
1142         sdd = spi_master_get_devdata(spi->master);
1143         if (cs && sdd->cs_gpio) {
1144                 gpio_free(cs->line);
1145                 if (spi->dev.of_node)
1146                         kfree(cs);
1147         }
1148         spi_set_ctldata(spi, NULL);
1149 }
1150
1151 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
1152 {
1153         struct s3c64xx_spi_driver_data *sdd = data;
1154         struct spi_master *spi = sdd->master;
1155         unsigned int val, clr = 0;
1156
1157         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
1158
1159         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
1160                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
1161                 dev_err(&spi->dev, "RX overrun\n");
1162         }
1163         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
1164                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
1165                 dev_err(&spi->dev, "RX underrun\n");
1166         }
1167         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
1168                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
1169                 dev_err(&spi->dev, "TX overrun\n");
1170         }
1171         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
1172                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1173                 dev_err(&spi->dev, "TX underrun\n");
1174         }
1175
1176         /* Clear the pending irq by setting and then clearing it */
1177         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1178         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1179
1180         return IRQ_HANDLED;
1181 }
1182
1183 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1184 {
1185         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1186         void __iomem *regs = sdd->regs;
1187         unsigned int val;
1188
1189         sdd->cur_speed = 0;
1190
1191         writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1192
1193         /* Disable Interrupts - we use Polling if not DMA mode */
1194         writel(0, regs + S3C64XX_SPI_INT_EN);
1195
1196         if (!sdd->port_conf->clk_from_cmu)
1197                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1198                                 regs + S3C64XX_SPI_CLK_CFG);
1199         writel(0, regs + S3C64XX_SPI_MODE_CFG);
1200         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1201
1202         /* Clear any irq pending bits, should set and clear the bits */
1203         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1204                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1205                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1206                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1207         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1208         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
1209
1210         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1211
1212         val = readl(regs + S3C64XX_SPI_MODE_CFG);
1213         val &= ~S3C64XX_SPI_MODE_4BURST;
1214         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1215         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1216         writel(val, regs + S3C64XX_SPI_MODE_CFG);
1217
1218         flush_fifo(sdd);
1219 }
1220
1221 #ifdef CONFIG_OF
1222 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1223 {
1224         struct s3c64xx_spi_info *sci;
1225         u32 temp;
1226
1227         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1228         if (!sci) {
1229                 dev_err(dev, "memory allocation for spi_info failed\n");
1230                 return ERR_PTR(-ENOMEM);
1231         }
1232
1233         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1234                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1235                 sci->src_clk_nr = 0;
1236         } else {
1237                 sci->src_clk_nr = temp;
1238         }
1239
1240         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1241                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1242                 sci->num_cs = 1;
1243         } else {
1244                 sci->num_cs = temp;
1245         }
1246
1247         return sci;
1248 }
1249 #else
1250 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1251 {
1252         return dev_get_platdata(dev);
1253 }
1254 #endif
1255
1256 static const struct of_device_id s3c64xx_spi_dt_match[];
1257
1258 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1259                                                 struct platform_device *pdev)
1260 {
1261 #ifdef CONFIG_OF
1262         if (pdev->dev.of_node) {
1263                 const struct of_device_id *match;
1264                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1265                 return (struct s3c64xx_spi_port_config *)match->data;
1266         }
1267 #endif
1268         return (struct s3c64xx_spi_port_config *)
1269                          platform_get_device_id(pdev)->driver_data;
1270 }
1271
1272 static int s3c64xx_spi_probe(struct platform_device *pdev)
1273 {
1274         struct resource *mem_res;
1275         struct resource *res;
1276         struct s3c64xx_spi_driver_data *sdd;
1277         struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1278         struct spi_master *master;
1279         int ret, irq;
1280         char clk_name[16];
1281
1282         if (!sci && pdev->dev.of_node) {
1283                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1284                 if (IS_ERR(sci))
1285                         return PTR_ERR(sci);
1286         }
1287
1288         if (!sci) {
1289                 dev_err(&pdev->dev, "platform_data missing!\n");
1290                 return -ENODEV;
1291         }
1292
1293         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1294         if (mem_res == NULL) {
1295                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1296                 return -ENXIO;
1297         }
1298
1299         irq = platform_get_irq(pdev, 0);
1300         if (irq < 0) {
1301                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1302                 return irq;
1303         }
1304
1305         master = spi_alloc_master(&pdev->dev,
1306                                 sizeof(struct s3c64xx_spi_driver_data));
1307         if (master == NULL) {
1308                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1309                 return -ENOMEM;
1310         }
1311
1312         platform_set_drvdata(pdev, master);
1313
1314         sdd = spi_master_get_devdata(master);
1315         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1316         sdd->master = master;
1317         sdd->cntrlr_info = sci;
1318         sdd->pdev = pdev;
1319         sdd->sfr_start = mem_res->start;
1320         sdd->cs_gpio = true;
1321         if (pdev->dev.of_node) {
1322                 if (!of_find_property(pdev->dev.of_node, "cs-gpio", NULL))
1323                         sdd->cs_gpio = false;
1324
1325                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1326                 if (ret < 0) {
1327                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1328                                 ret);
1329                         goto err0;
1330                 }
1331                 sdd->port_id = ret;
1332         } else {
1333                 sdd->port_id = pdev->id;
1334         }
1335
1336         sdd->cur_bpw = 8;
1337
1338         if (!sdd->pdev->dev.of_node) {
1339                 res = platform_get_resource(pdev, IORESOURCE_DMA,  0);
1340                 if (!res) {
1341                         dev_warn(&pdev->dev, "Unable to get SPI tx dma resource. Switching to poll mode\n");
1342                         sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1343                 } else
1344                         sdd->tx_dma.dmach = res->start;
1345
1346                 res = platform_get_resource(pdev, IORESOURCE_DMA,  1);
1347                 if (!res) {
1348                         dev_warn(&pdev->dev, "Unable to get SPI rx dma resource. Switching to poll mode\n");
1349                         sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1350                 } else
1351                         sdd->rx_dma.dmach = res->start;
1352         }
1353
1354         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1355         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1356
1357         master->dev.of_node = pdev->dev.of_node;
1358         master->bus_num = sdd->port_id;
1359         master->setup = s3c64xx_spi_setup;
1360         master->cleanup = s3c64xx_spi_cleanup;
1361         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1362         master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1363         master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1364         master->num_chipselect = sci->num_cs;
1365         master->dma_alignment = 8;
1366         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1367                                         SPI_BPW_MASK(8);
1368         /* the spi->mode bits understood by this driver: */
1369         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1370         master->auto_runtime_pm = true;
1371
1372         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1373         if (IS_ERR(sdd->regs)) {
1374                 ret = PTR_ERR(sdd->regs);
1375                 goto err0;
1376         }
1377
1378         if (sci->cfg_gpio && sci->cfg_gpio()) {
1379                 dev_err(&pdev->dev, "Unable to config gpio\n");
1380                 ret = -EBUSY;
1381                 goto err0;
1382         }
1383
1384         /* Setup clocks */
1385         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1386         if (IS_ERR(sdd->clk)) {
1387                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1388                 ret = PTR_ERR(sdd->clk);
1389                 goto err0;
1390         }
1391
1392         if (clk_prepare_enable(sdd->clk)) {
1393                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1394                 ret = -EBUSY;
1395                 goto err0;
1396         }
1397
1398         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1399         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1400         if (IS_ERR(sdd->src_clk)) {
1401                 dev_err(&pdev->dev,
1402                         "Unable to acquire clock '%s'\n", clk_name);
1403                 ret = PTR_ERR(sdd->src_clk);
1404                 goto err2;
1405         }
1406
1407         if (clk_prepare_enable(sdd->src_clk)) {
1408                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1409                 ret = -EBUSY;
1410                 goto err2;
1411         }
1412
1413         /* Setup Deufult Mode */
1414         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1415
1416         spin_lock_init(&sdd->lock);
1417         init_completion(&sdd->xfer_completion);
1418
1419         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1420                                 "spi-s3c64xx", sdd);
1421         if (ret != 0) {
1422                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1423                         irq, ret);
1424                 goto err3;
1425         }
1426
1427         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1428                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1429                sdd->regs + S3C64XX_SPI_INT_EN);
1430
1431         pm_runtime_enable(&pdev->dev);
1432
1433         if (spi_register_master(master)) {
1434                 dev_err(&pdev->dev, "cannot register SPI master\n");
1435                 ret = -EBUSY;
1436                 goto err3;
1437         }
1438
1439         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1440                                         sdd->port_id, master->num_chipselect);
1441         dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tDMA=[Rx-%d, Tx-%d]\n",
1442                                         mem_res,
1443                                         sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1444
1445         return 0;
1446
1447 err3:
1448         clk_disable_unprepare(sdd->src_clk);
1449 err2:
1450         clk_disable_unprepare(sdd->clk);
1451 err0:
1452         spi_master_put(master);
1453
1454         return ret;
1455 }
1456
1457 static int s3c64xx_spi_remove(struct platform_device *pdev)
1458 {
1459         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1460         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1461
1462         pm_runtime_disable(&pdev->dev);
1463
1464         spi_unregister_master(master);
1465
1466         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1467
1468         clk_disable_unprepare(sdd->src_clk);
1469
1470         clk_disable_unprepare(sdd->clk);
1471
1472         spi_master_put(master);
1473
1474         return 0;
1475 }
1476
1477 #ifdef CONFIG_PM_SLEEP
1478 static int s3c64xx_spi_suspend(struct device *dev)
1479 {
1480         struct spi_master *master = dev_get_drvdata(dev);
1481         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1482
1483         spi_master_suspend(master);
1484
1485         /* Disable the clock */
1486         clk_disable_unprepare(sdd->src_clk);
1487         clk_disable_unprepare(sdd->clk);
1488
1489         sdd->cur_speed = 0; /* Output Clock is stopped */
1490
1491         return 0;
1492 }
1493
1494 static int s3c64xx_spi_resume(struct device *dev)
1495 {
1496         struct spi_master *master = dev_get_drvdata(dev);
1497         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1498         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1499
1500         if (sci->cfg_gpio)
1501                 sci->cfg_gpio();
1502
1503         /* Enable the clock */
1504         clk_prepare_enable(sdd->src_clk);
1505         clk_prepare_enable(sdd->clk);
1506
1507         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1508
1509         spi_master_resume(master);
1510
1511         return 0;
1512 }
1513 #endif /* CONFIG_PM_SLEEP */
1514
1515 #ifdef CONFIG_PM_RUNTIME
1516 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1517 {
1518         struct spi_master *master = dev_get_drvdata(dev);
1519         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1520
1521         clk_disable_unprepare(sdd->clk);
1522         clk_disable_unprepare(sdd->src_clk);
1523
1524         return 0;
1525 }
1526
1527 static int s3c64xx_spi_runtime_resume(struct device *dev)
1528 {
1529         struct spi_master *master = dev_get_drvdata(dev);
1530         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1531
1532         clk_prepare_enable(sdd->src_clk);
1533         clk_prepare_enable(sdd->clk);
1534
1535         return 0;
1536 }
1537 #endif /* CONFIG_PM_RUNTIME */
1538
1539 static const struct dev_pm_ops s3c64xx_spi_pm = {
1540         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1541         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1542                            s3c64xx_spi_runtime_resume, NULL)
1543 };
1544
1545 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1546         .fifo_lvl_mask  = { 0x7f },
1547         .rx_lvl_offset  = 13,
1548         .tx_st_done     = 21,
1549         .high_speed     = true,
1550 };
1551
1552 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1553         .fifo_lvl_mask  = { 0x7f, 0x7F },
1554         .rx_lvl_offset  = 13,
1555         .tx_st_done     = 21,
1556 };
1557
1558 static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1559         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1560         .rx_lvl_offset  = 15,
1561         .tx_st_done     = 25,
1562 };
1563
1564 static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1565         .fifo_lvl_mask  = { 0x7f, 0x7F },
1566         .rx_lvl_offset  = 13,
1567         .tx_st_done     = 21,
1568         .high_speed     = true,
1569 };
1570
1571 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1572         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1573         .rx_lvl_offset  = 15,
1574         .tx_st_done     = 25,
1575         .high_speed     = true,
1576 };
1577
1578 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1579         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1580         .rx_lvl_offset  = 15,
1581         .tx_st_done     = 25,
1582         .high_speed     = true,
1583         .clk_from_cmu   = true,
1584 };
1585
1586 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1587         .fifo_lvl_mask  = { 0x1ff },
1588         .rx_lvl_offset  = 15,
1589         .tx_st_done     = 25,
1590         .high_speed     = true,
1591         .clk_from_cmu   = true,
1592         .quirks         = S3C64XX_SPI_QUIRK_POLL,
1593 };
1594
1595 static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1596         {
1597                 .name           = "s3c2443-spi",
1598                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1599         }, {
1600                 .name           = "s3c6410-spi",
1601                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1602         }, {
1603                 .name           = "s5p64x0-spi",
1604                 .driver_data    = (kernel_ulong_t)&s5p64x0_spi_port_config,
1605         }, {
1606                 .name           = "s5pc100-spi",
1607                 .driver_data    = (kernel_ulong_t)&s5pc100_spi_port_config,
1608         }, {
1609                 .name           = "s5pv210-spi",
1610                 .driver_data    = (kernel_ulong_t)&s5pv210_spi_port_config,
1611         }, {
1612                 .name           = "exynos4210-spi",
1613                 .driver_data    = (kernel_ulong_t)&exynos4_spi_port_config,
1614         },
1615         { },
1616 };
1617
1618 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1619         { .compatible = "samsung,exynos4210-spi",
1620                         .data = (void *)&exynos4_spi_port_config,
1621         },
1622         { .compatible = "samsung,exynos5440-spi",
1623                         .data = (void *)&exynos5440_spi_port_config,
1624         },
1625         { },
1626 };
1627 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1628
1629 static struct platform_driver s3c64xx_spi_driver = {
1630         .driver = {
1631                 .name   = "s3c64xx-spi",
1632                 .owner = THIS_MODULE,
1633                 .pm = &s3c64xx_spi_pm,
1634                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1635         },
1636         .remove = s3c64xx_spi_remove,
1637         .id_table = s3c64xx_spi_driver_ids,
1638 };
1639 MODULE_ALIAS("platform:s3c64xx-spi");
1640
1641 static int __init s3c64xx_spi_init(void)
1642 {
1643         return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1644 }
1645 subsys_initcall(s3c64xx_spi_init);
1646
1647 static void __exit s3c64xx_spi_exit(void)
1648 {
1649         platform_driver_unregister(&s3c64xx_spi_driver);
1650 }
1651 module_exit(s3c64xx_spi_exit);
1652
1653 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1654 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1655 MODULE_LICENSE("GPL");