2 * lis3l02dq.c support STMicroelectronics LISD02DQ
3 * 3d 2g Linear Accelerometers via SPI
5 * Copyright (c) 2007 Jonathan Cameron <jic23@kernel.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 * 16 bit left justified mode used.
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/gpio.h>
18 #include <linux/of_gpio.h>
19 #include <linux/mutex.h>
20 #include <linux/device.h>
21 #include <linux/kernel.h>
22 #include <linux/spi/spi.h>
23 #include <linux/slab.h>
24 #include <linux/sysfs.h>
25 #include <linux/module.h>
27 #include <linux/iio/iio.h>
28 #include <linux/iio/sysfs.h>
29 #include <linux/iio/events.h>
30 #include <linux/iio/buffer.h>
32 #include "lis3l02dq.h"
34 /* At the moment the spi framework doesn't allow global setting of cs_change.
35 * It's in the likely to be added comment at the top of spi.h.
36 * This means that use cannot be made of spi_write etc.
38 /* direct copy of the irq_default_primary_handler */
39 #ifndef CONFIG_IIO_BUFFER
40 static irqreturn_t lis3l02dq_nobuffer(int irq, void *private)
42 return IRQ_WAKE_THREAD;
47 * lis3l02dq_spi_read_reg_8() - read single byte from a single register
48 * @indio_dev: iio_dev for this actual device
49 * @reg_address: the address of the register to be read
50 * @val: pass back the resulting value
52 int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
53 u8 reg_address, u8 *val)
55 struct lis3l02dq_state *st = iio_priv(indio_dev);
57 struct spi_transfer xfer = {
64 mutex_lock(&st->buf_lock);
65 st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
68 ret = spi_sync_transfer(st->us, &xfer, 1);
70 mutex_unlock(&st->buf_lock);
76 * lis3l02dq_spi_write_reg_8() - write single byte to a register
77 * @indio_dev: iio_dev for this device
78 * @reg_address: the address of the register to be written
79 * @val: the value to write
81 int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
86 struct lis3l02dq_state *st = iio_priv(indio_dev);
88 mutex_lock(&st->buf_lock);
89 st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
91 ret = spi_write(st->us, st->tx, 2);
92 mutex_unlock(&st->buf_lock);
98 * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
99 * @indio_dev: iio_dev for this device
100 * @lower_reg_address: the address of the lower of the two registers.
101 * Second register is assumed to have address one greater.
102 * @value: value to be written
104 static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
105 u8 lower_reg_address,
109 struct lis3l02dq_state *st = iio_priv(indio_dev);
110 struct spi_transfer xfers[] = { {
116 .tx_buf = st->tx + 2,
122 mutex_lock(&st->buf_lock);
123 st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
124 st->tx[1] = value & 0xFF;
125 st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
126 st->tx[3] = (value >> 8) & 0xFF;
128 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
129 mutex_unlock(&st->buf_lock);
134 static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
135 u8 lower_reg_address,
138 struct lis3l02dq_state *st = iio_priv(indio_dev);
141 struct spi_transfer xfers[] = { {
148 .tx_buf = st->tx + 2,
149 .rx_buf = st->rx + 2,
155 mutex_lock(&st->buf_lock);
156 st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
158 st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
161 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
163 dev_err(&st->us->dev, "problem when reading 16 bit register");
166 tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
170 mutex_unlock(&st->buf_lock);
174 enum lis3l02dq_rm_ind {
180 static u8 lis3l02dq_axis_map[3][3] = {
181 [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
182 LIS3L02DQ_REG_OUT_Y_L_ADDR,
183 LIS3L02DQ_REG_OUT_Z_L_ADDR },
184 [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
185 LIS3L02DQ_REG_GAIN_Y_ADDR,
186 LIS3L02DQ_REG_GAIN_Z_ADDR },
187 [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
188 LIS3L02DQ_REG_OFFSET_Y_ADDR,
189 LIS3L02DQ_REG_OFFSET_Z_ADDR }
192 static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
193 const struct iio_chan_spec *chan,
194 enum iio_event_type type,
195 enum iio_event_direction dir,
196 enum iio_event_info info,
201 ret = lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
207 static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
208 const struct iio_chan_spec *chan,
209 enum iio_event_type type,
210 enum iio_event_direction dir,
211 enum iio_event_info info,
216 return lis3l02dq_spi_write_reg_s16(indio_dev,
217 LIS3L02DQ_REG_THS_L_ADDR,
221 static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
222 struct iio_chan_spec const *chan,
227 int ret = -EINVAL, reg;
232 case IIO_CHAN_INFO_CALIBBIAS:
233 if (val > 255 || val < -256)
236 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
237 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
239 case IIO_CHAN_INFO_CALIBSCALE:
243 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
244 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
250 static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
251 struct iio_chan_spec const *chan,
262 case IIO_CHAN_INFO_RAW:
263 /* Take the iio_dev status lock */
264 mutex_lock(&indio_dev->mlock);
265 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
268 reg = lis3l02dq_axis_map
269 [LIS3L02DQ_ACCEL][chan->address];
270 ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
272 mutex_unlock(&indio_dev->mlock);
276 case IIO_CHAN_INFO_SCALE:
279 return IIO_VAL_INT_PLUS_MICRO;
280 case IIO_CHAN_INFO_CALIBSCALE:
281 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
282 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
285 /* to match with what previous code does */
289 case IIO_CHAN_INFO_CALIBBIAS:
290 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
291 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
292 /* to match with what previous code does */
300 static ssize_t lis3l02dq_read_frequency(struct device *dev,
301 struct device_attribute *attr,
304 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
308 ret = lis3l02dq_spi_read_reg_8(indio_dev,
309 LIS3L02DQ_REG_CTRL_1_ADDR,
313 t &= LIS3L02DQ_DEC_MASK;
315 case LIS3L02DQ_REG_CTRL_1_DF_128:
316 len = sprintf(buf, "280\n");
318 case LIS3L02DQ_REG_CTRL_1_DF_64:
319 len = sprintf(buf, "560\n");
321 case LIS3L02DQ_REG_CTRL_1_DF_32:
322 len = sprintf(buf, "1120\n");
324 case LIS3L02DQ_REG_CTRL_1_DF_8:
325 len = sprintf(buf, "4480\n");
331 static ssize_t lis3l02dq_write_frequency(struct device *dev,
332 struct device_attribute *attr,
336 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
341 ret = kstrtoul(buf, 10, &val);
345 mutex_lock(&indio_dev->mlock);
346 ret = lis3l02dq_spi_read_reg_8(indio_dev,
347 LIS3L02DQ_REG_CTRL_1_ADDR,
350 goto error_ret_mutex;
351 /* Wipe the bits clean */
352 t &= ~LIS3L02DQ_DEC_MASK;
355 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
358 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
361 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
364 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
368 goto error_ret_mutex;
371 ret = lis3l02dq_spi_write_reg_8(indio_dev,
372 LIS3L02DQ_REG_CTRL_1_ADDR,
376 mutex_unlock(&indio_dev->mlock);
378 return ret ? ret : len;
381 static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
383 struct lis3l02dq_state *st = iio_priv(indio_dev);
387 st->us->mode = SPI_MODE_3;
391 val = LIS3L02DQ_DEFAULT_CTRL1;
392 /* Write suitable defaults to ctrl1 */
393 ret = lis3l02dq_spi_write_reg_8(indio_dev,
394 LIS3L02DQ_REG_CTRL_1_ADDR,
397 dev_err(&st->us->dev, "problem with setup control register 1");
400 /* Repeat as sometimes doesn't work first time? */
401 ret = lis3l02dq_spi_write_reg_8(indio_dev,
402 LIS3L02DQ_REG_CTRL_1_ADDR,
405 dev_err(&st->us->dev, "problem with setup control register 1");
409 /* Read back to check this has worked acts as loose test of correct
411 ret = lis3l02dq_spi_read_reg_8(indio_dev,
412 LIS3L02DQ_REG_CTRL_1_ADDR,
414 if (ret || (valtest != val)) {
415 dev_err(&indio_dev->dev,
416 "device not playing ball %d %d\n", valtest, val);
421 val = LIS3L02DQ_DEFAULT_CTRL2;
422 ret = lis3l02dq_spi_write_reg_8(indio_dev,
423 LIS3L02DQ_REG_CTRL_2_ADDR,
426 dev_err(&st->us->dev, "problem with setup control register 2");
430 val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
431 ret = lis3l02dq_spi_write_reg_8(indio_dev,
432 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
435 dev_err(&st->us->dev, "problem with interrupt cfg register");
441 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
442 lis3l02dq_read_frequency,
443 lis3l02dq_write_frequency);
445 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
447 static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
449 struct iio_dev *indio_dev = private;
452 s64 timestamp = iio_get_time_ns();
454 lis3l02dq_spi_read_reg_8(indio_dev,
455 LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
458 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
459 iio_push_event(indio_dev,
460 IIO_MOD_EVENT_CODE(IIO_ACCEL,
467 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
468 iio_push_event(indio_dev,
469 IIO_MOD_EVENT_CODE(IIO_ACCEL,
476 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
477 iio_push_event(indio_dev,
478 IIO_MOD_EVENT_CODE(IIO_ACCEL,
485 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
486 iio_push_event(indio_dev,
487 IIO_MOD_EVENT_CODE(IIO_ACCEL,
494 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
495 iio_push_event(indio_dev,
496 IIO_MOD_EVENT_CODE(IIO_ACCEL,
503 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
504 iio_push_event(indio_dev,
505 IIO_MOD_EVENT_CODE(IIO_ACCEL,
512 /* Ack and allow for new interrupts */
513 lis3l02dq_spi_read_reg_8(indio_dev,
514 LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
520 static const struct iio_event_spec lis3l02dq_event[] = {
522 .type = IIO_EV_TYPE_THRESH,
523 .dir = IIO_EV_DIR_RISING,
524 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
525 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE),
527 .type = IIO_EV_TYPE_THRESH,
528 .dir = IIO_EV_DIR_FALLING,
529 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
530 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE),
534 #define LIS3L02DQ_CHAN(index, mod) \
539 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
540 BIT(IIO_CHAN_INFO_CALIBSCALE) | \
541 BIT(IIO_CHAN_INFO_CALIBBIAS), \
542 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
544 .scan_index = index, \
550 .event_spec = lis3l02dq_event, \
551 .num_event_specs = ARRAY_SIZE(lis3l02dq_event), \
554 static const struct iio_chan_spec lis3l02dq_channels[] = {
555 LIS3L02DQ_CHAN(0, IIO_MOD_X),
556 LIS3L02DQ_CHAN(1, IIO_MOD_Y),
557 LIS3L02DQ_CHAN(2, IIO_MOD_Z),
558 IIO_CHAN_SOFT_TIMESTAMP(3)
561 static int lis3l02dq_read_event_config(struct iio_dev *indio_dev,
562 const struct iio_chan_spec *chan,
563 enum iio_event_type type,
564 enum iio_event_direction dir)
568 u8 mask = (1 << (chan->channel2*2 + (dir == IIO_EV_DIR_RISING)));
570 ret = lis3l02dq_spi_read_reg_8(indio_dev,
571 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
576 return !!(val & mask);
579 int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
584 ret = lis3l02dq_spi_read_reg_8(indio_dev,
585 LIS3L02DQ_REG_CTRL_2_ADDR,
588 control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
589 ret = lis3l02dq_spi_write_reg_8(indio_dev,
590 LIS3L02DQ_REG_CTRL_2_ADDR,
594 /* Also for consistency clear the mask */
595 ret = lis3l02dq_spi_read_reg_8(indio_dev,
596 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
602 ret = lis3l02dq_spi_write_reg_8(indio_dev,
603 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
613 static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
614 const struct iio_chan_spec *chan,
615 enum iio_event_type type,
616 enum iio_event_direction dir,
622 bool changed = false;
623 u8 mask = (1 << (chan->channel2*2 + (dir == IIO_EV_DIR_RISING)));
625 mutex_lock(&indio_dev->mlock);
626 /* read current control */
627 ret = lis3l02dq_spi_read_reg_8(indio_dev,
628 LIS3L02DQ_REG_CTRL_2_ADDR,
632 ret = lis3l02dq_spi_read_reg_8(indio_dev,
633 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
637 currentlyset = val & mask;
639 if (!currentlyset && state) {
642 } else if (currentlyset && !state) {
648 ret = lis3l02dq_spi_write_reg_8(indio_dev,
649 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
653 control = val & 0x3f ?
654 (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
655 (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
656 ret = lis3l02dq_spi_write_reg_8(indio_dev,
657 LIS3L02DQ_REG_CTRL_2_ADDR,
664 mutex_unlock(&indio_dev->mlock);
668 static struct attribute *lis3l02dq_attributes[] = {
669 &iio_dev_attr_sampling_frequency.dev_attr.attr,
670 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
674 static const struct attribute_group lis3l02dq_attribute_group = {
675 .attrs = lis3l02dq_attributes,
678 static const struct iio_info lis3l02dq_info = {
679 .read_raw = &lis3l02dq_read_raw,
680 .write_raw = &lis3l02dq_write_raw,
681 .read_event_value = &lis3l02dq_read_thresh,
682 .write_event_value = &lis3l02dq_write_thresh,
683 .write_event_config = &lis3l02dq_write_event_config,
684 .read_event_config = &lis3l02dq_read_event_config,
685 .driver_module = THIS_MODULE,
686 .attrs = &lis3l02dq_attribute_group,
689 static int lis3l02dq_probe(struct spi_device *spi)
692 struct lis3l02dq_state *st;
693 struct iio_dev *indio_dev;
695 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
698 st = iio_priv(indio_dev);
699 /* this is only used for removal purposes */
700 spi_set_drvdata(spi, indio_dev);
703 st->gpio = of_get_gpio(spi->dev.of_node, 0);
704 mutex_init(&st->buf_lock);
705 indio_dev->name = spi->dev.driver->name;
706 indio_dev->dev.parent = &spi->dev;
707 indio_dev->info = &lis3l02dq_info;
708 indio_dev->channels = lis3l02dq_channels;
709 indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
711 indio_dev->modes = INDIO_DIRECT_MODE;
713 ret = lis3l02dq_configure_buffer(indio_dev);
718 ret = request_threaded_irq(st->us->irq,
720 &lis3l02dq_event_handler,
725 goto error_unreg_buffer_funcs;
727 ret = lis3l02dq_probe_trigger(indio_dev);
729 goto error_free_interrupt;
732 /* Get the device into a sane initial state */
733 ret = lis3l02dq_initial_setup(indio_dev);
735 goto error_remove_trigger;
737 ret = iio_device_register(indio_dev);
739 goto error_remove_trigger;
743 error_remove_trigger:
745 lis3l02dq_remove_trigger(indio_dev);
746 error_free_interrupt:
748 free_irq(st->us->irq, indio_dev);
749 error_unreg_buffer_funcs:
750 lis3l02dq_unconfigure_buffer(indio_dev);
754 /* Power down the device */
755 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
758 struct lis3l02dq_state *st = iio_priv(indio_dev);
761 mutex_lock(&indio_dev->mlock);
762 ret = lis3l02dq_spi_write_reg_8(indio_dev,
763 LIS3L02DQ_REG_CTRL_1_ADDR,
766 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
770 ret = lis3l02dq_spi_write_reg_8(indio_dev,
771 LIS3L02DQ_REG_CTRL_2_ADDR,
774 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
776 mutex_unlock(&indio_dev->mlock);
780 /* fixme, confirm ordering in this function */
781 static int lis3l02dq_remove(struct spi_device *spi)
783 struct iio_dev *indio_dev = spi_get_drvdata(spi);
784 struct lis3l02dq_state *st = iio_priv(indio_dev);
786 iio_device_unregister(indio_dev);
788 lis3l02dq_disable_all_events(indio_dev);
789 lis3l02dq_stop_device(indio_dev);
792 free_irq(st->us->irq, indio_dev);
794 lis3l02dq_remove_trigger(indio_dev);
795 lis3l02dq_unconfigure_buffer(indio_dev);
800 static struct spi_driver lis3l02dq_driver = {
804 .probe = lis3l02dq_probe,
805 .remove = lis3l02dq_remove,
807 module_spi_driver(lis3l02dq_driver);
809 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
810 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
811 MODULE_LICENSE("GPL v2");
812 MODULE_ALIAS("spi:lis3l02dq");