1 #include <linux/interrupt.h>
2 #include <linux/gpio.h>
3 #include <linux/mutex.h>
4 #include <linux/kernel.h>
5 #include <linux/spi/spi.h>
6 #include <linux/slab.h>
7 #include <linux/export.h>
9 #include <linux/iio/iio.h>
10 #include "../ring_sw.h"
11 #include <linux/iio/kfifo_buf.h>
12 #include <linux/iio/trigger.h>
13 #include <linux/iio/trigger_consumer.h>
14 #include "lis3l02dq.h"
17 * combine_8_to_16() utility function to munge two u8s into u16
19 static inline u16 combine_8_to_16(u8 lower, u8 upper)
23 return _lower | (_upper << 8);
27 * lis3l02dq_data_rdy_trig_poll() the event handler for the data rdy trig
29 irqreturn_t lis3l02dq_data_rdy_trig_poll(int irq, void *private)
31 struct iio_dev *indio_dev = private;
32 struct lis3l02dq_state *st = iio_priv(indio_dev);
35 iio_trigger_poll(st->trig, iio_get_time_ns());
38 return IRQ_WAKE_THREAD;
41 static const u8 read_all_tx_array[] = {
42 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_L_ADDR), 0,
43 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_H_ADDR), 0,
44 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_L_ADDR), 0,
45 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_H_ADDR), 0,
46 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_L_ADDR), 0,
47 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_H_ADDR), 0,
51 * lis3l02dq_read_all() Reads all channels currently selected
52 * @indio_dev: IIO device state
53 * @rx_array: (dma capable) receive array, must be at least
54 * 4*number of channels
56 static int lis3l02dq_read_all(struct iio_dev *indio_dev, u8 *rx_array)
58 struct lis3l02dq_state *st = iio_priv(indio_dev);
59 struct spi_transfer *xfers;
60 struct spi_message msg;
63 xfers = kcalloc(bitmap_weight(indio_dev->active_scan_mask,
64 indio_dev->masklength) * 2,
65 sizeof(*xfers), GFP_KERNEL);
69 mutex_lock(&st->buf_lock);
71 for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++)
72 if (test_bit(i, indio_dev->active_scan_mask)) {
74 xfers[j].tx_buf = st->tx + 2*j;
75 st->tx[2*j] = read_all_tx_array[i*4];
78 xfers[j].rx_buf = rx_array + j*2;
79 xfers[j].bits_per_word = 8;
81 xfers[j].cs_change = 1;
85 xfers[j].tx_buf = st->tx + 2*j;
86 st->tx[2*j] = read_all_tx_array[i*4 + 2];
89 xfers[j].rx_buf = rx_array + j*2;
90 xfers[j].bits_per_word = 8;
92 xfers[j].cs_change = 1;
96 /* After these are transmitted, the rx_buff should have
97 * values in alternate bytes
99 spi_message_init(&msg);
100 for (j = 0; j < bitmap_weight(indio_dev->active_scan_mask,
101 indio_dev->masklength) * 2; j++)
102 spi_message_add_tail(&xfers[j], &msg);
104 ret = spi_sync(st->us, &msg);
105 mutex_unlock(&st->buf_lock);
111 static int lis3l02dq_get_buffer_element(struct iio_dev *indio_dev,
116 s16 *data = (s16 *)buf;
117 int scan_count = bitmap_weight(indio_dev->active_scan_mask,
118 indio_dev->masklength);
120 rx_array = kzalloc(4 * scan_count, GFP_KERNEL);
121 if (rx_array == NULL)
123 ret = lis3l02dq_read_all(indio_dev, rx_array);
128 for (i = 0; i < scan_count; i++)
129 data[i] = combine_8_to_16(rx_array[i*4+1],
133 return i*sizeof(data[0]);
136 static irqreturn_t lis3l02dq_trigger_handler(int irq, void *p)
138 struct iio_poll_func *pf = p;
139 struct iio_dev *indio_dev = pf->indio_dev;
140 struct iio_buffer *buffer = indio_dev->buffer;
144 data = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
146 dev_err(indio_dev->dev.parent,
147 "memory alloc failed in buffer bh");
151 if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
152 len = lis3l02dq_get_buffer_element(indio_dev, data);
154 /* Guaranteed to be aligned with 8 byte boundary */
155 if (indio_dev->scan_timestamp)
156 *(s64 *)((u8 *)data + ALIGN(len, sizeof(s64)))
158 buffer->access->store_to(buffer, (u8 *)data, pf->timestamp);
162 iio_trigger_notify_done(indio_dev->trig);
166 /* Caller responsible for locking as necessary. */
168 __lis3l02dq_write_data_ready_config(struct iio_dev *indio_dev, bool state)
173 struct lis3l02dq_state *st = iio_priv(indio_dev);
175 /* Get the current event mask register */
176 ret = lis3l02dq_spi_read_reg_8(indio_dev,
177 LIS3L02DQ_REG_CTRL_2_ADDR,
181 /* Find out if data ready is already on */
183 = valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
185 /* Disable requested */
186 if (!state && currentlyset) {
187 /* Disable the data ready signal */
188 valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
190 /* The double write is to overcome a hardware bug? */
191 ret = lis3l02dq_spi_write_reg_8(indio_dev,
192 LIS3L02DQ_REG_CTRL_2_ADDR,
196 ret = lis3l02dq_spi_write_reg_8(indio_dev,
197 LIS3L02DQ_REG_CTRL_2_ADDR,
201 st->trigger_on = false;
202 /* Enable requested */
203 } else if (state && !currentlyset) {
204 /* If not set, enable requested
205 * first disable all events */
206 ret = lis3l02dq_disable_all_events(indio_dev);
211 LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
213 st->trigger_on = true;
214 ret = lis3l02dq_spi_write_reg_8(indio_dev,
215 LIS3L02DQ_REG_CTRL_2_ADDR,
227 * lis3l02dq_data_rdy_trigger_set_state() set datardy interrupt state
229 * If disabling the interrupt also does a final read to ensure it is clear.
230 * This is only important in some cases where the scan enable elements are
231 * switched before the buffer is reenabled.
233 static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
236 struct iio_dev *indio_dev = trig->private_data;
240 __lis3l02dq_write_data_ready_config(indio_dev, state);
241 if (state == false) {
243 * A possible quirk with the handler is currently worked around
244 * by ensuring outstanding read events are cleared.
246 ret = lis3l02dq_read_all(indio_dev, NULL);
248 lis3l02dq_spi_read_reg_8(indio_dev,
249 LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
255 * lis3l02dq_trig_try_reen() try reenabling irq for data rdy trigger
256 * @trig: the datardy trigger
258 static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
260 struct iio_dev *indio_dev = trig->private_data;
261 struct lis3l02dq_state *st = iio_priv(indio_dev);
264 /* If gpio still high (or high again)
265 * In theory possible we will need to do this several times */
266 for (i = 0; i < 5; i++)
267 if (gpio_get_value(irq_to_gpio(st->us->irq)))
268 lis3l02dq_read_all(indio_dev, NULL);
273 "Failed to clear the interrupt for lis3l02dq\n");
275 /* irq reenabled so success! */
279 static const struct iio_trigger_ops lis3l02dq_trigger_ops = {
280 .owner = THIS_MODULE,
281 .set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state,
282 .try_reenable = &lis3l02dq_trig_try_reen,
285 int lis3l02dq_probe_trigger(struct iio_dev *indio_dev)
288 struct lis3l02dq_state *st = iio_priv(indio_dev);
290 st->trig = iio_trigger_alloc("lis3l02dq-dev%d", indio_dev->id);
296 st->trig->dev.parent = &st->us->dev;
297 st->trig->ops = &lis3l02dq_trigger_ops;
298 st->trig->private_data = indio_dev;
299 ret = iio_trigger_register(st->trig);
301 goto error_free_trig;
306 iio_trigger_free(st->trig);
311 void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
313 struct lis3l02dq_state *st = iio_priv(indio_dev);
315 iio_trigger_unregister(st->trig);
316 iio_trigger_free(st->trig);
319 void lis3l02dq_unconfigure_buffer(struct iio_dev *indio_dev)
321 iio_dealloc_pollfunc(indio_dev->pollfunc);
322 lis3l02dq_free_buf(indio_dev->buffer);
325 static int lis3l02dq_buffer_postenable(struct iio_dev *indio_dev)
327 /* Disable unwanted channels otherwise the interrupt will not clear */
330 bool oneenabled = false;
332 ret = lis3l02dq_spi_read_reg_8(indio_dev,
333 LIS3L02DQ_REG_CTRL_1_ADDR,
338 if (test_bit(0, indio_dev->active_scan_mask)) {
339 t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
342 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
343 if (test_bit(1, indio_dev->active_scan_mask)) {
344 t |= LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
347 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
348 if (test_bit(2, indio_dev->active_scan_mask)) {
349 t |= LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
352 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
354 if (!oneenabled) /* what happens in this case is unknown */
356 ret = lis3l02dq_spi_write_reg_8(indio_dev,
357 LIS3L02DQ_REG_CTRL_1_ADDR,
362 return iio_triggered_buffer_postenable(indio_dev);
367 /* Turn all channels on again */
368 static int lis3l02dq_buffer_predisable(struct iio_dev *indio_dev)
373 ret = iio_triggered_buffer_predisable(indio_dev);
377 ret = lis3l02dq_spi_read_reg_8(indio_dev,
378 LIS3L02DQ_REG_CTRL_1_ADDR,
382 t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE |
383 LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE |
384 LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
386 ret = lis3l02dq_spi_write_reg_8(indio_dev,
387 LIS3L02DQ_REG_CTRL_1_ADDR,
394 static const struct iio_buffer_setup_ops lis3l02dq_buffer_setup_ops = {
395 .preenable = &iio_sw_buffer_preenable,
396 .postenable = &lis3l02dq_buffer_postenable,
397 .predisable = &lis3l02dq_buffer_predisable,
400 int lis3l02dq_configure_buffer(struct iio_dev *indio_dev)
403 struct iio_buffer *buffer;
405 buffer = lis3l02dq_alloc_buf(indio_dev);
409 indio_dev->buffer = buffer;
411 buffer->scan_timestamp = true;
412 indio_dev->setup_ops = &lis3l02dq_buffer_setup_ops;
414 /* Functions are NULL as we set handler below */
415 indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
416 &lis3l02dq_trigger_handler,
419 "lis3l02dq_consumer%d",
422 if (indio_dev->pollfunc == NULL) {
424 goto error_iio_sw_rb_free;
427 indio_dev->modes |= INDIO_BUFFER_TRIGGERED;
430 error_iio_sw_rb_free:
431 lis3l02dq_free_buf(indio_dev->buffer);