drivers/staging/iio/frequency/ad9832.c

   1 /*
   2  * AD9832 SPI DDS driver
   3  *
   4  * Copyright 2011 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2.
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/sysfs.h>
  13 #include <linux/spi/spi.h>
  14 #include <linux/regulator/consumer.h>
  15 #include <linux/err.h>
  16 #include <linux/module.h>
  17 #include <asm/div64.h>
  18
  19 #include <linux/iio/iio.h>
  20 #include <linux/iio/sysfs.h>
  21 #include "dds.h"
  22
  23 #include "ad9832.h"
  24
  25 static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
  26 {
  27         unsigned long long freqreg = (u64)fout *
  28                                      (u64)((u64)1L << AD9832_FREQ_BITS);
  29         do_div(freqreg, mclk);
  30         return freqreg;
  31 }
  32
  33 static int ad9832_write_frequency(struct ad9832_state *st,
  34                                   unsigned addr, unsigned long fout)
  35 {
  36         unsigned long regval;
  37
  38         if (fout > (st->mclk / 2))
  39                 return -EINVAL;
  40
  41         regval = ad9832_calc_freqreg(st->mclk, fout);
  42
  43         st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
  44                                         (addr << ADD_SHIFT) |
  45                                         ((regval >> 24) & 0xFF));
  46         st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
  47                                         ((addr - 1) << ADD_SHIFT) |
  48                                         ((regval >> 16) & 0xFF));
  49         st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
  50                                         ((addr - 2) << ADD_SHIFT) |
  51                                         ((regval >> 8) & 0xFF));
  52         st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
  53                                         ((addr - 3) << ADD_SHIFT) |
  54                                         ((regval >> 0) & 0xFF));
  55
  56         return spi_sync(st->spi, &st->freq_msg);
  57 }
  58
  59 static int ad9832_write_phase(struct ad9832_state *st,
  60                               unsigned long addr, unsigned long phase)
  61 {
  62         if (phase > BIT(AD9832_PHASE_BITS))
  63                 return -EINVAL;
  64
  65         st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
  66                                         (addr << ADD_SHIFT) |
  67                                         ((phase >> 8) & 0xFF));
  68         st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
  69                                         ((addr - 1) << ADD_SHIFT) |
  70                                         (phase & 0xFF));
  71
  72         return spi_sync(st->spi, &st->phase_msg);
  73 }
  74
  75 static ssize_t ad9832_write(struct device *dev, struct device_attribute *attr,
  76                             const char *buf, size_t len)
  77 {
  78         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  79         struct ad9832_state *st = iio_priv(indio_dev);
  80         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
  81         int ret;
  82         unsigned long val;
  83
  84         ret = kstrtoul(buf, 10, &val);
  85         if (ret)
  86                 goto error_ret;
  87
  88         mutex_lock(&indio_dev->mlock);
  89         switch ((u32)this_attr->address) {
  90         case AD9832_FREQ0HM:
  91         case AD9832_FREQ1HM:
  92                 ret = ad9832_write_frequency(st, this_attr->address, val);
  93                 break;
  94         case AD9832_PHASE0H:
  95         case AD9832_PHASE1H:
  96         case AD9832_PHASE2H:
  97         case AD9832_PHASE3H:
  98                 ret = ad9832_write_phase(st, this_attr->address, val);
  99                 break;
 100         case AD9832_PINCTRL_EN:
 101                 if (val)
 102                         st->ctrl_ss &= ~AD9832_SELSRC;
 103                 else
 104                         st->ctrl_ss |= AD9832_SELSRC;
 105                 st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
 106                                         st->ctrl_ss);
 107                 ret = spi_sync(st->spi, &st->msg);
 108                 break;
 109         case AD9832_FREQ_SYM:
 110                 if (val == 1) {
 111                         st->ctrl_fp |= AD9832_FREQ;
 112                 } else if (val == 0) {
 113                         st->ctrl_fp &= ~AD9832_FREQ;
 114                 } else {
 115                         ret = -EINVAL;
 116                         break;
 117                 }
 118                 st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
 119                                         st->ctrl_fp);
 120                 ret = spi_sync(st->spi, &st->msg);
 121                 break;
 122         case AD9832_PHASE_SYM:
 123                 if (val > 3) {
 124                         ret = -EINVAL;
 125                         break;
 126                 }
 127
 128                 st->ctrl_fp &= ~AD9832_PHASE(3);
 129                 st->ctrl_fp |= AD9832_PHASE(val);
 130
 131                 st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
 132                                         st->ctrl_fp);
 133                 ret = spi_sync(st->spi, &st->msg);
 134                 break;
 135         case AD9832_OUTPUT_EN:
 136                 if (val)
 137                         st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP |
 138                                         AD9832_CLR);
 139                 else
 140                         st->ctrl_src |= AD9832_RESET;
 141
 142                 st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
 143                                         st->ctrl_src);
 144                 ret = spi_sync(st->spi, &st->msg);
 145                 break;
 146         default:
 147                 ret = -ENODEV;
 148         }
 149         mutex_unlock(&indio_dev->mlock);
 150
 151 error_ret:
 152         return ret ? ret : len;
 153 }
 154
 155 /**
 156  * see dds.h for further information
 157  */
 158
 159 static IIO_DEV_ATTR_FREQ(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ0HM);
 160 static IIO_DEV_ATTR_FREQ(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_FREQ1HM);
 161 static IIO_DEV_ATTR_FREQSYMBOL(0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ_SYM);
 162 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
 163
 164 static IIO_DEV_ATTR_PHASE(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_PHASE0H);
 165 static IIO_DEV_ATTR_PHASE(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_PHASE1H);
 166 static IIO_DEV_ATTR_PHASE(0, 2, S_IWUSR, NULL, ad9832_write, AD9832_PHASE2H);
 167 static IIO_DEV_ATTR_PHASE(0, 3, S_IWUSR, NULL, ad9832_write, AD9832_PHASE3H);
 168 static IIO_DEV_ATTR_PHASESYMBOL(0, S_IWUSR, NULL,
 169                                 ad9832_write, AD9832_PHASE_SYM);
 170 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
 171
 172 static IIO_DEV_ATTR_PINCONTROL_EN(0, S_IWUSR, NULL,
 173                                 ad9832_write, AD9832_PINCTRL_EN);
 174 static IIO_DEV_ATTR_OUT_ENABLE(0, S_IWUSR, NULL,
 175                                 ad9832_write, AD9832_OUTPUT_EN);
 176
 177 static struct attribute *ad9832_attributes[] = {
 178         &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
 179         &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
 180         &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
 181         &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
 182         &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
 183         &iio_dev_attr_out_altvoltage0_phase2.dev_attr.attr,
 184         &iio_dev_attr_out_altvoltage0_phase3.dev_attr.attr,
 185         &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
 186         &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
 187         &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
 188         &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
 189         &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
 190         NULL,
 191 };
 192
 193 static const struct attribute_group ad9832_attribute_group = {
 194         .attrs = ad9832_attributes,
 195 };
 196
 197 static const struct iio_info ad9832_info = {
 198         .attrs = &ad9832_attribute_group,
 199         .driver_module = THIS_MODULE,
 200 };
 201
 202 static int ad9832_probe(struct spi_device *spi)
 203 {
 204         struct ad9832_platform_data *pdata = spi->dev.platform_data;
 205         struct iio_dev *indio_dev;
 206         struct ad9832_state *st;
 207         struct regulator *reg;
 208         int ret;
 209
 210         if (!pdata) {
 211                 dev_dbg(&spi->dev, "no platform data?\n");
 212                 return -ENODEV;
 213         }
 214
 215         reg = devm_regulator_get(&spi->dev, "vcc");
 216         if (!IS_ERR(reg)) {
 217                 ret = regulator_enable(reg);
 218                 if (ret)
 219                         return ret;
 220         }
 221
 222         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 223         if (!indio_dev) {
 224                 ret = -ENOMEM;
 225                 goto error_disable_reg;
 226         }
 227         spi_set_drvdata(spi, indio_dev);
 228         st = iio_priv(indio_dev);
 229         st->reg = reg;
 230         st->mclk = pdata->mclk;
 231         st->spi = spi;
 232
 233         indio_dev->dev.parent = &spi->dev;
 234         indio_dev->name = spi_get_device_id(spi)->name;
 235         indio_dev->info = &ad9832_info;
 236         indio_dev->modes = INDIO_DIRECT_MODE;
 237
 238         /* Setup default messages */
 239
 240         st->xfer.tx_buf = &st->data;
 241         st->xfer.len = 2;
 242
 243         spi_message_init(&st->msg);
 244         spi_message_add_tail(&st->xfer, &st->msg);
 245
 246         st->freq_xfer[0].tx_buf = &st->freq_data[0];
 247         st->freq_xfer[0].len = 2;
 248         st->freq_xfer[0].cs_change = 1;
 249         st->freq_xfer[1].tx_buf = &st->freq_data[1];
 250         st->freq_xfer[1].len = 2;
 251         st->freq_xfer[1].cs_change = 1;
 252         st->freq_xfer[2].tx_buf = &st->freq_data[2];
 253         st->freq_xfer[2].len = 2;
 254         st->freq_xfer[2].cs_change = 1;
 255         st->freq_xfer[3].tx_buf = &st->freq_data[3];
 256         st->freq_xfer[3].len = 2;
 257
 258         spi_message_init(&st->freq_msg);
 259         spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
 260         spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
 261         spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
 262         spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
 263
 264         st->phase_xfer[0].tx_buf = &st->phase_data[0];
 265         st->phase_xfer[0].len = 2;
 266         st->phase_xfer[0].cs_change = 1;
 267         st->phase_xfer[1].tx_buf = &st->phase_data[1];
 268         st->phase_xfer[1].len = 2;
 269
 270         spi_message_init(&st->phase_msg);
 271         spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
 272         spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
 273
 274         st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
 275         st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
 276                                         st->ctrl_src);
 277         ret = spi_sync(st->spi, &st->msg);
 278         if (ret) {
 279                 dev_err(&spi->dev, "device init failed\n");
 280                 goto error_disable_reg;
 281         }
 282
 283         ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
 284         if (ret)
 285                 goto error_disable_reg;
 286
 287         ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
 288         if (ret)
 289                 goto error_disable_reg;
 290
 291         ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
 292         if (ret)
 293                 goto error_disable_reg;
 294
 295         ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
 296         if (ret)
 297                 goto error_disable_reg;
 298
 299         ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
 300         if (ret)
 301                 goto error_disable_reg;
 302
 303         ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
 304         if (ret)
 305                 goto error_disable_reg;
 306
 307         ret = iio_device_register(indio_dev);
 308         if (ret)
 309                 goto error_disable_reg;
 310
 311         return 0;
 312
 313 error_disable_reg:
 314         if (!IS_ERR(reg))
 315                 regulator_disable(reg);
 316
 317         return ret;
 318 }
 319
 320 static int ad9832_remove(struct spi_device *spi)
 321 {
 322         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 323         struct ad9832_state *st = iio_priv(indio_dev);
 324
 325         iio_device_unregister(indio_dev);
 326         if (!IS_ERR(st->reg))
 327                 regulator_disable(st->reg);
 328
 329         return 0;
 330 }
 331
 332 static const struct spi_device_id ad9832_id[] = {
 333         {"ad9832", 0},
 334         {"ad9835", 0},
 335         {}
 336 };
 337 MODULE_DEVICE_TABLE(spi, ad9832_id);
 338
 339 static struct spi_driver ad9832_driver = {
 340         .driver = {
 341                 .name   = "ad9832",
 342                 .owner  = THIS_MODULE,
 343         },
 344         .probe          = ad9832_probe,
 345         .remove         = ad9832_remove,
 346         .id_table       = ad9832_id,
 347 };
 348 module_spi_driver(ad9832_driver);
 349
 350 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
 351 MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
 352 MODULE_LICENSE("GPL v2");