4 /* New register for SM750LE */
5 #define DE_STATE1 0x100054
6 #define DE_STATE1_DE_ABORT BIT(0)
8 #define DE_STATE2 0x100058
9 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
10 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
11 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
13 #define SYSTEM_CTRL 0x000000
14 #define SYSTEM_CTRL_DPMS_MASK (0x3 << 30)
15 #define SYSTEM_CTRL_DPMS_VPHP (0x0 << 30)
16 #define SYSTEM_CTRL_DPMS_VPHN (0x1 << 30)
17 #define SYSTEM_CTRL_DPMS_VNHP (0x2 << 30)
18 #define SYSTEM_CTRL_DPMS_VNHN (0x3 << 30)
19 #define SYSTEM_CTRL_PCI_BURST BIT(29)
20 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
21 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
22 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
23 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
24 #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21)
25 #define SYSTEM_CTRL_CSC_STATUS_BUSY BIT(20)
26 #define SYSTEM_CTRL_CRT_VSYNC_ACTIVE BIT(19)
27 #define SYSTEM_CTRL_PANEL_VSYNC_ACTIVE BIT(18)
28 #define SYSTEM_CTRL_CURRENT_BUFFER_FLIP_PENDING BIT(17)
29 #define SYSTEM_CTRL_DMA_STATUS_BUSY BIT(16)
30 #define SYSTEM_CTRL_PCI_BURST_READ BIT(15)
31 #define SYSTEM_CTRL_DE_ABORT BIT(13)
32 #define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK BIT(11)
33 #define SYSTEM_CTRL_PCI_RETRY_OFF BIT(7)
34 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_MASK (0x3 << 4)
35 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1 (0x0 << 4)
36 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2 (0x1 << 4)
37 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4 (0x2 << 4)
38 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8 (0x3 << 4)
39 #define SYSTEM_CTRL_CRT_TRISTATE BIT(3)
40 #define SYSTEM_CTRL_PCIMEM_TRISTATE BIT(2)
41 #define SYSTEM_CTRL_LOCALMEM_TRISTATE BIT(1)
42 #define SYSTEM_CTRL_PANEL_TRISTATE BIT(0)
44 #define MISC_CTRL 0x000004
45 #define MISC_CTRL_DRAM_RERESH_COUNT BIT(27)
46 #define MISC_CTRL_DRAM_REFRESH_TIME_MASK (0x3 << 25)
47 #define MISC_CTRL_DRAM_REFRESH_TIME_8 (0x0 << 25)
48 #define MISC_CTRL_DRAM_REFRESH_TIME_16 (0x1 << 25)
49 #define MISC_CTRL_DRAM_REFRESH_TIME_32 (0x2 << 25)
50 #define MISC_CTRL_DRAM_REFRESH_TIME_64 (0x3 << 25)
51 #define MISC_CTRL_INT_OUTPUT_INVERT BIT(24)
52 #define MISC_CTRL_PLL_CLK_COUNT BIT(23)
53 #define MISC_CTRL_DAC_POWER_OFF BIT(20)
54 #define MISC_CTRL_CLK_SELECT_TESTCLK BIT(16)
55 #define MISC_CTRL_DRAM_COLUMN_SIZE_MASK (0x3 << 14)
56 #define MISC_CTRL_DRAM_COLUMN_SIZE_256 (0x0 << 14)
57 #define MISC_CTRL_DRAM_COLUMN_SIZE_512 (0x1 << 14)
58 #define MISC_CTRL_DRAM_COLUMN_SIZE_1024 (0x2 << 14)
59 #define MISC_CTRL_LOCALMEM_SIZE_MASK (0x3 << 12)
60 #define MISC_CTRL_LOCALMEM_SIZE_8M (0x3 << 12)
61 #define MISC_CTRL_LOCALMEM_SIZE_16M (0x0 << 12)
62 #define MISC_CTRL_LOCALMEM_SIZE_32M (0x1 << 12)
63 #define MISC_CTRL_LOCALMEM_SIZE_64M (0x2 << 12)
64 #define MISC_CTRL_DRAM_TWTR BIT(11)
65 #define MISC_CTRL_DRAM_TWR BIT(10)
66 #define MISC_CTRL_DRAM_TRP BIT(9)
67 #define MISC_CTRL_DRAM_TRFC BIT(8)
68 #define MISC_CTRL_DRAM_TRAS BIT(7)
69 #define MISC_CTRL_LOCALMEM_RESET BIT(6)
70 #define MISC_CTRL_LOCALMEM_STATE_INACTIVE BIT(5)
71 #define MISC_CTRL_CPU_CAS_LATENCY BIT(4)
72 #define MISC_CTRL_DLL_OFF BIT(3)
73 #define MISC_CTRL_DRAM_OUTPUT_HIGH BIT(2)
74 #define MISC_CTRL_LOCALMEM_BUS_SIZE BIT(1)
75 #define MISC_CTRL_EMBEDDED_LOCALMEM_OFF BIT(0)
77 #define GPIO_MUX 0x000008
78 #define GPIO_MUX_31 BIT(31)
79 #define GPIO_MUX_30 BIT(30)
80 #define GPIO_MUX_29 BIT(29)
81 #define GPIO_MUX_28 BIT(28)
82 #define GPIO_MUX_27 BIT(27)
83 #define GPIO_MUX_26 BIT(26)
84 #define GPIO_MUX_25 BIT(25)
85 #define GPIO_MUX_24 BIT(24)
86 #define GPIO_MUX_23 BIT(23)
87 #define GPIO_MUX_22 BIT(22)
88 #define GPIO_MUX_21 BIT(21)
89 #define GPIO_MUX_20 BIT(20)
90 #define GPIO_MUX_19 BIT(19)
91 #define GPIO_MUX_18 BIT(18)
92 #define GPIO_MUX_17 BIT(17)
93 #define GPIO_MUX_16 BIT(16)
94 #define GPIO_MUX_15 BIT(15)
95 #define GPIO_MUX_14 BIT(14)
96 #define GPIO_MUX_13 BIT(13)
97 #define GPIO_MUX_12 BIT(12)
98 #define GPIO_MUX_11 BIT(11)
99 #define GPIO_MUX_10 BIT(10)
100 #define GPIO_MUX_9 BIT(9)
101 #define GPIO_MUX_8 BIT(8)
102 #define GPIO_MUX_7 BIT(7)
103 #define GPIO_MUX_6 BIT(6)
104 #define GPIO_MUX_5 BIT(5)
105 #define GPIO_MUX_4 BIT(4)
106 #define GPIO_MUX_3 BIT(3)
107 #define GPIO_MUX_2 BIT(2)
108 #define GPIO_MUX_1 BIT(1)
109 #define GPIO_MUX_0 BIT(0)
111 #define LOCALMEM_ARBITRATION 0x00000C
112 #define LOCALMEM_ARBITRATION_ROTATE 28:28
113 #define LOCALMEM_ARBITRATION_ROTATE_OFF 0
114 #define LOCALMEM_ARBITRATION_ROTATE_ON 1
115 #define LOCALMEM_ARBITRATION_VGA 26:24
116 #define LOCALMEM_ARBITRATION_VGA_OFF 0
117 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_1 1
118 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_2 2
119 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_3 3
120 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_4 4
121 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_5 5
122 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_6 6
123 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_7 7
124 #define LOCALMEM_ARBITRATION_DMA 22:20
125 #define LOCALMEM_ARBITRATION_DMA_OFF 0
126 #define LOCALMEM_ARBITRATION_DMA_PRIORITY_1 1
127 #define LOCALMEM_ARBITRATION_DMA_PRIORITY_2 2
128 #define LOCALMEM_ARBITRATION_DMA_PRIORITY_3 3
129 #define LOCALMEM_ARBITRATION_DMA_PRIORITY_4 4
130 #define LOCALMEM_ARBITRATION_DMA_PRIORITY_5 5
131 #define LOCALMEM_ARBITRATION_DMA_PRIORITY_6 6
132 #define LOCALMEM_ARBITRATION_DMA_PRIORITY_7 7
133 #define LOCALMEM_ARBITRATION_ZVPORT1 18:16
134 #define LOCALMEM_ARBITRATION_ZVPORT1_OFF 0
135 #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_1 1
136 #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_2 2
137 #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_3 3
138 #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_4 4
139 #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_5 5
140 #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_6 6
141 #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_7 7
142 #define LOCALMEM_ARBITRATION_ZVPORT0 14:12
143 #define LOCALMEM_ARBITRATION_ZVPORT0_OFF 0
144 #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_1 1
145 #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_2 2
146 #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_3 3
147 #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_4 4
148 #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_5 5
149 #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_6 6
150 #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_7 7
151 #define LOCALMEM_ARBITRATION_VIDEO 10:8
152 #define LOCALMEM_ARBITRATION_VIDEO_OFF 0
153 #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_1 1
154 #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_2 2
155 #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_3 3
156 #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_4 4
157 #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_5 5
158 #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_6 6
159 #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_7 7
160 #define LOCALMEM_ARBITRATION_PANEL 6:4
161 #define LOCALMEM_ARBITRATION_PANEL_OFF 0
162 #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_1 1
163 #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_2 2
164 #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_3 3
165 #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_4 4
166 #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_5 5
167 #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_6 6
168 #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_7 7
169 #define LOCALMEM_ARBITRATION_CRT 2:0
170 #define LOCALMEM_ARBITRATION_CRT_OFF 0
171 #define LOCALMEM_ARBITRATION_CRT_PRIORITY_1 1
172 #define LOCALMEM_ARBITRATION_CRT_PRIORITY_2 2
173 #define LOCALMEM_ARBITRATION_CRT_PRIORITY_3 3
174 #define LOCALMEM_ARBITRATION_CRT_PRIORITY_4 4
175 #define LOCALMEM_ARBITRATION_CRT_PRIORITY_5 5
176 #define LOCALMEM_ARBITRATION_CRT_PRIORITY_6 6
177 #define LOCALMEM_ARBITRATION_CRT_PRIORITY_7 7
179 #define PCIMEM_ARBITRATION 0x000010
180 #define PCIMEM_ARBITRATION_ROTATE 28:28
181 #define PCIMEM_ARBITRATION_ROTATE_OFF 0
182 #define PCIMEM_ARBITRATION_ROTATE_ON 1
183 #define PCIMEM_ARBITRATION_VGA 26:24
184 #define PCIMEM_ARBITRATION_VGA_OFF 0
185 #define PCIMEM_ARBITRATION_VGA_PRIORITY_1 1
186 #define PCIMEM_ARBITRATION_VGA_PRIORITY_2 2
187 #define PCIMEM_ARBITRATION_VGA_PRIORITY_3 3
188 #define PCIMEM_ARBITRATION_VGA_PRIORITY_4 4
189 #define PCIMEM_ARBITRATION_VGA_PRIORITY_5 5
190 #define PCIMEM_ARBITRATION_VGA_PRIORITY_6 6
191 #define PCIMEM_ARBITRATION_VGA_PRIORITY_7 7
192 #define PCIMEM_ARBITRATION_DMA 22:20
193 #define PCIMEM_ARBITRATION_DMA_OFF 0
194 #define PCIMEM_ARBITRATION_DMA_PRIORITY_1 1
195 #define PCIMEM_ARBITRATION_DMA_PRIORITY_2 2
196 #define PCIMEM_ARBITRATION_DMA_PRIORITY_3 3
197 #define PCIMEM_ARBITRATION_DMA_PRIORITY_4 4
198 #define PCIMEM_ARBITRATION_DMA_PRIORITY_5 5
199 #define PCIMEM_ARBITRATION_DMA_PRIORITY_6 6
200 #define PCIMEM_ARBITRATION_DMA_PRIORITY_7 7
201 #define PCIMEM_ARBITRATION_ZVPORT1 18:16
202 #define PCIMEM_ARBITRATION_ZVPORT1_OFF 0
203 #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_1 1
204 #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_2 2
205 #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_3 3
206 #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_4 4
207 #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_5 5
208 #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_6 6
209 #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_7 7
210 #define PCIMEM_ARBITRATION_ZVPORT0 14:12
211 #define PCIMEM_ARBITRATION_ZVPORT0_OFF 0
212 #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_1 1
213 #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_2 2
214 #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_3 3
215 #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_4 4
216 #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_5 5
217 #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_6 6
218 #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_7 7
219 #define PCIMEM_ARBITRATION_VIDEO 10:8
220 #define PCIMEM_ARBITRATION_VIDEO_OFF 0
221 #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_1 1
222 #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_2 2
223 #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_3 3
224 #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_4 4
225 #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_5 5
226 #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_6 6
227 #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_7 7
228 #define PCIMEM_ARBITRATION_PANEL 6:4
229 #define PCIMEM_ARBITRATION_PANEL_OFF 0
230 #define PCIMEM_ARBITRATION_PANEL_PRIORITY_1 1
231 #define PCIMEM_ARBITRATION_PANEL_PRIORITY_2 2
232 #define PCIMEM_ARBITRATION_PANEL_PRIORITY_3 3
233 #define PCIMEM_ARBITRATION_PANEL_PRIORITY_4 4
234 #define PCIMEM_ARBITRATION_PANEL_PRIORITY_5 5
235 #define PCIMEM_ARBITRATION_PANEL_PRIORITY_6 6
236 #define PCIMEM_ARBITRATION_PANEL_PRIORITY_7 7
237 #define PCIMEM_ARBITRATION_CRT 2:0
238 #define PCIMEM_ARBITRATION_CRT_OFF 0
239 #define PCIMEM_ARBITRATION_CRT_PRIORITY_1 1
240 #define PCIMEM_ARBITRATION_CRT_PRIORITY_2 2
241 #define PCIMEM_ARBITRATION_CRT_PRIORITY_3 3
242 #define PCIMEM_ARBITRATION_CRT_PRIORITY_4 4
243 #define PCIMEM_ARBITRATION_CRT_PRIORITY_5 5
244 #define PCIMEM_ARBITRATION_CRT_PRIORITY_6 6
245 #define PCIMEM_ARBITRATION_CRT_PRIORITY_7 7
247 #define RAW_INT 0x000020
248 #define RAW_INT_ZVPORT1_VSYNC 4:4
249 #define RAW_INT_ZVPORT1_VSYNC_INACTIVE 0
250 #define RAW_INT_ZVPORT1_VSYNC_ACTIVE 1
251 #define RAW_INT_ZVPORT1_VSYNC_CLEAR 1
252 #define RAW_INT_ZVPORT0_VSYNC 3:3
253 #define RAW_INT_ZVPORT0_VSYNC_INACTIVE 0
254 #define RAW_INT_ZVPORT0_VSYNC_ACTIVE 1
255 #define RAW_INT_ZVPORT0_VSYNC_CLEAR 1
256 #define RAW_INT_CRT_VSYNC 2:2
257 #define RAW_INT_CRT_VSYNC_INACTIVE 0
258 #define RAW_INT_CRT_VSYNC_ACTIVE 1
259 #define RAW_INT_CRT_VSYNC_CLEAR 1
260 #define RAW_INT_PANEL_VSYNC 1:1
261 #define RAW_INT_PANEL_VSYNC_INACTIVE 0
262 #define RAW_INT_PANEL_VSYNC_ACTIVE 1
263 #define RAW_INT_PANEL_VSYNC_CLEAR 1
264 #define RAW_INT_VGA_VSYNC 0:0
265 #define RAW_INT_VGA_VSYNC_INACTIVE 0
266 #define RAW_INT_VGA_VSYNC_ACTIVE 1
267 #define RAW_INT_VGA_VSYNC_CLEAR 1
269 #define INT_STATUS 0x000024
270 #define INT_STATUS_GPIO31 31:31
271 #define INT_STATUS_GPIO31_INACTIVE 0
272 #define INT_STATUS_GPIO31_ACTIVE 1
273 #define INT_STATUS_GPIO30 30:30
274 #define INT_STATUS_GPIO30_INACTIVE 0
275 #define INT_STATUS_GPIO30_ACTIVE 1
276 #define INT_STATUS_GPIO29 29:29
277 #define INT_STATUS_GPIO29_INACTIVE 0
278 #define INT_STATUS_GPIO29_ACTIVE 1
279 #define INT_STATUS_GPIO28 28:28
280 #define INT_STATUS_GPIO28_INACTIVE 0
281 #define INT_STATUS_GPIO28_ACTIVE 1
282 #define INT_STATUS_GPIO27 27:27
283 #define INT_STATUS_GPIO27_INACTIVE 0
284 #define INT_STATUS_GPIO27_ACTIVE 1
285 #define INT_STATUS_GPIO26 26:26
286 #define INT_STATUS_GPIO26_INACTIVE 0
287 #define INT_STATUS_GPIO26_ACTIVE 1
288 #define INT_STATUS_GPIO25 25:25
289 #define INT_STATUS_GPIO25_INACTIVE 0
290 #define INT_STATUS_GPIO25_ACTIVE 1
291 #define INT_STATUS_I2C 12:12
292 #define INT_STATUS_I2C_INACTIVE 0
293 #define INT_STATUS_I2C_ACTIVE 1
294 #define INT_STATUS_PWM 11:11
295 #define INT_STATUS_PWM_INACTIVE 0
296 #define INT_STATUS_PWM_ACTIVE 1
297 #define INT_STATUS_DMA1 10:10
298 #define INT_STATUS_DMA1_INACTIVE 0
299 #define INT_STATUS_DMA1_ACTIVE 1
300 #define INT_STATUS_DMA0 9:9
301 #define INT_STATUS_DMA0_INACTIVE 0
302 #define INT_STATUS_DMA0_ACTIVE 1
303 #define INT_STATUS_PCI 8:8
304 #define INT_STATUS_PCI_INACTIVE 0
305 #define INT_STATUS_PCI_ACTIVE 1
306 #define INT_STATUS_SSP1 7:7
307 #define INT_STATUS_SSP1_INACTIVE 0
308 #define INT_STATUS_SSP1_ACTIVE 1
309 #define INT_STATUS_SSP0 6:6
310 #define INT_STATUS_SSP0_INACTIVE 0
311 #define INT_STATUS_SSP0_ACTIVE 1
312 #define INT_STATUS_DE 5:5
313 #define INT_STATUS_DE_INACTIVE 0
314 #define INT_STATUS_DE_ACTIVE 1
315 #define INT_STATUS_ZVPORT1_VSYNC 4:4
316 #define INT_STATUS_ZVPORT1_VSYNC_INACTIVE 0
317 #define INT_STATUS_ZVPORT1_VSYNC_ACTIVE 1
318 #define INT_STATUS_ZVPORT0_VSYNC 3:3
319 #define INT_STATUS_ZVPORT0_VSYNC_INACTIVE 0
320 #define INT_STATUS_ZVPORT0_VSYNC_ACTIVE 1
321 #define INT_STATUS_CRT_VSYNC 2:2
322 #define INT_STATUS_CRT_VSYNC_INACTIVE 0
323 #define INT_STATUS_CRT_VSYNC_ACTIVE 1
324 #define INT_STATUS_PANEL_VSYNC 1:1
325 #define INT_STATUS_PANEL_VSYNC_INACTIVE 0
326 #define INT_STATUS_PANEL_VSYNC_ACTIVE 1
327 #define INT_STATUS_VGA_VSYNC 0:0
328 #define INT_STATUS_VGA_VSYNC_INACTIVE 0
329 #define INT_STATUS_VGA_VSYNC_ACTIVE 1
331 #define INT_MASK 0x000028
332 #define INT_MASK_GPIO31 31:31
333 #define INT_MASK_GPIO31_DISABLE 0
334 #define INT_MASK_GPIO31_ENABLE 1
335 #define INT_MASK_GPIO30 30:30
336 #define INT_MASK_GPIO30_DISABLE 0
337 #define INT_MASK_GPIO30_ENABLE 1
338 #define INT_MASK_GPIO29 29:29
339 #define INT_MASK_GPIO29_DISABLE 0
340 #define INT_MASK_GPIO29_ENABLE 1
341 #define INT_MASK_GPIO28 28:28
342 #define INT_MASK_GPIO28_DISABLE 0
343 #define INT_MASK_GPIO28_ENABLE 1
344 #define INT_MASK_GPIO27 27:27
345 #define INT_MASK_GPIO27_DISABLE 0
346 #define INT_MASK_GPIO27_ENABLE 1
347 #define INT_MASK_GPIO26 26:26
348 #define INT_MASK_GPIO26_DISABLE 0
349 #define INT_MASK_GPIO26_ENABLE 1
350 #define INT_MASK_GPIO25 25:25
351 #define INT_MASK_GPIO25_DISABLE 0
352 #define INT_MASK_GPIO25_ENABLE 1
353 #define INT_MASK_I2C 12:12
354 #define INT_MASK_I2C_DISABLE 0
355 #define INT_MASK_I2C_ENABLE 1
356 #define INT_MASK_PWM 11:11
357 #define INT_MASK_PWM_DISABLE 0
358 #define INT_MASK_PWM_ENABLE 1
359 #define INT_MASK_DMA1 10:10
360 #define INT_MASK_DMA1_DISABLE 0
361 #define INT_MASK_DMA1_ENABLE 1
362 #define INT_MASK_DMA 9:9
363 #define INT_MASK_DMA_DISABLE 0
364 #define INT_MASK_DMA_ENABLE 1
365 #define INT_MASK_PCI 8:8
366 #define INT_MASK_PCI_DISABLE 0
367 #define INT_MASK_PCI_ENABLE 1
368 #define INT_MASK_SSP1 7:7
369 #define INT_MASK_SSP1_DISABLE 0
370 #define INT_MASK_SSP1_ENABLE 1
371 #define INT_MASK_SSP0 6:6
372 #define INT_MASK_SSP0_DISABLE 0
373 #define INT_MASK_SSP0_ENABLE 1
374 #define INT_MASK_DE 5:5
375 #define INT_MASK_DE_DISABLE 0
376 #define INT_MASK_DE_ENABLE 1
377 #define INT_MASK_ZVPORT1_VSYNC 4:4
378 #define INT_MASK_ZVPORT1_VSYNC_DISABLE 0
379 #define INT_MASK_ZVPORT1_VSYNC_ENABLE 1
380 #define INT_MASK_ZVPORT0_VSYNC 3:3
381 #define INT_MASK_ZVPORT0_VSYNC_DISABLE 0
382 #define INT_MASK_ZVPORT0_VSYNC_ENABLE 1
383 #define INT_MASK_CRT_VSYNC 2:2
384 #define INT_MASK_CRT_VSYNC_DISABLE 0
385 #define INT_MASK_CRT_VSYNC_ENABLE 1
386 #define INT_MASK_PANEL_VSYNC 1:1
387 #define INT_MASK_PANEL_VSYNC_DISABLE 0
388 #define INT_MASK_PANEL_VSYNC_ENABLE 1
389 #define INT_MASK_VGA_VSYNC 0:0
390 #define INT_MASK_VGA_VSYNC_DISABLE 0
391 #define INT_MASK_VGA_VSYNC_ENABLE 1
393 #define CURRENT_GATE 0x000040
394 #define CURRENT_GATE_MCLK_MASK (0x3 << 14)
395 #ifdef VALIDATION_CHIP
396 #define CURRENT_GATE_MCLK_112MHZ (0x0 << 14)
397 #define CURRENT_GATE_MCLK_84MHZ (0x1 << 14)
398 #define CURRENT_GATE_MCLK_56MHZ (0x2 << 14)
399 #define CURRENT_GATE_MCLK_42MHZ (0x3 << 14)
401 #define CURRENT_GATE_MCLK_DIV_3 (0x0 << 14)
402 #define CURRENT_GATE_MCLK_DIV_4 (0x1 << 14)
403 #define CURRENT_GATE_MCLK_DIV_6 (0x2 << 14)
404 #define CURRENT_GATE_MCLK_DIV_8 (0x3 << 14)
406 #define CURRENT_GATE_M2XCLK_MASK (0x3 << 12)
407 #ifdef VALIDATION_CHIP
408 #define CURRENT_GATE_M2XCLK_336MHZ (0x0 << 12)
409 #define CURRENT_GATE_M2XCLK_168MHZ (0x1 << 12)
410 #define CURRENT_GATE_M2XCLK_112MHZ (0x2 << 12)
411 #define CURRENT_GATE_M2XCLK_84MHZ (0x3 << 12)
413 #define CURRENT_GATE_M2XCLK_DIV_1 (0x0 << 12)
414 #define CURRENT_GATE_M2XCLK_DIV_2 (0x1 << 12)
415 #define CURRENT_GATE_M2XCLK_DIV_3 (0x2 << 12)
416 #define CURRENT_GATE_M2XCLK_DIV_4 (0x3 << 12)
418 #define CURRENT_GATE_VGA BIT(10)
419 #define CURRENT_GATE_PWM BIT(9)
420 #define CURRENT_GATE_I2C BIT(8)
421 #define CURRENT_GATE_SSP BIT(7)
422 #define CURRENT_GATE_GPIO BIT(6)
423 #define CURRENT_GATE_ZVPORT BIT(5)
424 #define CURRENT_GATE_CSC BIT(4)
425 #define CURRENT_GATE_DE BIT(3)
426 #define CURRENT_GATE_DISPLAY BIT(2)
427 #define CURRENT_GATE_LOCALMEM BIT(1)
428 #define CURRENT_GATE_DMA BIT(0)
430 #define MODE0_GATE 0x000044
431 #define MODE0_GATE_MCLK_MASK (0x3 << 14)
432 #define MODE0_GATE_MCLK_112MHZ (0x0 << 14)
433 #define MODE0_GATE_MCLK_84MHZ (0x1 << 14)
434 #define MODE0_GATE_MCLK_56MHZ (0x2 << 14)
435 #define MODE0_GATE_MCLK_42MHZ (0x3 << 14)
436 #define MODE0_GATE_M2XCLK_MASK (0x3 << 12)
437 #define MODE0_GATE_M2XCLK_336MHZ (0x0 << 12)
438 #define MODE0_GATE_M2XCLK_168MHZ (0x1 << 12)
439 #define MODE0_GATE_M2XCLK_112MHZ (0x2 << 12)
440 #define MODE0_GATE_M2XCLK_84MHZ (0x3 << 12)
441 #define MODE0_GATE_VGA BIT(10)
442 #define MODE0_GATE_PWM BIT(9)
443 #define MODE0_GATE_I2C BIT(8)
444 #define MODE0_GATE_SSP BIT(7)
445 #define MODE0_GATE_GPIO BIT(6)
446 #define MODE0_GATE_ZVPORT BIT(5)
447 #define MODE0_GATE_CSC BIT(4)
448 #define MODE0_GATE_DE BIT(3)
449 #define MODE0_GATE_DISPLAY BIT(2)
450 #define MODE0_GATE_LOCALMEM BIT(1)
451 #define MODE0_GATE_DMA BIT(0)
453 #define MODE1_GATE 0x000048
454 #define MODE1_GATE_MCLK 15:14
455 #define MODE1_GATE_MCLK_112MHZ 0
456 #define MODE1_GATE_MCLK_84MHZ 1
457 #define MODE1_GATE_MCLK_56MHZ 2
458 #define MODE1_GATE_MCLK_42MHZ 3
459 #define MODE1_GATE_M2XCLK 13:12
460 #define MODE1_GATE_M2XCLK_336MHZ 0
461 #define MODE1_GATE_M2XCLK_168MHZ 1
462 #define MODE1_GATE_M2XCLK_112MHZ 2
463 #define MODE1_GATE_M2XCLK_84MHZ 3
464 #define MODE1_GATE_VGA 10:10
465 #define MODE1_GATE_VGA_OFF 0
466 #define MODE1_GATE_VGA_ON 1
467 #define MODE1_GATE_PWM 9:9
468 #define MODE1_GATE_PWM_OFF 0
469 #define MODE1_GATE_PWM_ON 1
470 #define MODE1_GATE_I2C 8:8
471 #define MODE1_GATE_I2C_OFF 0
472 #define MODE1_GATE_I2C_ON 1
473 #define MODE1_GATE_SSP 7:7
474 #define MODE1_GATE_SSP_OFF 0
475 #define MODE1_GATE_SSP_ON 1
476 #define MODE1_GATE_GPIO 6:6
477 #define MODE1_GATE_GPIO_OFF 0
478 #define MODE1_GATE_GPIO_ON 1
479 #define MODE1_GATE_ZVPORT 5:5
480 #define MODE1_GATE_ZVPORT_OFF 0
481 #define MODE1_GATE_ZVPORT_ON 1
482 #define MODE1_GATE_CSC 4:4
483 #define MODE1_GATE_CSC_OFF 0
484 #define MODE1_GATE_CSC_ON 1
485 #define MODE1_GATE_DE 3:3
486 #define MODE1_GATE_DE_OFF 0
487 #define MODE1_GATE_DE_ON 1
488 #define MODE1_GATE_DISPLAY 2:2
489 #define MODE1_GATE_DISPLAY_OFF 0
490 #define MODE1_GATE_DISPLAY_ON 1
491 #define MODE1_GATE_LOCALMEM 1:1
492 #define MODE1_GATE_LOCALMEM_OFF 0
493 #define MODE1_GATE_LOCALMEM_ON 1
494 #define MODE1_GATE_DMA 0:0
495 #define MODE1_GATE_DMA_OFF 0
496 #define MODE1_GATE_DMA_ON 1
498 #define POWER_MODE_CTRL 0x00004C
499 #ifdef VALIDATION_CHIP
500 #define POWER_MODE_CTRL_336CLK BIT(4)
502 #define POWER_MODE_CTRL_OSC_INPUT BIT(3)
503 #define POWER_MODE_CTRL_ACPI BIT(2)
504 #define POWER_MODE_CTRL_MODE_MASK (0x3 << 0)
505 #define POWER_MODE_CTRL_MODE_MODE0 (0x0 << 0)
506 #define POWER_MODE_CTRL_MODE_MODE1 (0x1 << 0)
507 #define POWER_MODE_CTRL_MODE_SLEEP (0x2 << 0)
509 #define PCI_MASTER_BASE 0x000050
510 #define PCI_MASTER_BASE_ADDRESS 7:0
512 #define DEVICE_ID 0x000054
513 #define DEVICE_ID_DEVICE_ID 31:16
514 #define DEVICE_ID_REVISION_ID 7:0
516 #define PLL_CLK_COUNT 0x000058
517 #define PLL_CLK_COUNT_COUNTER 15:0
519 #define PANEL_PLL_CTRL 0x00005C
520 #define PLL_CTRL_BYPASS BIT(18)
521 #define PLL_CTRL_POWER BIT(17)
522 #define PLL_CTRL_INPUT BIT(16)
523 #ifdef VALIDATION_CHIP
524 #define PLL_CTRL_OD_SHIFT 14
525 #define PLL_CTRL_OD_MASK (0x3 << 14)
527 #define PLL_CTRL_POD_SHIFT 14
528 #define PLL_CTRL_POD_MASK (0x3 << 14)
529 #define PLL_CTRL_OD_SHIFT 12
530 #define PLL_CTRL_OD_MASK (0x3 << 12)
532 #define PLL_CTRL_N_SHIFT 8
533 #define PLL_CTRL_N_MASK (0xf << 8)
534 #define PLL_CTRL_M_SHIFT 0
535 #define PLL_CTRL_M_MASK 0xff
537 #define CRT_PLL_CTRL 0x000060
539 #define VGA_PLL0_CTRL 0x000064
541 #define VGA_PLL1_CTRL 0x000068
543 #define SCRATCH_DATA 0x00006c
545 #ifndef VALIDATION_CHIP
547 #define MXCLK_PLL_CTRL 0x000070
549 #define VGA_CONFIGURATION 0x000088
550 #define VGA_CONFIGURATION_USER_DEFINE_MASK (0x3 << 4)
551 #define VGA_CONFIGURATION_PLL BIT(2)
552 #define VGA_CONFIGURATION_MODE BIT(1)
556 #define GPIO_DATA 0x010000
557 #define GPIO_DATA_31 31:31
558 #define GPIO_DATA_30 30:30
559 #define GPIO_DATA_29 29:29
560 #define GPIO_DATA_28 28:28
561 #define GPIO_DATA_27 27:27
562 #define GPIO_DATA_26 26:26
563 #define GPIO_DATA_25 25:25
564 #define GPIO_DATA_24 24:24
565 #define GPIO_DATA_23 23:23
566 #define GPIO_DATA_22 22:22
567 #define GPIO_DATA_21 21:21
568 #define GPIO_DATA_20 20:20
569 #define GPIO_DATA_19 19:19
570 #define GPIO_DATA_18 18:18
571 #define GPIO_DATA_17 17:17
572 #define GPIO_DATA_16 16:16
573 #define GPIO_DATA_15 15:15
574 #define GPIO_DATA_14 14:14
575 #define GPIO_DATA_13 13:13
576 #define GPIO_DATA_12 12:12
577 #define GPIO_DATA_11 11:11
578 #define GPIO_DATA_10 10:10
579 #define GPIO_DATA_9 9:9
580 #define GPIO_DATA_8 8:8
581 #define GPIO_DATA_7 7:7
582 #define GPIO_DATA_6 6:6
583 #define GPIO_DATA_5 5:5
584 #define GPIO_DATA_4 4:4
585 #define GPIO_DATA_3 3:3
586 #define GPIO_DATA_2 2:2
587 #define GPIO_DATA_1 1:1
588 #define GPIO_DATA_0 0:0
590 #define GPIO_DATA_DIRECTION 0x010004
591 #define GPIO_DATA_DIRECTION_31 31:31
592 #define GPIO_DATA_DIRECTION_31_INPUT 0
593 #define GPIO_DATA_DIRECTION_31_OUTPUT 1
594 #define GPIO_DATA_DIRECTION_30 30:30
595 #define GPIO_DATA_DIRECTION_30_INPUT 0
596 #define GPIO_DATA_DIRECTION_30_OUTPUT 1
597 #define GPIO_DATA_DIRECTION_29 29:29
598 #define GPIO_DATA_DIRECTION_29_INPUT 0
599 #define GPIO_DATA_DIRECTION_29_OUTPUT 1
600 #define GPIO_DATA_DIRECTION_28 28:28
601 #define GPIO_DATA_DIRECTION_28_INPUT 0
602 #define GPIO_DATA_DIRECTION_28_OUTPUT 1
603 #define GPIO_DATA_DIRECTION_27 27:27
604 #define GPIO_DATA_DIRECTION_27_INPUT 0
605 #define GPIO_DATA_DIRECTION_27_OUTPUT 1
606 #define GPIO_DATA_DIRECTION_26 26:26
607 #define GPIO_DATA_DIRECTION_26_INPUT 0
608 #define GPIO_DATA_DIRECTION_26_OUTPUT 1
609 #define GPIO_DATA_DIRECTION_25 25:25
610 #define GPIO_DATA_DIRECTION_25_INPUT 0
611 #define GPIO_DATA_DIRECTION_25_OUTPUT 1
612 #define GPIO_DATA_DIRECTION_24 24:24
613 #define GPIO_DATA_DIRECTION_24_INPUT 0
614 #define GPIO_DATA_DIRECTION_24_OUTPUT 1
615 #define GPIO_DATA_DIRECTION_23 23:23
616 #define GPIO_DATA_DIRECTION_23_INPUT 0
617 #define GPIO_DATA_DIRECTION_23_OUTPUT 1
618 #define GPIO_DATA_DIRECTION_22 22:22
619 #define GPIO_DATA_DIRECTION_22_INPUT 0
620 #define GPIO_DATA_DIRECTION_22_OUTPUT 1
621 #define GPIO_DATA_DIRECTION_21 21:21
622 #define GPIO_DATA_DIRECTION_21_INPUT 0
623 #define GPIO_DATA_DIRECTION_21_OUTPUT 1
624 #define GPIO_DATA_DIRECTION_20 20:20
625 #define GPIO_DATA_DIRECTION_20_INPUT 0
626 #define GPIO_DATA_DIRECTION_20_OUTPUT 1
627 #define GPIO_DATA_DIRECTION_19 19:19
628 #define GPIO_DATA_DIRECTION_19_INPUT 0
629 #define GPIO_DATA_DIRECTION_19_OUTPUT 1
630 #define GPIO_DATA_DIRECTION_18 18:18
631 #define GPIO_DATA_DIRECTION_18_INPUT 0
632 #define GPIO_DATA_DIRECTION_18_OUTPUT 1
633 #define GPIO_DATA_DIRECTION_17 17:17
634 #define GPIO_DATA_DIRECTION_17_INPUT 0
635 #define GPIO_DATA_DIRECTION_17_OUTPUT 1
636 #define GPIO_DATA_DIRECTION_16 16:16
637 #define GPIO_DATA_DIRECTION_16_INPUT 0
638 #define GPIO_DATA_DIRECTION_16_OUTPUT 1
639 #define GPIO_DATA_DIRECTION_15 15:15
640 #define GPIO_DATA_DIRECTION_15_INPUT 0
641 #define GPIO_DATA_DIRECTION_15_OUTPUT 1
642 #define GPIO_DATA_DIRECTION_14 14:14
643 #define GPIO_DATA_DIRECTION_14_INPUT 0
644 #define GPIO_DATA_DIRECTION_14_OUTPUT 1
645 #define GPIO_DATA_DIRECTION_13 13:13
646 #define GPIO_DATA_DIRECTION_13_INPUT 0
647 #define GPIO_DATA_DIRECTION_13_OUTPUT 1
648 #define GPIO_DATA_DIRECTION_12 12:12
649 #define GPIO_DATA_DIRECTION_12_INPUT 0
650 #define GPIO_DATA_DIRECTION_12_OUTPUT 1
651 #define GPIO_DATA_DIRECTION_11 11:11
652 #define GPIO_DATA_DIRECTION_11_INPUT 0
653 #define GPIO_DATA_DIRECTION_11_OUTPUT 1
654 #define GPIO_DATA_DIRECTION_10 10:10
655 #define GPIO_DATA_DIRECTION_10_INPUT 0
656 #define GPIO_DATA_DIRECTION_10_OUTPUT 1
657 #define GPIO_DATA_DIRECTION_9 9:9
658 #define GPIO_DATA_DIRECTION_9_INPUT 0
659 #define GPIO_DATA_DIRECTION_9_OUTPUT 1
660 #define GPIO_DATA_DIRECTION_8 8:8
661 #define GPIO_DATA_DIRECTION_8_INPUT 0
662 #define GPIO_DATA_DIRECTION_8_OUTPUT 1
663 #define GPIO_DATA_DIRECTION_7 7:7
664 #define GPIO_DATA_DIRECTION_7_INPUT 0
665 #define GPIO_DATA_DIRECTION_7_OUTPUT 1
666 #define GPIO_DATA_DIRECTION_6 6:6
667 #define GPIO_DATA_DIRECTION_6_INPUT 0
668 #define GPIO_DATA_DIRECTION_6_OUTPUT 1
669 #define GPIO_DATA_DIRECTION_5 5:5
670 #define GPIO_DATA_DIRECTION_5_INPUT 0
671 #define GPIO_DATA_DIRECTION_5_OUTPUT 1
672 #define GPIO_DATA_DIRECTION_4 4:4
673 #define GPIO_DATA_DIRECTION_4_INPUT 0
674 #define GPIO_DATA_DIRECTION_4_OUTPUT 1
675 #define GPIO_DATA_DIRECTION_3 3:3
676 #define GPIO_DATA_DIRECTION_3_INPUT 0
677 #define GPIO_DATA_DIRECTION_3_OUTPUT 1
678 #define GPIO_DATA_DIRECTION_2 2:2
679 #define GPIO_DATA_DIRECTION_2_INPUT 0
680 #define GPIO_DATA_DIRECTION_2_OUTPUT 1
681 #define GPIO_DATA_DIRECTION_1 131
682 #define GPIO_DATA_DIRECTION_1_INPUT 0
683 #define GPIO_DATA_DIRECTION_1_OUTPUT 1
684 #define GPIO_DATA_DIRECTION_0 0:0
685 #define GPIO_DATA_DIRECTION_0_INPUT 0
686 #define GPIO_DATA_DIRECTION_0_OUTPUT 1
688 #define GPIO_INTERRUPT_SETUP 0x010008
689 #define GPIO_INTERRUPT_SETUP_TRIGGER_31 22:22
690 #define GPIO_INTERRUPT_SETUP_TRIGGER_31_EDGE 0
691 #define GPIO_INTERRUPT_SETUP_TRIGGER_31_LEVEL 1
692 #define GPIO_INTERRUPT_SETUP_TRIGGER_30 21:21
693 #define GPIO_INTERRUPT_SETUP_TRIGGER_30_EDGE 0
694 #define GPIO_INTERRUPT_SETUP_TRIGGER_30_LEVEL 1
695 #define GPIO_INTERRUPT_SETUP_TRIGGER_29 20:20
696 #define GPIO_INTERRUPT_SETUP_TRIGGER_29_EDGE 0
697 #define GPIO_INTERRUPT_SETUP_TRIGGER_29_LEVEL 1
698 #define GPIO_INTERRUPT_SETUP_TRIGGER_28 19:19
699 #define GPIO_INTERRUPT_SETUP_TRIGGER_28_EDGE 0
700 #define GPIO_INTERRUPT_SETUP_TRIGGER_28_LEVEL 1
701 #define GPIO_INTERRUPT_SETUP_TRIGGER_27 18:18
702 #define GPIO_INTERRUPT_SETUP_TRIGGER_27_EDGE 0
703 #define GPIO_INTERRUPT_SETUP_TRIGGER_27_LEVEL 1
704 #define GPIO_INTERRUPT_SETUP_TRIGGER_26 17:17
705 #define GPIO_INTERRUPT_SETUP_TRIGGER_26_EDGE 0
706 #define GPIO_INTERRUPT_SETUP_TRIGGER_26_LEVEL 1
707 #define GPIO_INTERRUPT_SETUP_TRIGGER_25 16:16
708 #define GPIO_INTERRUPT_SETUP_TRIGGER_25_EDGE 0
709 #define GPIO_INTERRUPT_SETUP_TRIGGER_25_LEVEL 1
710 #define GPIO_INTERRUPT_SETUP_ACTIVE_31 14:14
711 #define GPIO_INTERRUPT_SETUP_ACTIVE_31_LOW 0
712 #define GPIO_INTERRUPT_SETUP_ACTIVE_31_HIGH 1
713 #define GPIO_INTERRUPT_SETUP_ACTIVE_30 13:13
714 #define GPIO_INTERRUPT_SETUP_ACTIVE_30_LOW 0
715 #define GPIO_INTERRUPT_SETUP_ACTIVE_30_HIGH 1
716 #define GPIO_INTERRUPT_SETUP_ACTIVE_29 12:12
717 #define GPIO_INTERRUPT_SETUP_ACTIVE_29_LOW 0
718 #define GPIO_INTERRUPT_SETUP_ACTIVE_29_HIGH 1
719 #define GPIO_INTERRUPT_SETUP_ACTIVE_28 11:11
720 #define GPIO_INTERRUPT_SETUP_ACTIVE_28_LOW 0
721 #define GPIO_INTERRUPT_SETUP_ACTIVE_28_HIGH 1
722 #define GPIO_INTERRUPT_SETUP_ACTIVE_27 10:10
723 #define GPIO_INTERRUPT_SETUP_ACTIVE_27_LOW 0
724 #define GPIO_INTERRUPT_SETUP_ACTIVE_27_HIGH 1
725 #define GPIO_INTERRUPT_SETUP_ACTIVE_26 9:9
726 #define GPIO_INTERRUPT_SETUP_ACTIVE_26_LOW 0
727 #define GPIO_INTERRUPT_SETUP_ACTIVE_26_HIGH 1
728 #define GPIO_INTERRUPT_SETUP_ACTIVE_25 8:8
729 #define GPIO_INTERRUPT_SETUP_ACTIVE_25_LOW 0
730 #define GPIO_INTERRUPT_SETUP_ACTIVE_25_HIGH 1
731 #define GPIO_INTERRUPT_SETUP_ENABLE_31 6:6
732 #define GPIO_INTERRUPT_SETUP_ENABLE_31_GPIO 0
733 #define GPIO_INTERRUPT_SETUP_ENABLE_31_INTERRUPT 1
734 #define GPIO_INTERRUPT_SETUP_ENABLE_30 5:5
735 #define GPIO_INTERRUPT_SETUP_ENABLE_30_GPIO 0
736 #define GPIO_INTERRUPT_SETUP_ENABLE_30_INTERRUPT 1
737 #define GPIO_INTERRUPT_SETUP_ENABLE_29 4:4
738 #define GPIO_INTERRUPT_SETUP_ENABLE_29_GPIO 0
739 #define GPIO_INTERRUPT_SETUP_ENABLE_29_INTERRUPT 1
740 #define GPIO_INTERRUPT_SETUP_ENABLE_28 3:3
741 #define GPIO_INTERRUPT_SETUP_ENABLE_28_GPIO 0
742 #define GPIO_INTERRUPT_SETUP_ENABLE_28_INTERRUPT 1
743 #define GPIO_INTERRUPT_SETUP_ENABLE_27 2:2
744 #define GPIO_INTERRUPT_SETUP_ENABLE_27_GPIO 0
745 #define GPIO_INTERRUPT_SETUP_ENABLE_27_INTERRUPT 1
746 #define GPIO_INTERRUPT_SETUP_ENABLE_26 1:1
747 #define GPIO_INTERRUPT_SETUP_ENABLE_26_GPIO 0
748 #define GPIO_INTERRUPT_SETUP_ENABLE_26_INTERRUPT 1
749 #define GPIO_INTERRUPT_SETUP_ENABLE_25 0:0
750 #define GPIO_INTERRUPT_SETUP_ENABLE_25_GPIO 0
751 #define GPIO_INTERRUPT_SETUP_ENABLE_25_INTERRUPT 1
753 #define GPIO_INTERRUPT_STATUS 0x01000C
754 #define GPIO_INTERRUPT_STATUS_31 22:22
755 #define GPIO_INTERRUPT_STATUS_31_INACTIVE 0
756 #define GPIO_INTERRUPT_STATUS_31_ACTIVE 1
757 #define GPIO_INTERRUPT_STATUS_31_RESET 1
758 #define GPIO_INTERRUPT_STATUS_30 21:21
759 #define GPIO_INTERRUPT_STATUS_30_INACTIVE 0
760 #define GPIO_INTERRUPT_STATUS_30_ACTIVE 1
761 #define GPIO_INTERRUPT_STATUS_30_RESET 1
762 #define GPIO_INTERRUPT_STATUS_29 20:20
763 #define GPIO_INTERRUPT_STATUS_29_INACTIVE 0
764 #define GPIO_INTERRUPT_STATUS_29_ACTIVE 1
765 #define GPIO_INTERRUPT_STATUS_29_RESET 1
766 #define GPIO_INTERRUPT_STATUS_28 19:19
767 #define GPIO_INTERRUPT_STATUS_28_INACTIVE 0
768 #define GPIO_INTERRUPT_STATUS_28_ACTIVE 1
769 #define GPIO_INTERRUPT_STATUS_28_RESET 1
770 #define GPIO_INTERRUPT_STATUS_27 18:18
771 #define GPIO_INTERRUPT_STATUS_27_INACTIVE 0
772 #define GPIO_INTERRUPT_STATUS_27_ACTIVE 1
773 #define GPIO_INTERRUPT_STATUS_27_RESET 1
774 #define GPIO_INTERRUPT_STATUS_26 17:17
775 #define GPIO_INTERRUPT_STATUS_26_INACTIVE 0
776 #define GPIO_INTERRUPT_STATUS_26_ACTIVE 1
777 #define GPIO_INTERRUPT_STATUS_26_RESET 1
778 #define GPIO_INTERRUPT_STATUS_25 16:16
779 #define GPIO_INTERRUPT_STATUS_25_INACTIVE 0
780 #define GPIO_INTERRUPT_STATUS_25_ACTIVE 1
781 #define GPIO_INTERRUPT_STATUS_25_RESET 1
784 #define PANEL_DISPLAY_CTRL 0x080000
785 #define PANEL_DISPLAY_CTRL_RESERVED_1_MASK 31:30
786 #define PANEL_DISPLAY_CTRL_RESERVED_1_MASK_DISABLE 0
787 #define PANEL_DISPLAY_CTRL_RESERVED_1_MASK_ENABLE 3
788 #define PANEL_DISPLAY_CTRL_SELECT 29:28
789 #define PANEL_DISPLAY_CTRL_SELECT_PANEL 0
790 #define PANEL_DISPLAY_CTRL_SELECT_VGA 1
791 #define PANEL_DISPLAY_CTRL_SELECT_CRT 2
792 #define PANEL_DISPLAY_CTRL_FPEN 27:27
793 #define PANEL_DISPLAY_CTRL_FPEN_LOW 0
794 #define PANEL_DISPLAY_CTRL_FPEN_HIGH 1
795 #define PANEL_DISPLAY_CTRL_VBIASEN 26:26
796 #define PANEL_DISPLAY_CTRL_VBIASEN_LOW 0
797 #define PANEL_DISPLAY_CTRL_VBIASEN_HIGH 1
798 #define PANEL_DISPLAY_CTRL_DATA 25:25
799 #define PANEL_DISPLAY_CTRL_DATA_DISABLE 0
800 #define PANEL_DISPLAY_CTRL_DATA_ENABLE 1
801 #define PANEL_DISPLAY_CTRL_FPVDDEN 24:24
802 #define PANEL_DISPLAY_CTRL_FPVDDEN_LOW 0
803 #define PANEL_DISPLAY_CTRL_FPVDDEN_HIGH 1
804 #define PANEL_DISPLAY_CTRL_RESERVED_2_MASK 23:20
805 #define PANEL_DISPLAY_CTRL_RESERVED_2_MASK_DISABLE 0
806 #define PANEL_DISPLAY_CTRL_RESERVED_2_MASK_ENABLE 15
808 #define PANEL_DISPLAY_CTRL_TFT_DISP 19:18
809 #define PANEL_DISPLAY_CTRL_TFT_DISP_24 0
810 #define PANEL_DISPLAY_CTRL_TFT_DISP_36 1
811 #define PANEL_DISPLAY_CTRL_TFT_DISP_18 2
814 #define PANEL_DISPLAY_CTRL_DUAL_DISPLAY 19:19
815 #define PANEL_DISPLAY_CTRL_DUAL_DISPLAY_DISABLE 0
816 #define PANEL_DISPLAY_CTRL_DUAL_DISPLAY_ENABLE 1
817 #define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL 18:18
818 #define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL_DISABLE 0
819 #define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL_ENABLE 1
820 #define PANEL_DISPLAY_CTRL_FIFO 17:16
821 #define PANEL_DISPLAY_CTRL_FIFO_1 0
822 #define PANEL_DISPLAY_CTRL_FIFO_3 1
823 #define PANEL_DISPLAY_CTRL_FIFO_7 2
824 #define PANEL_DISPLAY_CTRL_FIFO_11 3
825 #define PANEL_DISPLAY_CTRL_RESERVED_3_MASK 15:15
826 #define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE 0
827 #define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE 1
828 #define PANEL_DISPLAY_CTRL_CLOCK_PHASE 14:14
829 #define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0
830 #define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1
831 #define PANEL_DISPLAY_CTRL_VSYNC_PHASE 13:13
832 #define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0
833 #define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1
834 #define PANEL_DISPLAY_CTRL_HSYNC_PHASE 12:12
835 #define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0
836 #define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1
837 #define PANEL_DISPLAY_CTRL_VSYNC 11:11
838 #define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_HIGH 0
839 #define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_LOW 1
840 #define PANEL_DISPLAY_CTRL_CAPTURE_TIMING 10:10
841 #define PANEL_DISPLAY_CTRL_CAPTURE_TIMING_DISABLE 0
842 #define PANEL_DISPLAY_CTRL_CAPTURE_TIMING_ENABLE 1
843 #define PANEL_DISPLAY_CTRL_COLOR_KEY 9:9
844 #define PANEL_DISPLAY_CTRL_COLOR_KEY_DISABLE 0
845 #define PANEL_DISPLAY_CTRL_COLOR_KEY_ENABLE 1
846 #define PANEL_DISPLAY_CTRL_TIMING 8:8
847 #define PANEL_DISPLAY_CTRL_TIMING_DISABLE 0
848 #define PANEL_DISPLAY_CTRL_TIMING_ENABLE 1
849 #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR 7:7
850 #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_DOWN 0
851 #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_UP 1
852 #define PANEL_DISPLAY_CTRL_VERTICAL_PAN 6:6
853 #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DISABLE 0
854 #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_ENABLE 1
855 #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR 5:5
856 #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_RIGHT 0
857 #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_LEFT 1
858 #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN 4:4
859 #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DISABLE 0
860 #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_ENABLE 1
861 #define PANEL_DISPLAY_CTRL_GAMMA 3:3
862 #define PANEL_DISPLAY_CTRL_GAMMA_DISABLE 0
863 #define PANEL_DISPLAY_CTRL_GAMMA_ENABLE 1
864 #define PANEL_DISPLAY_CTRL_PLANE 2:2
865 #define PANEL_DISPLAY_CTRL_PLANE_DISABLE 0
866 #define PANEL_DISPLAY_CTRL_PLANE_ENABLE 1
867 #define PANEL_DISPLAY_CTRL_FORMAT 1:0
868 #define PANEL_DISPLAY_CTRL_FORMAT_8 0
869 #define PANEL_DISPLAY_CTRL_FORMAT_16 1
870 #define PANEL_DISPLAY_CTRL_FORMAT_32 2
872 #define PANEL_PAN_CTRL 0x080004
873 #define PANEL_PAN_CTRL_VERTICAL_PAN 31:24
874 #define PANEL_PAN_CTRL_VERTICAL_VSYNC 21:16
875 #define PANEL_PAN_CTRL_HORIZONTAL_PAN 15:8
876 #define PANEL_PAN_CTRL_HORIZONTAL_VSYNC 5:0
878 #define PANEL_COLOR_KEY 0x080008
879 #define PANEL_COLOR_KEY_MASK 31:16
880 #define PANEL_COLOR_KEY_VALUE 15:0
882 #define PANEL_FB_ADDRESS 0x08000C
883 #define PANEL_FB_ADDRESS_STATUS 31:31
884 #define PANEL_FB_ADDRESS_STATUS_CURRENT 0
885 #define PANEL_FB_ADDRESS_STATUS_PENDING 1
886 #define PANEL_FB_ADDRESS_EXT 27:27
887 #define PANEL_FB_ADDRESS_EXT_LOCAL 0
888 #define PANEL_FB_ADDRESS_EXT_EXTERNAL 1
889 #define PANEL_FB_ADDRESS_ADDRESS 25:0
891 #define PANEL_FB_WIDTH 0x080010
892 #define PANEL_FB_WIDTH_WIDTH 29:16
893 #define PANEL_FB_WIDTH_OFFSET 13:0
895 #define PANEL_WINDOW_WIDTH 0x080014
896 #define PANEL_WINDOW_WIDTH_WIDTH 27:16
897 #define PANEL_WINDOW_WIDTH_X 11:0
899 #define PANEL_WINDOW_HEIGHT 0x080018
900 #define PANEL_WINDOW_HEIGHT_HEIGHT 27:16
901 #define PANEL_WINDOW_HEIGHT_Y 11:0
903 #define PANEL_PLANE_TL 0x08001C
904 #define PANEL_PLANE_TL_TOP 26:16
905 #define PANEL_PLANE_TL_LEFT 10:0
907 #define PANEL_PLANE_BR 0x080020
908 #define PANEL_PLANE_BR_BOTTOM 26:16
909 #define PANEL_PLANE_BR_RIGHT 10:0
911 #define PANEL_HORIZONTAL_TOTAL 0x080024
912 #define PANEL_HORIZONTAL_TOTAL_TOTAL 27:16
913 #define PANEL_HORIZONTAL_TOTAL_DISPLAY_END 11:0
915 #define PANEL_HORIZONTAL_SYNC 0x080028
916 #define PANEL_HORIZONTAL_SYNC_WIDTH 23:16
917 #define PANEL_HORIZONTAL_SYNC_START 11:0
919 #define PANEL_VERTICAL_TOTAL 0x08002C
920 #define PANEL_VERTICAL_TOTAL_TOTAL 26:16
921 #define PANEL_VERTICAL_TOTAL_DISPLAY_END 10:0
923 #define PANEL_VERTICAL_SYNC 0x080030
924 #define PANEL_VERTICAL_SYNC_HEIGHT 21:16
925 #define PANEL_VERTICAL_SYNC_START 10:0
927 #define PANEL_CURRENT_LINE 0x080034
928 #define PANEL_CURRENT_LINE_LINE 10:0
932 #define VIDEO_DISPLAY_CTRL 0x080040
933 #define VIDEO_DISPLAY_CTRL_LINE_BUFFER 18:18
934 #define VIDEO_DISPLAY_CTRL_LINE_BUFFER_DISABLE 0
935 #define VIDEO_DISPLAY_CTRL_LINE_BUFFER_ENABLE 1
936 #define VIDEO_DISPLAY_CTRL_FIFO 17:16
937 #define VIDEO_DISPLAY_CTRL_FIFO_1 0
938 #define VIDEO_DISPLAY_CTRL_FIFO_3 1
939 #define VIDEO_DISPLAY_CTRL_FIFO_7 2
940 #define VIDEO_DISPLAY_CTRL_FIFO_11 3
941 #define VIDEO_DISPLAY_CTRL_BUFFER 15:15
942 #define VIDEO_DISPLAY_CTRL_BUFFER_0 0
943 #define VIDEO_DISPLAY_CTRL_BUFFER_1 1
944 #define VIDEO_DISPLAY_CTRL_CAPTURE 14:14
945 #define VIDEO_DISPLAY_CTRL_CAPTURE_DISABLE 0
946 #define VIDEO_DISPLAY_CTRL_CAPTURE_ENABLE 1
947 #define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER 13:13
948 #define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER_DISABLE 0
949 #define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER_ENABLE 1
950 #define VIDEO_DISPLAY_CTRL_BYTE_SWAP 12:12
951 #define VIDEO_DISPLAY_CTRL_BYTE_SWAP_DISABLE 0
952 #define VIDEO_DISPLAY_CTRL_BYTE_SWAP_ENABLE 1
953 #define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE 11:11
954 #define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE_NORMAL 0
955 #define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE_HALF 1
956 #define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE 10:10
957 #define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE_NORMAL 0
958 #define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE_HALF 1
959 #define VIDEO_DISPLAY_CTRL_VERTICAL_MODE 9:9
960 #define VIDEO_DISPLAY_CTRL_VERTICAL_MODE_REPLICATE 0
961 #define VIDEO_DISPLAY_CTRL_VERTICAL_MODE_INTERPOLATE 1
962 #define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE 8:8
963 #define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE_REPLICATE 0
964 #define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE_INTERPOLATE 1
965 #define VIDEO_DISPLAY_CTRL_PIXEL 7:4
966 #define VIDEO_DISPLAY_CTRL_GAMMA 3:3
967 #define VIDEO_DISPLAY_CTRL_GAMMA_DISABLE 0
968 #define VIDEO_DISPLAY_CTRL_GAMMA_ENABLE 1
969 #define VIDEO_DISPLAY_CTRL_PLANE 2:2
970 #define VIDEO_DISPLAY_CTRL_PLANE_DISABLE 0
971 #define VIDEO_DISPLAY_CTRL_PLANE_ENABLE 1
972 #define VIDEO_DISPLAY_CTRL_FORMAT 1:0
973 #define VIDEO_DISPLAY_CTRL_FORMAT_8 0
974 #define VIDEO_DISPLAY_CTRL_FORMAT_16 1
975 #define VIDEO_DISPLAY_CTRL_FORMAT_32 2
976 #define VIDEO_DISPLAY_CTRL_FORMAT_YUV 3
978 #define VIDEO_FB_0_ADDRESS 0x080044
979 #define VIDEO_FB_0_ADDRESS_STATUS 31:31
980 #define VIDEO_FB_0_ADDRESS_STATUS_CURRENT 0
981 #define VIDEO_FB_0_ADDRESS_STATUS_PENDING 1
982 #define VIDEO_FB_0_ADDRESS_EXT 27:27
983 #define VIDEO_FB_0_ADDRESS_EXT_LOCAL 0
984 #define VIDEO_FB_0_ADDRESS_EXT_EXTERNAL 1
985 #define VIDEO_FB_0_ADDRESS_ADDRESS 25:0
987 #define VIDEO_FB_WIDTH 0x080048
988 #define VIDEO_FB_WIDTH_WIDTH 29:16
989 #define VIDEO_FB_WIDTH_OFFSET 13:0
991 #define VIDEO_FB_0_LAST_ADDRESS 0x08004C
992 #define VIDEO_FB_0_LAST_ADDRESS_EXT 27:27
993 #define VIDEO_FB_0_LAST_ADDRESS_EXT_LOCAL 0
994 #define VIDEO_FB_0_LAST_ADDRESS_EXT_EXTERNAL 1
995 #define VIDEO_FB_0_LAST_ADDRESS_ADDRESS 25:0
997 #define VIDEO_PLANE_TL 0x080050
998 #define VIDEO_PLANE_TL_TOP 26:16
999 #define VIDEO_PLANE_TL_LEFT 10:0
1001 #define VIDEO_PLANE_BR 0x080054
1002 #define VIDEO_PLANE_BR_BOTTOM 26:16
1003 #define VIDEO_PLANE_BR_RIGHT 10:0
1005 #define VIDEO_SCALE 0x080058
1006 #define VIDEO_SCALE_VERTICAL_MODE 31:31
1007 #define VIDEO_SCALE_VERTICAL_MODE_EXPAND 0
1008 #define VIDEO_SCALE_VERTICAL_MODE_SHRINK 1
1009 #define VIDEO_SCALE_VERTICAL_SCALE 27:16
1010 #define VIDEO_SCALE_HORIZONTAL_MODE 15:15
1011 #define VIDEO_SCALE_HORIZONTAL_MODE_EXPAND 0
1012 #define VIDEO_SCALE_HORIZONTAL_MODE_SHRINK 1
1013 #define VIDEO_SCALE_HORIZONTAL_SCALE 11:0
1015 #define VIDEO_INITIAL_SCALE 0x08005C
1016 #define VIDEO_INITIAL_SCALE_FB_1 27:16
1017 #define VIDEO_INITIAL_SCALE_FB_0 11:0
1019 #define VIDEO_YUV_CONSTANTS 0x080060
1020 #define VIDEO_YUV_CONSTANTS_Y 31:24
1021 #define VIDEO_YUV_CONSTANTS_R 23:16
1022 #define VIDEO_YUV_CONSTANTS_G 15:8
1023 #define VIDEO_YUV_CONSTANTS_B 7:0
1025 #define VIDEO_FB_1_ADDRESS 0x080064
1026 #define VIDEO_FB_1_ADDRESS_STATUS 31:31
1027 #define VIDEO_FB_1_ADDRESS_STATUS_CURRENT 0
1028 #define VIDEO_FB_1_ADDRESS_STATUS_PENDING 1
1029 #define VIDEO_FB_1_ADDRESS_EXT 27:27
1030 #define VIDEO_FB_1_ADDRESS_EXT_LOCAL 0
1031 #define VIDEO_FB_1_ADDRESS_EXT_EXTERNAL 1
1032 #define VIDEO_FB_1_ADDRESS_ADDRESS 25:0
1034 #define VIDEO_FB_1_LAST_ADDRESS 0x080068
1035 #define VIDEO_FB_1_LAST_ADDRESS_EXT 27:27
1036 #define VIDEO_FB_1_LAST_ADDRESS_EXT_LOCAL 0
1037 #define VIDEO_FB_1_LAST_ADDRESS_EXT_EXTERNAL 1
1038 #define VIDEO_FB_1_LAST_ADDRESS_ADDRESS 25:0
1040 /* Video Alpha Control */
1042 #define VIDEO_ALPHA_DISPLAY_CTRL 0x080080
1043 #define VIDEO_ALPHA_DISPLAY_CTRL_SELECT 28:28
1044 #define VIDEO_ALPHA_DISPLAY_CTRL_SELECT_PER_PIXEL 0
1045 #define VIDEO_ALPHA_DISPLAY_CTRL_SELECT_ALPHA 1
1046 #define VIDEO_ALPHA_DISPLAY_CTRL_ALPHA 27:24
1047 #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO 17:16
1048 #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_1 0
1049 #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_3 1
1050 #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_7 2
1051 #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_11 3
1052 #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE 11:11
1053 #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE_NORMAL 0
1054 #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE_HALF 1
1055 #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE 10:10
1056 #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE_NORMAL 0
1057 #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE_HALF 1
1058 #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE 9:9
1059 #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE_REPLICATE 0
1060 #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE_INTERPOLATE 1
1061 #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE 8:8
1062 #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE_REPLICATE 0
1063 #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE_INTERPOLATE 1
1064 #define VIDEO_ALPHA_DISPLAY_CTRL_PIXEL 7:4
1065 #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3
1066 #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0
1067 #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1
1068 #define VIDEO_ALPHA_DISPLAY_CTRL_PLANE 2:2
1069 #define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_DISABLE 0
1070 #define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_ENABLE 1
1071 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT 1:0
1072 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8 0
1073 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16 1
1074 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 2
1075 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4 3
1077 #define VIDEO_ALPHA_FB_ADDRESS 0x080084
1078 #define VIDEO_ALPHA_FB_ADDRESS_STATUS 31:31
1079 #define VIDEO_ALPHA_FB_ADDRESS_STATUS_CURRENT 0
1080 #define VIDEO_ALPHA_FB_ADDRESS_STATUS_PENDING 1
1081 #define VIDEO_ALPHA_FB_ADDRESS_EXT 27:27
1082 #define VIDEO_ALPHA_FB_ADDRESS_EXT_LOCAL 0
1083 #define VIDEO_ALPHA_FB_ADDRESS_EXT_EXTERNAL 1
1084 #define VIDEO_ALPHA_FB_ADDRESS_ADDRESS 25:0
1086 #define VIDEO_ALPHA_FB_WIDTH 0x080088
1087 #define VIDEO_ALPHA_FB_WIDTH_WIDTH 29:16
1088 #define VIDEO_ALPHA_FB_WIDTH_OFFSET 13:0
1090 #define VIDEO_ALPHA_FB_LAST_ADDRESS 0x08008C
1091 #define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT 27:27
1092 #define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT_LOCAL 0
1093 #define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT_EXTERNAL 1
1094 #define VIDEO_ALPHA_FB_LAST_ADDRESS_ADDRESS 25:0
1096 #define VIDEO_ALPHA_PLANE_TL 0x080090
1097 #define VIDEO_ALPHA_PLANE_TL_TOP 26:16
1098 #define VIDEO_ALPHA_PLANE_TL_LEFT 10:0
1100 #define VIDEO_ALPHA_PLANE_BR 0x080094
1101 #define VIDEO_ALPHA_PLANE_BR_BOTTOM 26:16
1102 #define VIDEO_ALPHA_PLANE_BR_RIGHT 10:0
1104 #define VIDEO_ALPHA_SCALE 0x080098
1105 #define VIDEO_ALPHA_SCALE_VERTICAL_MODE 31:31
1106 #define VIDEO_ALPHA_SCALE_VERTICAL_MODE_EXPAND 0
1107 #define VIDEO_ALPHA_SCALE_VERTICAL_MODE_SHRINK 1
1108 #define VIDEO_ALPHA_SCALE_VERTICAL_SCALE 27:16
1109 #define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE 15:15
1110 #define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE_EXPAND 0
1111 #define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE_SHRINK 1
1112 #define VIDEO_ALPHA_SCALE_HORIZONTAL_SCALE 11:0
1114 #define VIDEO_ALPHA_INITIAL_SCALE 0x08009C
1115 #define VIDEO_ALPHA_INITIAL_SCALE_VERTICAL 27:16
1116 #define VIDEO_ALPHA_INITIAL_SCALE_HORIZONTAL 11:0
1118 #define VIDEO_ALPHA_CHROMA_KEY 0x0800A0
1119 #define VIDEO_ALPHA_CHROMA_KEY_MASK 31:16
1120 #define VIDEO_ALPHA_CHROMA_KEY_VALUE 15:0
1122 #define VIDEO_ALPHA_COLOR_LOOKUP_01 0x0800A4
1123 #define VIDEO_ALPHA_COLOR_LOOKUP_01_1 31:16
1124 #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_RED 31:27
1125 #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_GREEN 26:21
1126 #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_BLUE 20:16
1127 #define VIDEO_ALPHA_COLOR_LOOKUP_01_0 15:0
1128 #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_RED 15:11
1129 #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_GREEN 10:5
1130 #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_BLUE 4:0
1132 #define VIDEO_ALPHA_COLOR_LOOKUP_23 0x0800A8
1133 #define VIDEO_ALPHA_COLOR_LOOKUP_23_3 31:16
1134 #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_RED 31:27
1135 #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_GREEN 26:21
1136 #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_BLUE 20:16
1137 #define VIDEO_ALPHA_COLOR_LOOKUP_23_2 15:0
1138 #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_RED 15:11
1139 #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_GREEN 10:5
1140 #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_BLUE 4:0
1142 #define VIDEO_ALPHA_COLOR_LOOKUP_45 0x0800AC
1143 #define VIDEO_ALPHA_COLOR_LOOKUP_45_5 31:16
1144 #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_RED 31:27
1145 #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_GREEN 26:21
1146 #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_BLUE 20:16
1147 #define VIDEO_ALPHA_COLOR_LOOKUP_45_4 15:0
1148 #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_RED 15:11
1149 #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_GREEN 10:5
1150 #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_BLUE 4:0
1152 #define VIDEO_ALPHA_COLOR_LOOKUP_67 0x0800B0
1153 #define VIDEO_ALPHA_COLOR_LOOKUP_67_7 31:16
1154 #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_RED 31:27
1155 #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_GREEN 26:21
1156 #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_BLUE 20:16
1157 #define VIDEO_ALPHA_COLOR_LOOKUP_67_6 15:0
1158 #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_RED 15:11
1159 #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_GREEN 10:5
1160 #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_BLUE 4:0
1162 #define VIDEO_ALPHA_COLOR_LOOKUP_89 0x0800B4
1163 #define VIDEO_ALPHA_COLOR_LOOKUP_89_9 31:16
1164 #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_RED 31:27
1165 #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_GREEN 26:21
1166 #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_BLUE 20:16
1167 #define VIDEO_ALPHA_COLOR_LOOKUP_89_8 15:0
1168 #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_RED 15:11
1169 #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_GREEN 10:5
1170 #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_BLUE 4:0
1172 #define VIDEO_ALPHA_COLOR_LOOKUP_AB 0x0800B8
1173 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B 31:16
1174 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_RED 31:27
1175 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_GREEN 26:21
1176 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_BLUE 20:16
1177 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A 15:0
1178 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_RED 15:11
1179 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_GREEN 10:5
1180 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_BLUE 4:0
1182 #define VIDEO_ALPHA_COLOR_LOOKUP_CD 0x0800BC
1183 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D 31:16
1184 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_RED 31:27
1185 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_GREEN 26:21
1186 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_BLUE 20:16
1187 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C 15:0
1188 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_RED 15:11
1189 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_GREEN 10:5
1190 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_BLUE 4:0
1192 #define VIDEO_ALPHA_COLOR_LOOKUP_EF 0x0800C0
1193 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F 31:16
1194 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_RED 31:27
1195 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_GREEN 26:21
1196 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_BLUE 20:16
1197 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E 15:0
1198 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_RED 15:11
1199 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_GREEN 10:5
1200 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_BLUE 4:0
1202 /* Panel Cursor Control */
1204 #define PANEL_HWC_ADDRESS 0x0800F0
1205 #define PANEL_HWC_ADDRESS_ENABLE 31:31
1206 #define PANEL_HWC_ADDRESS_ENABLE_DISABLE 0
1207 #define PANEL_HWC_ADDRESS_ENABLE_ENABLE 1
1208 #define PANEL_HWC_ADDRESS_EXT 27:27
1209 #define PANEL_HWC_ADDRESS_EXT_LOCAL 0
1210 #define PANEL_HWC_ADDRESS_EXT_EXTERNAL 1
1211 #define PANEL_HWC_ADDRESS_ADDRESS 25:0
1213 #define PANEL_HWC_LOCATION 0x0800F4
1214 #define PANEL_HWC_LOCATION_TOP 27:27
1215 #define PANEL_HWC_LOCATION_TOP_INSIDE 0
1216 #define PANEL_HWC_LOCATION_TOP_OUTSIDE 1
1217 #define PANEL_HWC_LOCATION_Y 26:16
1218 #define PANEL_HWC_LOCATION_LEFT 11:11
1219 #define PANEL_HWC_LOCATION_LEFT_INSIDE 0
1220 #define PANEL_HWC_LOCATION_LEFT_OUTSIDE 1
1221 #define PANEL_HWC_LOCATION_X 10:0
1223 #define PANEL_HWC_COLOR_12 0x0800F8
1224 #define PANEL_HWC_COLOR_12_2_RGB565 31:16
1225 #define PANEL_HWC_COLOR_12_1_RGB565 15:0
1227 #define PANEL_HWC_COLOR_3 0x0800FC
1228 #define PANEL_HWC_COLOR_3_RGB565 15:0
1230 /* Old Definitions +++ */
1231 #define PANEL_HWC_COLOR_01 0x0800F8
1232 #define PANEL_HWC_COLOR_01_1_RED 31:27
1233 #define PANEL_HWC_COLOR_01_1_GREEN 26:21
1234 #define PANEL_HWC_COLOR_01_1_BLUE 20:16
1235 #define PANEL_HWC_COLOR_01_0_RED 15:11
1236 #define PANEL_HWC_COLOR_01_0_GREEN 10:5
1237 #define PANEL_HWC_COLOR_01_0_BLUE 4:0
1239 #define PANEL_HWC_COLOR_2 0x0800FC
1240 #define PANEL_HWC_COLOR_2_RED 15:11
1241 #define PANEL_HWC_COLOR_2_GREEN 10:5
1242 #define PANEL_HWC_COLOR_2_BLUE 4:0
1243 /* Old Definitions --- */
1247 #define ALPHA_DISPLAY_CTRL 0x080100
1248 #define ALPHA_DISPLAY_CTRL_SELECT 28:28
1249 #define ALPHA_DISPLAY_CTRL_SELECT_PER_PIXEL 0
1250 #define ALPHA_DISPLAY_CTRL_SELECT_ALPHA 1
1251 #define ALPHA_DISPLAY_CTRL_ALPHA 27:24
1252 #define ALPHA_DISPLAY_CTRL_FIFO 17:16
1253 #define ALPHA_DISPLAY_CTRL_FIFO_1 0
1254 #define ALPHA_DISPLAY_CTRL_FIFO_3 1
1255 #define ALPHA_DISPLAY_CTRL_FIFO_7 2
1256 #define ALPHA_DISPLAY_CTRL_FIFO_11 3
1257 #define ALPHA_DISPLAY_CTRL_PIXEL 7:4
1258 #define ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3
1259 #define ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0
1260 #define ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1
1261 #define ALPHA_DISPLAY_CTRL_PLANE 2:2
1262 #define ALPHA_DISPLAY_CTRL_PLANE_DISABLE 0
1263 #define ALPHA_DISPLAY_CTRL_PLANE_ENABLE 1
1264 #define ALPHA_DISPLAY_CTRL_FORMAT 1:0
1265 #define ALPHA_DISPLAY_CTRL_FORMAT_16 1
1266 #define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 2
1267 #define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4 3
1269 #define ALPHA_FB_ADDRESS 0x080104
1270 #define ALPHA_FB_ADDRESS_STATUS 31:31
1271 #define ALPHA_FB_ADDRESS_STATUS_CURRENT 0
1272 #define ALPHA_FB_ADDRESS_STATUS_PENDING 1
1273 #define ALPHA_FB_ADDRESS_EXT 27:27
1274 #define ALPHA_FB_ADDRESS_EXT_LOCAL 0
1275 #define ALPHA_FB_ADDRESS_EXT_EXTERNAL 1
1276 #define ALPHA_FB_ADDRESS_ADDRESS 25:0
1278 #define ALPHA_FB_WIDTH 0x080108
1279 #define ALPHA_FB_WIDTH_WIDTH 29:16
1280 #define ALPHA_FB_WIDTH_OFFSET 13:0
1282 #define ALPHA_PLANE_TL 0x08010C
1283 #define ALPHA_PLANE_TL_TOP 26:16
1284 #define ALPHA_PLANE_TL_LEFT 10:0
1286 #define ALPHA_PLANE_BR 0x080110
1287 #define ALPHA_PLANE_BR_BOTTOM 26:16
1288 #define ALPHA_PLANE_BR_RIGHT 10:0
1290 #define ALPHA_CHROMA_KEY 0x080114
1291 #define ALPHA_CHROMA_KEY_MASK 31:16
1292 #define ALPHA_CHROMA_KEY_VALUE 15:0
1294 #define ALPHA_COLOR_LOOKUP_01 0x080118
1295 #define ALPHA_COLOR_LOOKUP_01_1 31:16
1296 #define ALPHA_COLOR_LOOKUP_01_1_RED 31:27
1297 #define ALPHA_COLOR_LOOKUP_01_1_GREEN 26:21
1298 #define ALPHA_COLOR_LOOKUP_01_1_BLUE 20:16
1299 #define ALPHA_COLOR_LOOKUP_01_0 15:0
1300 #define ALPHA_COLOR_LOOKUP_01_0_RED 15:11
1301 #define ALPHA_COLOR_LOOKUP_01_0_GREEN 10:5
1302 #define ALPHA_COLOR_LOOKUP_01_0_BLUE 4:0
1304 #define ALPHA_COLOR_LOOKUP_23 0x08011C
1305 #define ALPHA_COLOR_LOOKUP_23_3 31:16
1306 #define ALPHA_COLOR_LOOKUP_23_3_RED 31:27
1307 #define ALPHA_COLOR_LOOKUP_23_3_GREEN 26:21
1308 #define ALPHA_COLOR_LOOKUP_23_3_BLUE 20:16
1309 #define ALPHA_COLOR_LOOKUP_23_2 15:0
1310 #define ALPHA_COLOR_LOOKUP_23_2_RED 15:11
1311 #define ALPHA_COLOR_LOOKUP_23_2_GREEN 10:5
1312 #define ALPHA_COLOR_LOOKUP_23_2_BLUE 4:0
1314 #define ALPHA_COLOR_LOOKUP_45 0x080120
1315 #define ALPHA_COLOR_LOOKUP_45_5 31:16
1316 #define ALPHA_COLOR_LOOKUP_45_5_RED 31:27
1317 #define ALPHA_COLOR_LOOKUP_45_5_GREEN 26:21
1318 #define ALPHA_COLOR_LOOKUP_45_5_BLUE 20:16
1319 #define ALPHA_COLOR_LOOKUP_45_4 15:0
1320 #define ALPHA_COLOR_LOOKUP_45_4_RED 15:11
1321 #define ALPHA_COLOR_LOOKUP_45_4_GREEN 10:5
1322 #define ALPHA_COLOR_LOOKUP_45_4_BLUE 4:0
1324 #define ALPHA_COLOR_LOOKUP_67 0x080124
1325 #define ALPHA_COLOR_LOOKUP_67_7 31:16
1326 #define ALPHA_COLOR_LOOKUP_67_7_RED 31:27
1327 #define ALPHA_COLOR_LOOKUP_67_7_GREEN 26:21
1328 #define ALPHA_COLOR_LOOKUP_67_7_BLUE 20:16
1329 #define ALPHA_COLOR_LOOKUP_67_6 15:0
1330 #define ALPHA_COLOR_LOOKUP_67_6_RED 15:11
1331 #define ALPHA_COLOR_LOOKUP_67_6_GREEN 10:5
1332 #define ALPHA_COLOR_LOOKUP_67_6_BLUE 4:0
1334 #define ALPHA_COLOR_LOOKUP_89 0x080128
1335 #define ALPHA_COLOR_LOOKUP_89_9 31:16
1336 #define ALPHA_COLOR_LOOKUP_89_9_RED 31:27
1337 #define ALPHA_COLOR_LOOKUP_89_9_GREEN 26:21
1338 #define ALPHA_COLOR_LOOKUP_89_9_BLUE 20:16
1339 #define ALPHA_COLOR_LOOKUP_89_8 15:0
1340 #define ALPHA_COLOR_LOOKUP_89_8_RED 15:11
1341 #define ALPHA_COLOR_LOOKUP_89_8_GREEN 10:5
1342 #define ALPHA_COLOR_LOOKUP_89_8_BLUE 4:0
1344 #define ALPHA_COLOR_LOOKUP_AB 0x08012C
1345 #define ALPHA_COLOR_LOOKUP_AB_B 31:16
1346 #define ALPHA_COLOR_LOOKUP_AB_B_RED 31:27
1347 #define ALPHA_COLOR_LOOKUP_AB_B_GREEN 26:21
1348 #define ALPHA_COLOR_LOOKUP_AB_B_BLUE 20:16
1349 #define ALPHA_COLOR_LOOKUP_AB_A 15:0
1350 #define ALPHA_COLOR_LOOKUP_AB_A_RED 15:11
1351 #define ALPHA_COLOR_LOOKUP_AB_A_GREEN 10:5
1352 #define ALPHA_COLOR_LOOKUP_AB_A_BLUE 4:0
1354 #define ALPHA_COLOR_LOOKUP_CD 0x080130
1355 #define ALPHA_COLOR_LOOKUP_CD_D 31:16
1356 #define ALPHA_COLOR_LOOKUP_CD_D_RED 31:27
1357 #define ALPHA_COLOR_LOOKUP_CD_D_GREEN 26:21
1358 #define ALPHA_COLOR_LOOKUP_CD_D_BLUE 20:16
1359 #define ALPHA_COLOR_LOOKUP_CD_C 15:0
1360 #define ALPHA_COLOR_LOOKUP_CD_C_RED 15:11
1361 #define ALPHA_COLOR_LOOKUP_CD_C_GREEN 10:5
1362 #define ALPHA_COLOR_LOOKUP_CD_C_BLUE 4:0
1364 #define ALPHA_COLOR_LOOKUP_EF 0x080134
1365 #define ALPHA_COLOR_LOOKUP_EF_F 31:16
1366 #define ALPHA_COLOR_LOOKUP_EF_F_RED 31:27
1367 #define ALPHA_COLOR_LOOKUP_EF_F_GREEN 26:21
1368 #define ALPHA_COLOR_LOOKUP_EF_F_BLUE 20:16
1369 #define ALPHA_COLOR_LOOKUP_EF_E 15:0
1370 #define ALPHA_COLOR_LOOKUP_EF_E_RED 15:11
1371 #define ALPHA_COLOR_LOOKUP_EF_E_GREEN 10:5
1372 #define ALPHA_COLOR_LOOKUP_EF_E_BLUE 4:0
1374 /* CRT Graphics Control */
1376 #define CRT_DISPLAY_CTRL 0x080200
1377 #define CRT_DISPLAY_CTRL_RESERVED_1_MASK 31:27
1378 #define CRT_DISPLAY_CTRL_RESERVED_1_MASK_DISABLE 0
1379 #define CRT_DISPLAY_CTRL_RESERVED_1_MASK_ENABLE 0x1F
1381 /* SM750LE definition */
1382 #define CRT_DISPLAY_CTRL_DPMS 31:30
1383 #define CRT_DISPLAY_CTRL_DPMS_0 0
1384 #define CRT_DISPLAY_CTRL_DPMS_1 1
1385 #define CRT_DISPLAY_CTRL_DPMS_2 2
1386 #define CRT_DISPLAY_CTRL_DPMS_3 3
1387 #define CRT_DISPLAY_CTRL_CLK 29:27
1388 #define CRT_DISPLAY_CTRL_CLK_PLL25 0
1389 #define CRT_DISPLAY_CTRL_CLK_PLL41 1
1390 #define CRT_DISPLAY_CTRL_CLK_PLL62 2
1391 #define CRT_DISPLAY_CTRL_CLK_PLL65 3
1392 #define CRT_DISPLAY_CTRL_CLK_PLL74 4
1393 #define CRT_DISPLAY_CTRL_CLK_PLL80 5
1394 #define CRT_DISPLAY_CTRL_CLK_PLL108 6
1395 #define CRT_DISPLAY_CTRL_CLK_RESERVED 7
1396 #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC 26:26
1397 #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_DISABLE 1
1398 #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_ENABLE 0
1401 #define CRT_DISPLAY_CTRL_RESERVED_2_MASK 25:24
1402 #define CRT_DISPLAY_CTRL_RESERVED_2_MASK_ENABLE 3
1403 #define CRT_DISPLAY_CTRL_RESERVED_2_MASK_DISABLE 0
1405 /* SM750LE definition */
1406 #define CRT_DISPLAY_CTRL_CRTSELECT 25:25
1407 #define CRT_DISPLAY_CTRL_CRTSELECT_VGA 0
1408 #define CRT_DISPLAY_CTRL_CRTSELECT_CRT 1
1409 #define CRT_DISPLAY_CTRL_RGBBIT 24:24
1410 #define CRT_DISPLAY_CTRL_RGBBIT_24BIT 0
1411 #define CRT_DISPLAY_CTRL_RGBBIT_12BIT 1
1414 #define CRT_DISPLAY_CTRL_RESERVED_3_MASK 15:15
1415 #define CRT_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE 0
1416 #define CRT_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE 1
1418 #define CRT_DISPLAY_CTRL_RESERVED_4_MASK 9:9
1419 #define CRT_DISPLAY_CTRL_RESERVED_4_MASK_DISABLE 0
1420 #define CRT_DISPLAY_CTRL_RESERVED_4_MASK_ENABLE 1
1422 #ifndef VALIDATION_CHIP
1423 #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC 26:26
1424 #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_DISABLE 1
1425 #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_ENABLE 0
1426 #define CRT_DISPLAY_CTRL_CENTERING 24:24
1427 #define CRT_DISPLAY_CTRL_CENTERING_DISABLE 0
1428 #define CRT_DISPLAY_CTRL_CENTERING_ENABLE 1
1430 #define CRT_DISPLAY_CTRL_LOCK_TIMING 23:23
1431 #define CRT_DISPLAY_CTRL_LOCK_TIMING_DISABLE 0
1432 #define CRT_DISPLAY_CTRL_LOCK_TIMING_ENABLE 1
1433 #define CRT_DISPLAY_CTRL_EXPANSION 22:22
1434 #define CRT_DISPLAY_CTRL_EXPANSION_DISABLE 0
1435 #define CRT_DISPLAY_CTRL_EXPANSION_ENABLE 1
1436 #define CRT_DISPLAY_CTRL_VERTICAL_MODE 21:21
1437 #define CRT_DISPLAY_CTRL_VERTICAL_MODE_REPLICATE 0
1438 #define CRT_DISPLAY_CTRL_VERTICAL_MODE_INTERPOLATE 1
1439 #define CRT_DISPLAY_CTRL_HORIZONTAL_MODE 20:20
1440 #define CRT_DISPLAY_CTRL_HORIZONTAL_MODE_REPLICATE 0
1441 #define CRT_DISPLAY_CTRL_HORIZONTAL_MODE_INTERPOLATE 1
1442 #define CRT_DISPLAY_CTRL_SELECT 19:18
1443 #define CRT_DISPLAY_CTRL_SELECT_PANEL 0
1444 #define CRT_DISPLAY_CTRL_SELECT_VGA 1
1445 #define CRT_DISPLAY_CTRL_SELECT_CRT 2
1446 #define CRT_DISPLAY_CTRL_FIFO 17:16
1447 #define CRT_DISPLAY_CTRL_FIFO_1 0
1448 #define CRT_DISPLAY_CTRL_FIFO_3 1
1449 #define CRT_DISPLAY_CTRL_FIFO_7 2
1450 #define CRT_DISPLAY_CTRL_FIFO_11 3
1451 #define CRT_DISPLAY_CTRL_CLOCK_PHASE 14:14
1452 #define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0
1453 #define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1
1454 #define CRT_DISPLAY_CTRL_VSYNC_PHASE 13:13
1455 #define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0
1456 #define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1
1457 #define CRT_DISPLAY_CTRL_HSYNC_PHASE 12:12
1458 #define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0
1459 #define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1
1460 #define CRT_DISPLAY_CTRL_BLANK 10:10
1461 #define CRT_DISPLAY_CTRL_BLANK_OFF 0
1462 #define CRT_DISPLAY_CTRL_BLANK_ON 1
1463 #define CRT_DISPLAY_CTRL_TIMING 8:8
1464 #define CRT_DISPLAY_CTRL_TIMING_DISABLE 0
1465 #define CRT_DISPLAY_CTRL_TIMING_ENABLE 1
1466 #define CRT_DISPLAY_CTRL_PIXEL 7:4
1467 #define CRT_DISPLAY_CTRL_GAMMA 3:3
1468 #define CRT_DISPLAY_CTRL_GAMMA_DISABLE 0
1469 #define CRT_DISPLAY_CTRL_GAMMA_ENABLE 1
1470 #define CRT_DISPLAY_CTRL_PLANE 2:2
1471 #define CRT_DISPLAY_CTRL_PLANE_DISABLE 0
1472 #define CRT_DISPLAY_CTRL_PLANE_ENABLE 1
1473 #define CRT_DISPLAY_CTRL_FORMAT 1:0
1474 #define CRT_DISPLAY_CTRL_FORMAT_8 0
1475 #define CRT_DISPLAY_CTRL_FORMAT_16 1
1476 #define CRT_DISPLAY_CTRL_FORMAT_32 2
1477 #define CRT_DISPLAY_CTRL_RESERVED_BITS_MASK 0xFF000200
1479 #define CRT_FB_ADDRESS 0x080204
1480 #define CRT_FB_ADDRESS_STATUS 31:31
1481 #define CRT_FB_ADDRESS_STATUS_CURRENT 0
1482 #define CRT_FB_ADDRESS_STATUS_PENDING 1
1483 #define CRT_FB_ADDRESS_EXT 27:27
1484 #define CRT_FB_ADDRESS_EXT_LOCAL 0
1485 #define CRT_FB_ADDRESS_EXT_EXTERNAL 1
1486 #define CRT_FB_ADDRESS_ADDRESS 25:0
1488 #define CRT_FB_WIDTH 0x080208
1489 #define CRT_FB_WIDTH_WIDTH 29:16
1490 #define CRT_FB_WIDTH_OFFSET 13:0
1492 #define CRT_HORIZONTAL_TOTAL 0x08020C
1493 #define CRT_HORIZONTAL_TOTAL_TOTAL 27:16
1494 #define CRT_HORIZONTAL_TOTAL_DISPLAY_END 11:0
1496 #define CRT_HORIZONTAL_SYNC 0x080210
1497 #define CRT_HORIZONTAL_SYNC_WIDTH 23:16
1498 #define CRT_HORIZONTAL_SYNC_START 11:0
1500 #define CRT_VERTICAL_TOTAL 0x080214
1501 #define CRT_VERTICAL_TOTAL_TOTAL 26:16
1502 #define CRT_VERTICAL_TOTAL_DISPLAY_END 10:0
1504 #define CRT_VERTICAL_SYNC 0x080218
1505 #define CRT_VERTICAL_SYNC_HEIGHT 21:16
1506 #define CRT_VERTICAL_SYNC_START 10:0
1508 #define CRT_SIGNATURE_ANALYZER 0x08021C
1509 #define CRT_SIGNATURE_ANALYZER_STATUS 31:16
1510 #define CRT_SIGNATURE_ANALYZER_ENABLE 3:3
1511 #define CRT_SIGNATURE_ANALYZER_ENABLE_DISABLE 0
1512 #define CRT_SIGNATURE_ANALYZER_ENABLE_ENABLE 1
1513 #define CRT_SIGNATURE_ANALYZER_RESET 2:2
1514 #define CRT_SIGNATURE_ANALYZER_RESET_NORMAL 0
1515 #define CRT_SIGNATURE_ANALYZER_RESET_RESET 1
1516 #define CRT_SIGNATURE_ANALYZER_SOURCE 1:0
1517 #define CRT_SIGNATURE_ANALYZER_SOURCE_RED 0
1518 #define CRT_SIGNATURE_ANALYZER_SOURCE_GREEN 1
1519 #define CRT_SIGNATURE_ANALYZER_SOURCE_BLUE 2
1521 #define CRT_CURRENT_LINE 0x080220
1522 #define CRT_CURRENT_LINE_LINE 10:0
1524 #define CRT_MONITOR_DETECT 0x080224
1525 #define CRT_MONITOR_DETECT_VALUE 25:25
1526 #define CRT_MONITOR_DETECT_VALUE_DISABLE 0
1527 #define CRT_MONITOR_DETECT_VALUE_ENABLE 1
1528 #define CRT_MONITOR_DETECT_ENABLE 24:24
1529 #define CRT_MONITOR_DETECT_ENABLE_DISABLE 0
1530 #define CRT_MONITOR_DETECT_ENABLE_ENABLE 1
1531 #define CRT_MONITOR_DETECT_RED 23:16
1532 #define CRT_MONITOR_DETECT_GREEN 15:8
1533 #define CRT_MONITOR_DETECT_BLUE 7:0
1535 #define CRT_SCALE 0x080228
1536 #define CRT_SCALE_VERTICAL_MODE 31:31
1537 #define CRT_SCALE_VERTICAL_MODE_EXPAND 0
1538 #define CRT_SCALE_VERTICAL_MODE_SHRINK 1
1539 #define CRT_SCALE_VERTICAL_SCALE 27:16
1540 #define CRT_SCALE_HORIZONTAL_MODE 15:15
1541 #define CRT_SCALE_HORIZONTAL_MODE_EXPAND 0
1542 #define CRT_SCALE_HORIZONTAL_MODE_SHRINK 1
1543 #define CRT_SCALE_HORIZONTAL_SCALE 11:0
1545 /* CRT Cursor Control */
1547 #define CRT_HWC_ADDRESS 0x080230
1548 #define CRT_HWC_ADDRESS_ENABLE 31:31
1549 #define CRT_HWC_ADDRESS_ENABLE_DISABLE 0
1550 #define CRT_HWC_ADDRESS_ENABLE_ENABLE 1
1551 #define CRT_HWC_ADDRESS_EXT 27:27
1552 #define CRT_HWC_ADDRESS_EXT_LOCAL 0
1553 #define CRT_HWC_ADDRESS_EXT_EXTERNAL 1
1554 #define CRT_HWC_ADDRESS_ADDRESS 25:0
1556 #define CRT_HWC_LOCATION 0x080234
1557 #define CRT_HWC_LOCATION_TOP 27:27
1558 #define CRT_HWC_LOCATION_TOP_INSIDE 0
1559 #define CRT_HWC_LOCATION_TOP_OUTSIDE 1
1560 #define CRT_HWC_LOCATION_Y 26:16
1561 #define CRT_HWC_LOCATION_LEFT 11:11
1562 #define CRT_HWC_LOCATION_LEFT_INSIDE 0
1563 #define CRT_HWC_LOCATION_LEFT_OUTSIDE 1
1564 #define CRT_HWC_LOCATION_X 10:0
1566 #define CRT_HWC_COLOR_12 0x080238
1567 #define CRT_HWC_COLOR_12_2_RGB565 31:16
1568 #define CRT_HWC_COLOR_12_1_RGB565 15:0
1570 #define CRT_HWC_COLOR_3 0x08023C
1571 #define CRT_HWC_COLOR_3_RGB565 15:0
1573 /* This vertical expansion below start at 0x080240 ~ 0x080264 */
1574 #define CRT_VERTICAL_EXPANSION 0x080240
1575 #ifndef VALIDATION_CHIP
1576 #define CRT_VERTICAL_CENTERING_VALUE 31:24
1578 #define CRT_VERTICAL_EXPANSION_COMPARE_VALUE 23:16
1579 #define CRT_VERTICAL_EXPANSION_LINE_BUFFER 15:12
1580 #define CRT_VERTICAL_EXPANSION_SCALE_FACTOR 11:0
1582 /* This horizontal expansion below start at 0x080268 ~ 0x08027C */
1583 #define CRT_HORIZONTAL_EXPANSION 0x080268
1584 #ifndef VALIDATION_CHIP
1585 #define CRT_HORIZONTAL_CENTERING_VALUE 31:24
1587 #define CRT_HORIZONTAL_EXPANSION_COMPARE_VALUE 23:16
1588 #define CRT_HORIZONTAL_EXPANSION_SCALE_FACTOR 11:0
1590 #ifndef VALIDATION_CHIP
1591 /* Auto Centering */
1592 #define CRT_AUTO_CENTERING_TL 0x080280
1593 #define CRT_AUTO_CENTERING_TL_TOP 26:16
1594 #define CRT_AUTO_CENTERING_TL_LEFT 10:0
1596 #define CRT_AUTO_CENTERING_BR 0x080284
1597 #define CRT_AUTO_CENTERING_BR_BOTTOM 26:16
1598 #define CRT_AUTO_CENTERING_BR_RIGHT 10:0
1601 /* sm750le new register to control panel output */
1602 #define DISPLAY_CONTROL_750LE 0x80288
1605 /* Panel Palette register starts at 0x080400 ~ 0x0807FC */
1606 #define PANEL_PALETTE_RAM 0x080400
1608 /* Panel Palette register starts at 0x080C00 ~ 0x080FFC */
1609 #define CRT_PALETTE_RAM 0x080C00
1611 /* Color Space Conversion registers. */
1613 #define CSC_Y_SOURCE_BASE 0x1000C8
1614 #define CSC_Y_SOURCE_BASE_EXT 27:27
1615 #define CSC_Y_SOURCE_BASE_EXT_LOCAL 0
1616 #define CSC_Y_SOURCE_BASE_EXT_EXTERNAL 1
1617 #define CSC_Y_SOURCE_BASE_CS 26:26
1618 #define CSC_Y_SOURCE_BASE_CS_0 0
1619 #define CSC_Y_SOURCE_BASE_CS_1 1
1620 #define CSC_Y_SOURCE_BASE_ADDRESS 25:0
1622 #define CSC_CONSTANTS 0x1000CC
1623 #define CSC_CONSTANTS_Y 31:24
1624 #define CSC_CONSTANTS_R 23:16
1625 #define CSC_CONSTANTS_G 15:8
1626 #define CSC_CONSTANTS_B 7:0
1628 #define CSC_Y_SOURCE_X 0x1000D0
1629 #define CSC_Y_SOURCE_X_INTEGER 26:16
1630 #define CSC_Y_SOURCE_X_FRACTION 15:3
1632 #define CSC_Y_SOURCE_Y 0x1000D4
1633 #define CSC_Y_SOURCE_Y_INTEGER 27:16
1634 #define CSC_Y_SOURCE_Y_FRACTION 15:3
1636 #define CSC_U_SOURCE_BASE 0x1000D8
1637 #define CSC_U_SOURCE_BASE_EXT 27:27
1638 #define CSC_U_SOURCE_BASE_EXT_LOCAL 0
1639 #define CSC_U_SOURCE_BASE_EXT_EXTERNAL 1
1640 #define CSC_U_SOURCE_BASE_CS 26:26
1641 #define CSC_U_SOURCE_BASE_CS_0 0
1642 #define CSC_U_SOURCE_BASE_CS_1 1
1643 #define CSC_U_SOURCE_BASE_ADDRESS 25:0
1645 #define CSC_V_SOURCE_BASE 0x1000DC
1646 #define CSC_V_SOURCE_BASE_EXT 27:27
1647 #define CSC_V_SOURCE_BASE_EXT_LOCAL 0
1648 #define CSC_V_SOURCE_BASE_EXT_EXTERNAL 1
1649 #define CSC_V_SOURCE_BASE_CS 26:26
1650 #define CSC_V_SOURCE_BASE_CS_0 0
1651 #define CSC_V_SOURCE_BASE_CS_1 1
1652 #define CSC_V_SOURCE_BASE_ADDRESS 25:0
1654 #define CSC_SOURCE_DIMENSION 0x1000E0
1655 #define CSC_SOURCE_DIMENSION_X 31:16
1656 #define CSC_SOURCE_DIMENSION_Y 15:0
1658 #define CSC_SOURCE_PITCH 0x1000E4
1659 #define CSC_SOURCE_PITCH_Y 31:16
1660 #define CSC_SOURCE_PITCH_UV 15:0
1662 #define CSC_DESTINATION 0x1000E8
1663 #define CSC_DESTINATION_WRAP 31:31
1664 #define CSC_DESTINATION_WRAP_DISABLE 0
1665 #define CSC_DESTINATION_WRAP_ENABLE 1
1666 #define CSC_DESTINATION_X 27:16
1667 #define CSC_DESTINATION_Y 11:0
1669 #define CSC_DESTINATION_DIMENSION 0x1000EC
1670 #define CSC_DESTINATION_DIMENSION_X 31:16
1671 #define CSC_DESTINATION_DIMENSION_Y 15:0
1673 #define CSC_DESTINATION_PITCH 0x1000F0
1674 #define CSC_DESTINATION_PITCH_X 31:16
1675 #define CSC_DESTINATION_PITCH_Y 15:0
1677 #define CSC_SCALE_FACTOR 0x1000F4
1678 #define CSC_SCALE_FACTOR_HORIZONTAL 31:16
1679 #define CSC_SCALE_FACTOR_VERTICAL 15:0
1681 #define CSC_DESTINATION_BASE 0x1000F8
1682 #define CSC_DESTINATION_BASE_EXT 27:27
1683 #define CSC_DESTINATION_BASE_EXT_LOCAL 0
1684 #define CSC_DESTINATION_BASE_EXT_EXTERNAL 1
1685 #define CSC_DESTINATION_BASE_CS 26:26
1686 #define CSC_DESTINATION_BASE_CS_0 0
1687 #define CSC_DESTINATION_BASE_CS_1 1
1688 #define CSC_DESTINATION_BASE_ADDRESS 25:0
1690 #define CSC_CONTROL 0x1000FC
1691 #define CSC_CONTROL_STATUS 31:31
1692 #define CSC_CONTROL_STATUS_STOP 0
1693 #define CSC_CONTROL_STATUS_START 1
1694 #define CSC_CONTROL_SOURCE_FORMAT 30:28
1695 #define CSC_CONTROL_SOURCE_FORMAT_YUV422 0
1696 #define CSC_CONTROL_SOURCE_FORMAT_YUV420I 1
1697 #define CSC_CONTROL_SOURCE_FORMAT_YUV420 2
1698 #define CSC_CONTROL_SOURCE_FORMAT_YVU9 3
1699 #define CSC_CONTROL_SOURCE_FORMAT_IYU1 4
1700 #define CSC_CONTROL_SOURCE_FORMAT_IYU2 5
1701 #define CSC_CONTROL_SOURCE_FORMAT_RGB565 6
1702 #define CSC_CONTROL_SOURCE_FORMAT_RGB8888 7
1703 #define CSC_CONTROL_DESTINATION_FORMAT 27:26
1704 #define CSC_CONTROL_DESTINATION_FORMAT_RGB565 0
1705 #define CSC_CONTROL_DESTINATION_FORMAT_RGB8888 1
1706 #define CSC_CONTROL_HORIZONTAL_FILTER 25:25
1707 #define CSC_CONTROL_HORIZONTAL_FILTER_DISABLE 0
1708 #define CSC_CONTROL_HORIZONTAL_FILTER_ENABLE 1
1709 #define CSC_CONTROL_VERTICAL_FILTER 24:24
1710 #define CSC_CONTROL_VERTICAL_FILTER_DISABLE 0
1711 #define CSC_CONTROL_VERTICAL_FILTER_ENABLE 1
1712 #define CSC_CONTROL_BYTE_ORDER 23:23
1713 #define CSC_CONTROL_BYTE_ORDER_YUYV 0
1714 #define CSC_CONTROL_BYTE_ORDER_UYVY 1
1716 #define DE_DATA_PORT 0x110000
1718 #define I2C_BYTE_COUNT 0x010040
1719 #define I2C_BYTE_COUNT_COUNT 3:0
1721 #define I2C_CTRL 0x010041
1722 #define I2C_CTRL_INT 4:4
1723 #define I2C_CTRL_INT_DISABLE 0
1724 #define I2C_CTRL_INT_ENABLE 1
1725 #define I2C_CTRL_DIR 3:3
1726 #define I2C_CTRL_DIR_WR 0
1727 #define I2C_CTRL_DIR_RD 1
1728 #define I2C_CTRL_CTRL 2:2
1729 #define I2C_CTRL_CTRL_STOP 0
1730 #define I2C_CTRL_CTRL_START 1
1731 #define I2C_CTRL_MODE 1:1
1732 #define I2C_CTRL_MODE_STANDARD 0
1733 #define I2C_CTRL_MODE_FAST 1
1734 #define I2C_CTRL_EN 0:0
1735 #define I2C_CTRL_EN_DISABLE 0
1736 #define I2C_CTRL_EN_ENABLE 1
1738 #define I2C_STATUS 0x010042
1739 #define I2C_STATUS_TX 3:3
1740 #define I2C_STATUS_TX_PROGRESS 0
1741 #define I2C_STATUS_TX_COMPLETED 1
1742 #define I2C_TX_DONE 0x08
1743 #define I2C_STATUS_ERR 2:2
1744 #define I2C_STATUS_ERR_NORMAL 0
1745 #define I2C_STATUS_ERR_ERROR 1
1746 #define I2C_STATUS_ERR_CLEAR 0
1747 #define I2C_STATUS_ACK 1:1
1748 #define I2C_STATUS_ACK_RECEIVED 0
1749 #define I2C_STATUS_ACK_NOT 1
1750 #define I2C_STATUS_BSY 0:0
1751 #define I2C_STATUS_BSY_IDLE 0
1752 #define I2C_STATUS_BSY_BUSY 1
1754 #define I2C_RESET 0x010042
1755 #define I2C_RESET_BUS_ERROR 2:2
1756 #define I2C_RESET_BUS_ERROR_CLEAR 0
1758 #define I2C_SLAVE_ADDRESS 0x010043
1759 #define I2C_SLAVE_ADDRESS_ADDRESS 7:1
1760 #define I2C_SLAVE_ADDRESS_RW 0:0
1761 #define I2C_SLAVE_ADDRESS_RW_W 0
1762 #define I2C_SLAVE_ADDRESS_RW_R 1
1764 #define I2C_DATA0 0x010044
1765 #define I2C_DATA1 0x010045
1766 #define I2C_DATA2 0x010046
1767 #define I2C_DATA3 0x010047
1768 #define I2C_DATA4 0x010048
1769 #define I2C_DATA5 0x010049
1770 #define I2C_DATA6 0x01004A
1771 #define I2C_DATA7 0x01004B
1772 #define I2C_DATA8 0x01004C
1773 #define I2C_DATA9 0x01004D
1774 #define I2C_DATA10 0x01004E
1775 #define I2C_DATA11 0x01004F
1776 #define I2C_DATA12 0x010050
1777 #define I2C_DATA13 0x010051
1778 #define I2C_DATA14 0x010052
1779 #define I2C_DATA15 0x010053
1782 #define ZV0_CAPTURE_CTRL 0x090000
1783 #define ZV0_CAPTURE_CTRL_FIELD_INPUT 27:27
1784 #define ZV0_CAPTURE_CTRL_FIELD_INPUT_EVEN_FIELD 0
1785 #define ZV0_CAPTURE_CTRL_FIELD_INPUT_ODD_FIELD 1
1786 #define ZV0_CAPTURE_CTRL_SCAN 26:26
1787 #define ZV0_CAPTURE_CTRL_SCAN_PROGRESSIVE 0
1788 #define ZV0_CAPTURE_CTRL_SCAN_INTERLACE 1
1789 #define ZV0_CAPTURE_CTRL_CURRENT_BUFFER 25:25
1790 #define ZV0_CAPTURE_CTRL_CURRENT_BUFFER_0 0
1791 #define ZV0_CAPTURE_CTRL_CURRENT_BUFFER_1 1
1792 #define ZV0_CAPTURE_CTRL_VERTICAL_SYNC 24:24
1793 #define ZV0_CAPTURE_CTRL_VERTICAL_SYNC_INACTIVE 0
1794 #define ZV0_CAPTURE_CTRL_VERTICAL_SYNC_ACTIVE 1
1795 #define ZV0_CAPTURE_CTRL_ADJ 19:19
1796 #define ZV0_CAPTURE_CTRL_ADJ_NORMAL 0
1797 #define ZV0_CAPTURE_CTRL_ADJ_DELAY 1
1798 #define ZV0_CAPTURE_CTRL_HA 18:18
1799 #define ZV0_CAPTURE_CTRL_HA_DISABLE 0
1800 #define ZV0_CAPTURE_CTRL_HA_ENABLE 1
1801 #define ZV0_CAPTURE_CTRL_VSK 17:17
1802 #define ZV0_CAPTURE_CTRL_VSK_DISABLE 0
1803 #define ZV0_CAPTURE_CTRL_VSK_ENABLE 1
1804 #define ZV0_CAPTURE_CTRL_HSK 16:16
1805 #define ZV0_CAPTURE_CTRL_HSK_DISABLE 0
1806 #define ZV0_CAPTURE_CTRL_HSK_ENABLE 1
1807 #define ZV0_CAPTURE_CTRL_FD 15:15
1808 #define ZV0_CAPTURE_CTRL_FD_RISING 0
1809 #define ZV0_CAPTURE_CTRL_FD_FALLING 1
1810 #define ZV0_CAPTURE_CTRL_VP 14:14
1811 #define ZV0_CAPTURE_CTRL_VP_HIGH 0
1812 #define ZV0_CAPTURE_CTRL_VP_LOW 1
1813 #define ZV0_CAPTURE_CTRL_HP 13:13
1814 #define ZV0_CAPTURE_CTRL_HP_HIGH 0
1815 #define ZV0_CAPTURE_CTRL_HP_LOW 1
1816 #define ZV0_CAPTURE_CTRL_CP 12:12
1817 #define ZV0_CAPTURE_CTRL_CP_HIGH 0
1818 #define ZV0_CAPTURE_CTRL_CP_LOW 1
1819 #define ZV0_CAPTURE_CTRL_UVS 11:11
1820 #define ZV0_CAPTURE_CTRL_UVS_DISABLE 0
1821 #define ZV0_CAPTURE_CTRL_UVS_ENABLE 1
1822 #define ZV0_CAPTURE_CTRL_BS 10:10
1823 #define ZV0_CAPTURE_CTRL_BS_DISABLE 0
1824 #define ZV0_CAPTURE_CTRL_BS_ENABLE 1
1825 #define ZV0_CAPTURE_CTRL_CS 9:9
1826 #define ZV0_CAPTURE_CTRL_CS_16 0
1827 #define ZV0_CAPTURE_CTRL_CS_8 1
1828 #define ZV0_CAPTURE_CTRL_CF 8:8
1829 #define ZV0_CAPTURE_CTRL_CF_YUV 0
1830 #define ZV0_CAPTURE_CTRL_CF_RGB 1
1831 #define ZV0_CAPTURE_CTRL_FS 7:7
1832 #define ZV0_CAPTURE_CTRL_FS_DISABLE 0
1833 #define ZV0_CAPTURE_CTRL_FS_ENABLE 1
1834 #define ZV0_CAPTURE_CTRL_WEAVE 6:6
1835 #define ZV0_CAPTURE_CTRL_WEAVE_DISABLE 0
1836 #define ZV0_CAPTURE_CTRL_WEAVE_ENABLE 1
1837 #define ZV0_CAPTURE_CTRL_BOB 5:5
1838 #define ZV0_CAPTURE_CTRL_BOB_DISABLE 0
1839 #define ZV0_CAPTURE_CTRL_BOB_ENABLE 1
1840 #define ZV0_CAPTURE_CTRL_DB 4:4
1841 #define ZV0_CAPTURE_CTRL_DB_DISABLE 0
1842 #define ZV0_CAPTURE_CTRL_DB_ENABLE 1
1843 #define ZV0_CAPTURE_CTRL_CC 3:3
1844 #define ZV0_CAPTURE_CTRL_CC_CONTINUE 0
1845 #define ZV0_CAPTURE_CTRL_CC_CONDITION 1
1846 #define ZV0_CAPTURE_CTRL_RGB 2:2
1847 #define ZV0_CAPTURE_CTRL_RGB_DISABLE 0
1848 #define ZV0_CAPTURE_CTRL_RGB_ENABLE 1
1849 #define ZV0_CAPTURE_CTRL_656 1:1
1850 #define ZV0_CAPTURE_CTRL_656_DISABLE 0
1851 #define ZV0_CAPTURE_CTRL_656_ENABLE 1
1852 #define ZV0_CAPTURE_CTRL_CAP 0:0
1853 #define ZV0_CAPTURE_CTRL_CAP_DISABLE 0
1854 #define ZV0_CAPTURE_CTRL_CAP_ENABLE 1
1856 #define ZV0_CAPTURE_CLIP 0x090004
1857 #define ZV0_CAPTURE_CLIP_YCLIP_EVEN_FIELD 25:16
1858 #define ZV0_CAPTURE_CLIP_YCLIP 25:16
1859 #define ZV0_CAPTURE_CLIP_XCLIP 9:0
1861 #define ZV0_CAPTURE_SIZE 0x090008
1862 #define ZV0_CAPTURE_SIZE_HEIGHT 26:16
1863 #define ZV0_CAPTURE_SIZE_WIDTH 10:0
1865 #define ZV0_CAPTURE_BUF0_ADDRESS 0x09000C
1866 #define ZV0_CAPTURE_BUF0_ADDRESS_STATUS 31:31
1867 #define ZV0_CAPTURE_BUF0_ADDRESS_STATUS_CURRENT 0
1868 #define ZV0_CAPTURE_BUF0_ADDRESS_STATUS_PENDING 1
1869 #define ZV0_CAPTURE_BUF0_ADDRESS_EXT 27:27
1870 #define ZV0_CAPTURE_BUF0_ADDRESS_EXT_LOCAL 0
1871 #define ZV0_CAPTURE_BUF0_ADDRESS_EXT_EXTERNAL 1
1872 #define ZV0_CAPTURE_BUF0_ADDRESS_CS 26:26
1873 #define ZV0_CAPTURE_BUF0_ADDRESS_CS_0 0
1874 #define ZV0_CAPTURE_BUF0_ADDRESS_CS_1 1
1875 #define ZV0_CAPTURE_BUF0_ADDRESS_ADDRESS 25:0
1877 #define ZV0_CAPTURE_BUF1_ADDRESS 0x090010
1878 #define ZV0_CAPTURE_BUF1_ADDRESS_STATUS 31:31
1879 #define ZV0_CAPTURE_BUF1_ADDRESS_STATUS_CURRENT 0
1880 #define ZV0_CAPTURE_BUF1_ADDRESS_STATUS_PENDING 1
1881 #define ZV0_CAPTURE_BUF1_ADDRESS_EXT 27:27
1882 #define ZV0_CAPTURE_BUF1_ADDRESS_EXT_LOCAL 0
1883 #define ZV0_CAPTURE_BUF1_ADDRESS_EXT_EXTERNAL 1
1884 #define ZV0_CAPTURE_BUF1_ADDRESS_CS 26:26
1885 #define ZV0_CAPTURE_BUF1_ADDRESS_CS_0 0
1886 #define ZV0_CAPTURE_BUF1_ADDRESS_CS_1 1
1887 #define ZV0_CAPTURE_BUF1_ADDRESS_ADDRESS 25:0
1889 #define ZV0_CAPTURE_BUF_OFFSET 0x090014
1890 #ifndef VALIDATION_CHIP
1891 #define ZV0_CAPTURE_BUF_OFFSET_YCLIP_ODD_FIELD 25:16
1893 #define ZV0_CAPTURE_BUF_OFFSET_OFFSET 15:0
1895 #define ZV0_CAPTURE_FIFO_CTRL 0x090018
1896 #define ZV0_CAPTURE_FIFO_CTRL_FIFO 2:0
1897 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_0 0
1898 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_1 1
1899 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_2 2
1900 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_3 3
1901 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_4 4
1902 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_5 5
1903 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_6 6
1904 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_7 7
1906 #define ZV0_CAPTURE_YRGB_CONST 0x09001C
1907 #define ZV0_CAPTURE_YRGB_CONST_Y 31:24
1908 #define ZV0_CAPTURE_YRGB_CONST_R 23:16
1909 #define ZV0_CAPTURE_YRGB_CONST_G 15:8
1910 #define ZV0_CAPTURE_YRGB_CONST_B 7:0
1912 #define ZV0_CAPTURE_LINE_COMP 0x090020
1913 #define ZV0_CAPTURE_LINE_COMP_LC 10:0
1917 #define ZV1_CAPTURE_CTRL 0x098000
1918 #define ZV1_CAPTURE_CTRL_FIELD_INPUT 27:27
1919 #define ZV1_CAPTURE_CTRL_FIELD_INPUT_EVEN_FIELD 0
1920 #define ZV1_CAPTURE_CTRL_FIELD_INPUT_ODD_FIELD 0
1921 #define ZV1_CAPTURE_CTRL_SCAN 26:26
1922 #define ZV1_CAPTURE_CTRL_SCAN_PROGRESSIVE 0
1923 #define ZV1_CAPTURE_CTRL_SCAN_INTERLACE 1
1924 #define ZV1_CAPTURE_CTRL_CURRENT_BUFFER 25:25
1925 #define ZV1_CAPTURE_CTRL_CURRENT_BUFFER_0 0
1926 #define ZV1_CAPTURE_CTRL_CURRENT_BUFFER_1 1
1927 #define ZV1_CAPTURE_CTRL_VERTICAL_SYNC 24:24
1928 #define ZV1_CAPTURE_CTRL_VERTICAL_SYNC_INACTIVE 0
1929 #define ZV1_CAPTURE_CTRL_VERTICAL_SYNC_ACTIVE 1
1930 #define ZV1_CAPTURE_CTRL_PANEL 20:20
1931 #define ZV1_CAPTURE_CTRL_PANEL_DISABLE 0
1932 #define ZV1_CAPTURE_CTRL_PANEL_ENABLE 1
1933 #define ZV1_CAPTURE_CTRL_ADJ 19:19
1934 #define ZV1_CAPTURE_CTRL_ADJ_NORMAL 0
1935 #define ZV1_CAPTURE_CTRL_ADJ_DELAY 1
1936 #define ZV1_CAPTURE_CTRL_HA 18:18
1937 #define ZV1_CAPTURE_CTRL_HA_DISABLE 0
1938 #define ZV1_CAPTURE_CTRL_HA_ENABLE 1
1939 #define ZV1_CAPTURE_CTRL_VSK 17:17
1940 #define ZV1_CAPTURE_CTRL_VSK_DISABLE 0
1941 #define ZV1_CAPTURE_CTRL_VSK_ENABLE 1
1942 #define ZV1_CAPTURE_CTRL_HSK 16:16
1943 #define ZV1_CAPTURE_CTRL_HSK_DISABLE 0
1944 #define ZV1_CAPTURE_CTRL_HSK_ENABLE 1
1945 #define ZV1_CAPTURE_CTRL_FD 15:15
1946 #define ZV1_CAPTURE_CTRL_FD_RISING 0
1947 #define ZV1_CAPTURE_CTRL_FD_FALLING 1
1948 #define ZV1_CAPTURE_CTRL_VP 14:14
1949 #define ZV1_CAPTURE_CTRL_VP_HIGH 0
1950 #define ZV1_CAPTURE_CTRL_VP_LOW 1
1951 #define ZV1_CAPTURE_CTRL_HP 13:13
1952 #define ZV1_CAPTURE_CTRL_HP_HIGH 0
1953 #define ZV1_CAPTURE_CTRL_HP_LOW 1
1954 #define ZV1_CAPTURE_CTRL_CP 12:12
1955 #define ZV1_CAPTURE_CTRL_CP_HIGH 0
1956 #define ZV1_CAPTURE_CTRL_CP_LOW 1
1957 #define ZV1_CAPTURE_CTRL_UVS 11:11
1958 #define ZV1_CAPTURE_CTRL_UVS_DISABLE 0
1959 #define ZV1_CAPTURE_CTRL_UVS_ENABLE 1
1960 #define ZV1_CAPTURE_CTRL_BS 10:10
1961 #define ZV1_CAPTURE_CTRL_BS_DISABLE 0
1962 #define ZV1_CAPTURE_CTRL_BS_ENABLE 1
1963 #define ZV1_CAPTURE_CTRL_CS 9:9
1964 #define ZV1_CAPTURE_CTRL_CS_16 0
1965 #define ZV1_CAPTURE_CTRL_CS_8 1
1966 #define ZV1_CAPTURE_CTRL_CF 8:8
1967 #define ZV1_CAPTURE_CTRL_CF_YUV 0
1968 #define ZV1_CAPTURE_CTRL_CF_RGB 1
1969 #define ZV1_CAPTURE_CTRL_FS 7:7
1970 #define ZV1_CAPTURE_CTRL_FS_DISABLE 0
1971 #define ZV1_CAPTURE_CTRL_FS_ENABLE 1
1972 #define ZV1_CAPTURE_CTRL_WEAVE 6:6
1973 #define ZV1_CAPTURE_CTRL_WEAVE_DISABLE 0
1974 #define ZV1_CAPTURE_CTRL_WEAVE_ENABLE 1
1975 #define ZV1_CAPTURE_CTRL_BOB 5:5
1976 #define ZV1_CAPTURE_CTRL_BOB_DISABLE 0
1977 #define ZV1_CAPTURE_CTRL_BOB_ENABLE 1
1978 #define ZV1_CAPTURE_CTRL_DB 4:4
1979 #define ZV1_CAPTURE_CTRL_DB_DISABLE 0
1980 #define ZV1_CAPTURE_CTRL_DB_ENABLE 1
1981 #define ZV1_CAPTURE_CTRL_CC 3:3
1982 #define ZV1_CAPTURE_CTRL_CC_CONTINUE 0
1983 #define ZV1_CAPTURE_CTRL_CC_CONDITION 1
1984 #define ZV1_CAPTURE_CTRL_RGB 2:2
1985 #define ZV1_CAPTURE_CTRL_RGB_DISABLE 0
1986 #define ZV1_CAPTURE_CTRL_RGB_ENABLE 1
1987 #define ZV1_CAPTURE_CTRL_656 1:1
1988 #define ZV1_CAPTURE_CTRL_656_DISABLE 0
1989 #define ZV1_CAPTURE_CTRL_656_ENABLE 1
1990 #define ZV1_CAPTURE_CTRL_CAP 0:0
1991 #define ZV1_CAPTURE_CTRL_CAP_DISABLE 0
1992 #define ZV1_CAPTURE_CTRL_CAP_ENABLE 1
1994 #define ZV1_CAPTURE_CLIP 0x098004
1995 #define ZV1_CAPTURE_CLIP_YCLIP 25:16
1996 #define ZV1_CAPTURE_CLIP_XCLIP 9:0
1998 #define ZV1_CAPTURE_SIZE 0x098008
1999 #define ZV1_CAPTURE_SIZE_HEIGHT 26:16
2000 #define ZV1_CAPTURE_SIZE_WIDTH 10:0
2002 #define ZV1_CAPTURE_BUF0_ADDRESS 0x09800C
2003 #define ZV1_CAPTURE_BUF0_ADDRESS_STATUS 31:31
2004 #define ZV1_CAPTURE_BUF0_ADDRESS_STATUS_CURRENT 0
2005 #define ZV1_CAPTURE_BUF0_ADDRESS_STATUS_PENDING 1
2006 #define ZV1_CAPTURE_BUF0_ADDRESS_EXT 27:27
2007 #define ZV1_CAPTURE_BUF0_ADDRESS_EXT_LOCAL 0
2008 #define ZV1_CAPTURE_BUF0_ADDRESS_EXT_EXTERNAL 1
2009 #define ZV1_CAPTURE_BUF0_ADDRESS_CS 26:26
2010 #define ZV1_CAPTURE_BUF0_ADDRESS_CS_0 0
2011 #define ZV1_CAPTURE_BUF0_ADDRESS_CS_1 1
2012 #define ZV1_CAPTURE_BUF0_ADDRESS_ADDRESS 25:0
2014 #define ZV1_CAPTURE_BUF1_ADDRESS 0x098010
2015 #define ZV1_CAPTURE_BUF1_ADDRESS_STATUS 31:31
2016 #define ZV1_CAPTURE_BUF1_ADDRESS_STATUS_CURRENT 0
2017 #define ZV1_CAPTURE_BUF1_ADDRESS_STATUS_PENDING 1
2018 #define ZV1_CAPTURE_BUF1_ADDRESS_EXT 27:27
2019 #define ZV1_CAPTURE_BUF1_ADDRESS_EXT_LOCAL 0
2020 #define ZV1_CAPTURE_BUF1_ADDRESS_EXT_EXTERNAL 1
2021 #define ZV1_CAPTURE_BUF1_ADDRESS_CS 26:26
2022 #define ZV1_CAPTURE_BUF1_ADDRESS_CS_0 0
2023 #define ZV1_CAPTURE_BUF1_ADDRESS_CS_1 1
2024 #define ZV1_CAPTURE_BUF1_ADDRESS_ADDRESS 25:0
2026 #define ZV1_CAPTURE_BUF_OFFSET 0x098014
2027 #define ZV1_CAPTURE_BUF_OFFSET_OFFSET 15:0
2029 #define ZV1_CAPTURE_FIFO_CTRL 0x098018
2030 #define ZV1_CAPTURE_FIFO_CTRL_FIFO 2:0
2031 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_0 0
2032 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_1 1
2033 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_2 2
2034 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_3 3
2035 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_4 4
2036 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_5 5
2037 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_6 6
2038 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_7 7
2040 #define ZV1_CAPTURE_YRGB_CONST 0x09801C
2041 #define ZV1_CAPTURE_YRGB_CONST_Y 31:24
2042 #define ZV1_CAPTURE_YRGB_CONST_R 23:16
2043 #define ZV1_CAPTURE_YRGB_CONST_G 15:8
2044 #define ZV1_CAPTURE_YRGB_CONST_B 7:0
2046 #define DMA_1_SOURCE 0x0D0010
2047 #define DMA_1_SOURCE_ADDRESS_EXT 27:27
2048 #define DMA_1_SOURCE_ADDRESS_EXT_LOCAL 0
2049 #define DMA_1_SOURCE_ADDRESS_EXT_EXTERNAL 1
2050 #define DMA_1_SOURCE_ADDRESS_CS 26:26
2051 #define DMA_1_SOURCE_ADDRESS_CS_0 0
2052 #define DMA_1_SOURCE_ADDRESS_CS_1 1
2053 #define DMA_1_SOURCE_ADDRESS 25:0
2055 #define DMA_1_DESTINATION 0x0D0014
2056 #define DMA_1_DESTINATION_ADDRESS_EXT 27:27
2057 #define DMA_1_DESTINATION_ADDRESS_EXT_LOCAL 0
2058 #define DMA_1_DESTINATION_ADDRESS_EXT_EXTERNAL 1
2059 #define DMA_1_DESTINATION_ADDRESS_CS 26:26
2060 #define DMA_1_DESTINATION_ADDRESS_CS_0 0
2061 #define DMA_1_DESTINATION_ADDRESS_CS_1 1
2062 #define DMA_1_DESTINATION_ADDRESS 25:0
2064 #define DMA_1_SIZE_CONTROL 0x0D0018
2065 #define DMA_1_SIZE_CONTROL_STATUS 31:31
2066 #define DMA_1_SIZE_CONTROL_STATUS_IDLE 0
2067 #define DMA_1_SIZE_CONTROL_STATUS_ACTIVE 1
2068 #define DMA_1_SIZE_CONTROL_SIZE 23:0
2070 #define DMA_ABORT_INTERRUPT 0x0D0020
2071 #define DMA_ABORT_INTERRUPT_ABORT_1 5:5
2072 #define DMA_ABORT_INTERRUPT_ABORT_1_ENABLE 0
2073 #define DMA_ABORT_INTERRUPT_ABORT_1_ABORT 1
2074 #define DMA_ABORT_INTERRUPT_ABORT_0 4:4
2075 #define DMA_ABORT_INTERRUPT_ABORT_0_ENABLE 0
2076 #define DMA_ABORT_INTERRUPT_ABORT_0_ABORT 1
2077 #define DMA_ABORT_INTERRUPT_INT_1 1:1
2078 #define DMA_ABORT_INTERRUPT_INT_1_CLEAR 0
2079 #define DMA_ABORT_INTERRUPT_INT_1_FINISHED 1
2080 #define DMA_ABORT_INTERRUPT_INT_0 0:0
2081 #define DMA_ABORT_INTERRUPT_INT_0_CLEAR 0
2082 #define DMA_ABORT_INTERRUPT_INT_0_FINISHED 1
2088 /* Default i2c CLK and Data GPIO. These are the default i2c pins */
2089 #define DEFAULT_I2C_SCL 30
2090 #define DEFAULT_I2C_SDA 31
2093 #define GPIO_DATA_SM750LE 0x020018
2094 #define GPIO_DATA_SM750LE_1 1:1
2095 #define GPIO_DATA_SM750LE_0 0:0
2097 #define GPIO_DATA_DIRECTION_SM750LE 0x02001C
2098 #define GPIO_DATA_DIRECTION_SM750LE_1 1:1
2099 #define GPIO_DATA_DIRECTION_SM750LE_1_INPUT 0
2100 #define GPIO_DATA_DIRECTION_SM750LE_1_OUTPUT 1
2101 #define GPIO_DATA_DIRECTION_SM750LE_0 0:0
2102 #define GPIO_DATA_DIRECTION_SM750LE_0_INPUT 0
2103 #define GPIO_DATA_DIRECTION_SM750LE_0_OUTPUT 1