drivers/usb/dwc3/dwc3-omap.c

   1 /**
   2  * dwc3-omap.c - OMAP Specific Glue layer
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/platform_data/dwc3-omap.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/ioport.h>
  29 #include <linux/io.h>
  30 #include <linux/of.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/extcon.h>
  33 #include <linux/extcon/of_extcon.h>
  34 #include <linux/regulator/consumer.h>
  35
  36 #include <linux/usb/otg.h>
  37
  38 /*
  39  * All these registers belong to OMAP's Wrapper around the
  40  * DesignWare USB3 Core.
  41  */
  42
  43 #define USBOTGSS_REVISION                       0x0000
  44 #define USBOTGSS_SYSCONFIG                      0x0010
  45 #define USBOTGSS_IRQ_EOI                        0x0020
  46 #define USBOTGSS_EOI_OFFSET                     0x0008
  47 #define USBOTGSS_IRQSTATUS_RAW_0                0x0024
  48 #define USBOTGSS_IRQSTATUS_0                    0x0028
  49 #define USBOTGSS_IRQENABLE_SET_0                0x002c
  50 #define USBOTGSS_IRQENABLE_CLR_0                0x0030
  51 #define USBOTGSS_IRQ0_OFFSET                    0x0004
  52 #define USBOTGSS_IRQSTATUS_RAW_1                0x0030
  53 #define USBOTGSS_IRQSTATUS_1                    0x0034
  54 #define USBOTGSS_IRQENABLE_SET_1                0x0038
  55 #define USBOTGSS_IRQENABLE_CLR_1                0x003c
  56 #define USBOTGSS_IRQSTATUS_RAW_2                0x0040
  57 #define USBOTGSS_IRQSTATUS_2                    0x0044
  58 #define USBOTGSS_IRQENABLE_SET_2                0x0048
  59 #define USBOTGSS_IRQENABLE_CLR_2                0x004c
  60 #define USBOTGSS_IRQSTATUS_RAW_3                0x0050
  61 #define USBOTGSS_IRQSTATUS_3                    0x0054
  62 #define USBOTGSS_IRQENABLE_SET_3                0x0058
  63 #define USBOTGSS_IRQENABLE_CLR_3                0x005c
  64 #define USBOTGSS_IRQSTATUS_EOI_MISC             0x0030
  65 #define USBOTGSS_IRQSTATUS_RAW_MISC             0x0034
  66 #define USBOTGSS_IRQSTATUS_MISC                 0x0038
  67 #define USBOTGSS_IRQENABLE_SET_MISC             0x003c
  68 #define USBOTGSS_IRQENABLE_CLR_MISC             0x0040
  69 #define USBOTGSS_IRQMISC_OFFSET                 0x03fc
  70 #define USBOTGSS_UTMI_OTG_CTRL                  0x0080
  71 #define USBOTGSS_UTMI_OTG_STATUS                0x0084
  72 #define USBOTGSS_UTMI_OTG_OFFSET                0x0480
  73 #define USBOTGSS_TXFIFO_DEPTH                   0x0508
  74 #define USBOTGSS_RXFIFO_DEPTH                   0x050c
  75 #define USBOTGSS_MMRAM_OFFSET                   0x0100
  76 #define USBOTGSS_FLADJ                          0x0104
  77 #define USBOTGSS_DEBUG_CFG                      0x0108
  78 #define USBOTGSS_DEBUG_DATA                     0x010c
  79 #define USBOTGSS_DEV_EBC_EN                     0x0110
  80 #define USBOTGSS_DEBUG_OFFSET                   0x0600
  81
  82 /* REVISION REGISTER */
  83 #define USBOTGSS_REVISION_XMAJOR(reg)           ((reg >> 8) & 0x7)
  84 #define USBOTGSS_REVISION_XMAJOR1               1
  85 #define USBOTGSS_REVISION_XMAJOR2               2
  86 /* SYSCONFIG REGISTER */
  87 #define USBOTGSS_SYSCONFIG_DMADISABLE           (1 << 16)
  88
  89 /* IRQ_EOI REGISTER */
  90 #define USBOTGSS_IRQ_EOI_LINE_NUMBER            (1 << 0)
  91
  92 /* IRQS0 BITS */
  93 #define USBOTGSS_IRQO_COREIRQ_ST                (1 << 0)
  94
  95 /* IRQMISC BITS */
  96 #define USBOTGSS_IRQMISC_DMADISABLECLR          (1 << 17)
  97 #define USBOTGSS_IRQMISC_OEVT                   (1 << 16)
  98 #define USBOTGSS_IRQMISC_DRVVBUS_RISE           (1 << 13)
  99 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE          (1 << 12)
 100 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE       (1 << 11)
 101 #define USBOTGSS_IRQMISC_IDPULLUP_RISE          (1 << 8)
 102 #define USBOTGSS_IRQMISC_DRVVBUS_FALL           (1 << 5)
 103 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL          (1 << 4)
 104 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL               (1 << 3)
 105 #define USBOTGSS_IRQMISC_IDPULLUP_FALL          (1 << 0)
 106
 107 /* UTMI_OTG_CTRL REGISTER */
 108 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS          (1 << 5)
 109 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS         (1 << 4)
 110 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS      (1 << 3)
 111 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP         (1 << 0)
 112
 113 /* UTMI_OTG_STATUS REGISTER */
 114 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE        (1 << 31)
 115 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT   (1 << 9)
 116 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
 117 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG          (1 << 4)
 118 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND        (1 << 3)
 119 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID      (1 << 2)
 120 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID      (1 << 1)
 121
 122 struct dwc3_omap {
 123         /* device lock */
 124         spinlock_t              lock;
 125
 126         struct device           *dev;
 127
 128         int                     irq;
 129         void __iomem            *base;
 130
 131         u32                     utmi_otg_status;
 132         u32                     utmi_otg_offset;
 133         u32                     irqmisc_offset;
 134         u32                     irq_eoi_offset;
 135         u32                     debug_offset;
 136         u32                     irq0_offset;
 137         u32                     revision;
 138
 139         u32                     dma_status:1;
 140
 141         struct extcon_specific_cable_nb extcon_vbus_dev;
 142         struct extcon_specific_cable_nb extcon_id_dev;
 143         struct notifier_block   vbus_nb;
 144         struct notifier_block   id_nb;
 145
 146         struct regulator        *vbus_reg;
 147 };
 148
 149 enum omap_dwc3_vbus_id_status {
 150         OMAP_DWC3_ID_FLOAT,
 151         OMAP_DWC3_ID_GROUND,
 152         OMAP_DWC3_VBUS_OFF,
 153         OMAP_DWC3_VBUS_VALID,
 154 };
 155
 156 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
 157 {
 158         return readl(base + offset);
 159 }
 160
 161 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
 162 {
 163         writel(value, base + offset);
 164 }
 165
 166 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
 167 {
 168         return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
 169                                                         omap->utmi_otg_offset);
 170 }
 171
 172 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
 173 {
 174         dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
 175                                         omap->utmi_otg_offset, value);
 176
 177 }
 178
 179 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
 180 {
 181         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
 182                                                 omap->irq0_offset);
 183 }
 184
 185 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
 186 {
 187         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
 188                                                 omap->irq0_offset, value);
 189
 190 }
 191
 192 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
 193 {
 194         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
 195                                                 omap->irqmisc_offset);
 196 }
 197
 198 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
 199 {
 200         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
 201                                         omap->irqmisc_offset, value);
 202
 203 }
 204
 205 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
 206 {
 207         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
 208                                                 omap->irqmisc_offset, value);
 209
 210 }
 211
 212 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
 213 {
 214         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
 215                                                 omap->irq0_offset, value);
 216 }
 217
 218 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
 219         enum omap_dwc3_vbus_id_status status)
 220 {
 221         int     ret;
 222         u32     val;
 223
 224         switch (status) {
 225         case OMAP_DWC3_ID_GROUND:
 226                 dev_dbg(omap->dev, "ID GND\n");
 227
 228                 if (omap->vbus_reg) {
 229                         ret = regulator_enable(omap->vbus_reg);
 230                         if (ret) {
 231                                 dev_dbg(omap->dev, "regulator enable failed\n");
 232                                 return;
 233                         }
 234                 }
 235
 236                 val = dwc3_omap_read_utmi_status(omap);
 237                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
 238                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 239                                 | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
 240                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 241                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
 242                 dwc3_omap_write_utmi_status(omap, val);
 243                 break;
 244
 245         case OMAP_DWC3_VBUS_VALID:
 246                 dev_dbg(omap->dev, "VBUS Connect\n");
 247
 248                 val = dwc3_omap_read_utmi_status(omap);
 249                 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
 250                 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
 251                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 252                                 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 253                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
 254                 dwc3_omap_write_utmi_status(omap, val);
 255                 break;
 256
 257         case OMAP_DWC3_ID_FLOAT:
 258                 if (omap->vbus_reg)
 259                         regulator_disable(omap->vbus_reg);
 260
 261         case OMAP_DWC3_VBUS_OFF:
 262                 dev_dbg(omap->dev, "VBUS Disconnect\n");
 263
 264                 val = dwc3_omap_read_utmi_status(omap);
 265                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 266                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 267                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
 268                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
 269                                 | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
 270                 dwc3_omap_write_utmi_status(omap, val);
 271                 break;
 272
 273         default:
 274                 dev_dbg(omap->dev, "invalid state\n");
 275         }
 276 }
 277
 278 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
 279 {
 280         struct dwc3_omap        *omap = _omap;
 281         u32                     reg;
 282
 283         spin_lock(&omap->lock);
 284
 285         reg = dwc3_omap_read_irqmisc_status(omap);
 286
 287         if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
 288                 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
 289                 omap->dma_status = false;
 290         }
 291
 292         if (reg & USBOTGSS_IRQMISC_OEVT)
 293                 dev_dbg(omap->dev, "OTG Event\n");
 294
 295         if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
 296                 dev_dbg(omap->dev, "DRVVBUS Rise\n");
 297
 298         if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
 299                 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
 300
 301         if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
 302                 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
 303
 304         if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
 305                 dev_dbg(omap->dev, "IDPULLUP Rise\n");
 306
 307         if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
 308                 dev_dbg(omap->dev, "DRVVBUS Fall\n");
 309
 310         if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
 311                 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
 312
 313         if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
 314                 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
 315
 316         if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
 317                 dev_dbg(omap->dev, "IDPULLUP Fall\n");
 318
 319         dwc3_omap_write_irqmisc_status(omap, reg);
 320
 321         reg = dwc3_omap_read_irq0_status(omap);
 322
 323         dwc3_omap_write_irq0_status(omap, reg);
 324
 325         spin_unlock(&omap->lock);
 326
 327         return IRQ_HANDLED;
 328 }
 329
 330 static int dwc3_omap_remove_core(struct device *dev, void *c)
 331 {
 332         struct platform_device *pdev = to_platform_device(dev);
 333
 334         platform_device_unregister(pdev);
 335
 336         return 0;
 337 }
 338
 339 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
 340 {
 341         u32                     reg;
 342
 343         /* enable all IRQs */
 344         reg = USBOTGSS_IRQO_COREIRQ_ST;
 345         dwc3_omap_write_irq0_set(omap, reg);
 346
 347         reg = (USBOTGSS_IRQMISC_OEVT |
 348                         USBOTGSS_IRQMISC_DRVVBUS_RISE |
 349                         USBOTGSS_IRQMISC_CHRGVBUS_RISE |
 350                         USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
 351                         USBOTGSS_IRQMISC_IDPULLUP_RISE |
 352                         USBOTGSS_IRQMISC_DRVVBUS_FALL |
 353                         USBOTGSS_IRQMISC_CHRGVBUS_FALL |
 354                         USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
 355                         USBOTGSS_IRQMISC_IDPULLUP_FALL);
 356
 357         dwc3_omap_write_irqmisc_set(omap, reg);
 358 }
 359
 360 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
 361 {
 362         /* disable all IRQs */
 363         dwc3_omap_write_irqmisc_set(omap, 0x00);
 364         dwc3_omap_write_irq0_set(omap, 0x00);
 365 }
 366
 367 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
 368
 369 static int dwc3_omap_id_notifier(struct notifier_block *nb,
 370         unsigned long event, void *ptr)
 371 {
 372         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
 373
 374         if (event)
 375                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
 376         else
 377                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
 378
 379         return NOTIFY_DONE;
 380 }
 381
 382 static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
 383         unsigned long event, void *ptr)
 384 {
 385         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
 386
 387         if (event)
 388                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
 389         else
 390                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
 391
 392         return NOTIFY_DONE;
 393 }
 394
 395 static int dwc3_omap_probe(struct platform_device *pdev)
 396 {
 397         struct device_node      *node = pdev->dev.of_node;
 398
 399         struct dwc3_omap        *omap;
 400         struct resource         *res;
 401         struct device           *dev = &pdev->dev;
 402         struct extcon_dev       *edev;
 403         struct regulator        *vbus_reg = NULL;
 404
 405         int                     ret = -ENOMEM;
 406         int                     irq;
 407
 408         int                     utmi_mode = 0;
 409         int                     x_major;
 410
 411         u32                     reg;
 412
 413         void __iomem            *base;
 414
 415         if (!node) {
 416                 dev_err(dev, "device node not found\n");
 417                 return -EINVAL;
 418         }
 419
 420         omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
 421         if (!omap) {
 422                 dev_err(dev, "not enough memory\n");
 423                 return -ENOMEM;
 424         }
 425
 426         platform_set_drvdata(pdev, omap);
 427
 428         irq = platform_get_irq(pdev, 0);
 429         if (irq < 0) {
 430                 dev_err(dev, "missing IRQ resource\n");
 431                 return -EINVAL;
 432         }
 433
 434         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 435         if (!res) {
 436                 dev_err(dev, "missing memory base resource\n");
 437                 return -EINVAL;
 438         }
 439
 440         base = devm_ioremap_resource(dev, res);
 441         if (IS_ERR(base))
 442                 return PTR_ERR(base);
 443
 444         if (of_property_read_bool(node, "vbus-supply")) {
 445                 vbus_reg = devm_regulator_get(dev, "vbus");
 446                 if (IS_ERR(vbus_reg)) {
 447                         dev_err(dev, "vbus init failed\n");
 448                         return PTR_ERR(vbus_reg);
 449                 }
 450         }
 451
 452         spin_lock_init(&omap->lock);
 453
 454         omap->dev       = dev;
 455         omap->irq       = irq;
 456         omap->base      = base;
 457         omap->vbus_reg  = vbus_reg;
 458         dev->dma_mask   = &dwc3_omap_dma_mask;
 459
 460         pm_runtime_enable(dev);
 461         ret = pm_runtime_get_sync(dev);
 462         if (ret < 0) {
 463                 dev_err(dev, "get_sync failed with err %d\n", ret);
 464                 goto err0;
 465         }
 466
 467         reg = dwc3_omap_readl(omap->base, USBOTGSS_REVISION);
 468         omap->revision = reg;
 469         x_major = USBOTGSS_REVISION_XMAJOR(reg);
 470
 471         /* Differentiate between OMAP5 and AM437x */
 472         switch (x_major) {
 473         case USBOTGSS_REVISION_XMAJOR1:
 474         case USBOTGSS_REVISION_XMAJOR2:
 475                 omap->irq_eoi_offset = 0;
 476                 omap->irq0_offset = 0;
 477                 omap->irqmisc_offset = 0;
 478                 omap->utmi_otg_offset = 0;
 479                 omap->debug_offset = 0;
 480                 break;
 481         default:
 482                 /* Default to the latest revision */
 483                 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
 484                 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
 485                 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
 486                 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
 487                 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
 488                 break;
 489         }
 490
 491         /* For OMAP5(ES2.0) and AM437x x_major is 2 even though there are
 492          * changes in wrapper registers, Using dt compatible for aegis
 493          */
 494
 495         if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
 496                 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
 497                 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
 498                 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
 499                 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
 500                 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
 501         }
 502
 503         reg = dwc3_omap_read_utmi_status(omap);
 504
 505         of_property_read_u32(node, "utmi-mode", &utmi_mode);
 506
 507         switch (utmi_mode) {
 508         case DWC3_OMAP_UTMI_MODE_SW:
 509                 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 510                 break;
 511         case DWC3_OMAP_UTMI_MODE_HW:
 512                 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 513                 break;
 514         default:
 515                 dev_dbg(dev, "UNKNOWN utmi mode %d\n", utmi_mode);
 516         }
 517
 518         dwc3_omap_write_utmi_status(omap, reg);
 519
 520         /* check the DMA Status */
 521         reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
 522         omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
 523
 524         ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
 525                         "dwc3-omap", omap);
 526         if (ret) {
 527                 dev_err(dev, "failed to request IRQ #%d --> %d\n",
 528                                 omap->irq, ret);
 529                 goto err1;
 530         }
 531
 532         dwc3_omap_enable_irqs(omap);
 533
 534         if (of_property_read_bool(node, "extcon")) {
 535                 edev = of_extcon_get_extcon_dev(dev, 0);
 536                 if (IS_ERR(edev)) {
 537                         dev_vdbg(dev, "couldn't get extcon device\n");
 538                         ret = PTR_ERR(edev);
 539                         goto err2;
 540                 }
 541
 542                 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
 543                 ret = extcon_register_interest(&omap->extcon_vbus_dev,
 544                         edev->name, "USB", &omap->vbus_nb);
 545                 if (ret < 0)
 546                         dev_vdbg(dev, "failed to register notifier for USB\n");
 547                 omap->id_nb.notifier_call = dwc3_omap_id_notifier;
 548                 ret = extcon_register_interest(&omap->extcon_id_dev, edev->name,
 549                                          "USB-HOST", &omap->id_nb);
 550                 if (ret < 0)
 551                         dev_vdbg(dev,
 552                                 "failed to register notifier for USB-HOST\n");
 553
 554                 if (extcon_get_cable_state(edev, "USB") == true)
 555                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
 556                 if (extcon_get_cable_state(edev, "USB-HOST") == true)
 557                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
 558         }
 559
 560         ret = of_platform_populate(node, NULL, NULL, dev);
 561         if (ret) {
 562                 dev_err(&pdev->dev, "failed to create dwc3 core\n");
 563                 goto err3;
 564         }
 565
 566         return 0;
 567
 568 err3:
 569         if (omap->extcon_vbus_dev.edev)
 570                 extcon_unregister_interest(&omap->extcon_vbus_dev);
 571         if (omap->extcon_id_dev.edev)
 572                 extcon_unregister_interest(&omap->extcon_id_dev);
 573
 574 err2:
 575         dwc3_omap_disable_irqs(omap);
 576
 577 err1:
 578         pm_runtime_put_sync(dev);
 579
 580 err0:
 581         pm_runtime_disable(dev);
 582
 583         return ret;
 584 }
 585
 586 static int dwc3_omap_remove(struct platform_device *pdev)
 587 {
 588         struct dwc3_omap        *omap = platform_get_drvdata(pdev);
 589
 590         if (omap->extcon_vbus_dev.edev)
 591                 extcon_unregister_interest(&omap->extcon_vbus_dev);
 592         if (omap->extcon_id_dev.edev)
 593                 extcon_unregister_interest(&omap->extcon_id_dev);
 594         dwc3_omap_disable_irqs(omap);
 595         pm_runtime_put_sync(&pdev->dev);
 596         pm_runtime_disable(&pdev->dev);
 597         device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
 598
 599         return 0;
 600 }
 601
 602 static const struct of_device_id of_dwc3_match[] = {
 603         {
 604                 .compatible =   "ti,dwc3"
 605         },
 606         {
 607                 .compatible =   "ti,am437x-dwc3"
 608         },
 609         { },
 610 };
 611 MODULE_DEVICE_TABLE(of, of_dwc3_match);
 612
 613 #ifdef CONFIG_PM_SLEEP
 614 static int dwc3_omap_prepare(struct device *dev)
 615 {
 616         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 617
 618         dwc3_omap_disable_irqs(omap);
 619
 620         return 0;
 621 }
 622
 623 static void dwc3_omap_complete(struct device *dev)
 624 {
 625         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 626
 627         dwc3_omap_enable_irqs(omap);
 628 }
 629
 630 static int dwc3_omap_suspend(struct device *dev)
 631 {
 632         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 633
 634         omap->utmi_otg_status = dwc3_omap_read_utmi_status(omap);
 635
 636         return 0;
 637 }
 638
 639 static int dwc3_omap_resume(struct device *dev)
 640 {
 641         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 642
 643         dwc3_omap_write_utmi_status(omap, omap->utmi_otg_status);
 644
 645         pm_runtime_disable(dev);
 646         pm_runtime_set_active(dev);
 647         pm_runtime_enable(dev);
 648
 649         return 0;
 650 }
 651
 652 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
 653         .prepare        = dwc3_omap_prepare,
 654         .complete       = dwc3_omap_complete,
 655
 656         SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
 657 };
 658
 659 #define DEV_PM_OPS      (&dwc3_omap_dev_pm_ops)
 660 #else
 661 #define DEV_PM_OPS      NULL
 662 #endif /* CONFIG_PM_SLEEP */
 663
 664 static struct platform_driver dwc3_omap_driver = {
 665         .probe          = dwc3_omap_probe,
 666         .remove         = dwc3_omap_remove,
 667         .driver         = {
 668                 .name   = "omap-dwc3",
 669                 .of_match_table = of_dwc3_match,
 670                 .pm     = DEV_PM_OPS,
 671         },
 672 };
 673
 674 module_platform_driver(dwc3_omap_driver);
 675
 676 MODULE_ALIAS("platform:omap-dwc3");
 677 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 678 MODULE_LICENSE("GPL v2");
 679 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");