2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/list.h>
97 #include <linux/kobject.h>
98 #include <linux/prefetch.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
102 #include <linux/usb.h>
104 #include "musb_core.h"
106 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
109 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
110 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
112 #define MUSB_VERSION "6.0"
114 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
116 #define MUSB_DRIVER_NAME "musb-hdrc"
117 const char musb_driver_name[] = MUSB_DRIVER_NAME;
119 MODULE_DESCRIPTION(DRIVER_INFO);
120 MODULE_AUTHOR(DRIVER_AUTHOR);
121 MODULE_LICENSE("GPL");
122 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
125 /*-------------------------------------------------------------------------*/
127 static inline struct musb *dev_to_musb(struct device *dev)
129 return dev_get_drvdata(dev);
132 /*-------------------------------------------------------------------------*/
134 #ifndef CONFIG_BLACKFIN
135 static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
137 void __iomem *addr = phy->io_priv;
143 pm_runtime_get_sync(phy->io_dev);
145 /* Make sure the transceiver is not in low power mode */
146 power = musb_readb(addr, MUSB_POWER);
147 power &= ~MUSB_POWER_SUSPENDM;
148 musb_writeb(addr, MUSB_POWER, power);
150 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
151 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
154 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
155 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
156 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
158 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
159 & MUSB_ULPI_REG_CMPLT)) {
167 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
168 r &= ~MUSB_ULPI_REG_CMPLT;
169 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
171 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
174 pm_runtime_put(phy->io_dev);
179 static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
181 void __iomem *addr = phy->io_priv;
187 pm_runtime_get_sync(phy->io_dev);
189 /* Make sure the transceiver is not in low power mode */
190 power = musb_readb(addr, MUSB_POWER);
191 power &= ~MUSB_POWER_SUSPENDM;
192 musb_writeb(addr, MUSB_POWER, power);
194 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
195 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
196 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
198 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
199 & MUSB_ULPI_REG_CMPLT)) {
207 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
208 r &= ~MUSB_ULPI_REG_CMPLT;
209 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
212 pm_runtime_put(phy->io_dev);
217 #define musb_ulpi_read NULL
218 #define musb_ulpi_write NULL
221 static struct usb_phy_io_ops musb_ulpi_access = {
222 .read = musb_ulpi_read,
223 .write = musb_ulpi_write,
226 /*-------------------------------------------------------------------------*/
228 static u32 musb_default_fifo_offset(u8 epnum)
230 return 0x20 + (epnum * 4);
233 /* "flat" mapping: each endpoint has its own i/o address */
234 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
238 static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
240 return 0x100 + (0x10 * epnum) + offset;
243 /* "indexed" mapping: INDEX register controls register bank select */
244 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
246 musb_writeb(mbase, MUSB_INDEX, epnum);
249 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
251 return 0x10 + offset;
254 static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
256 return 0x80 + (0x08 * epnum) + offset;
259 static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
261 return __raw_readb(addr + offset);
264 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
266 __raw_writeb(data, addr + offset);
269 static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
271 return __raw_readw(addr + offset);
274 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
276 __raw_writew(data, addr + offset);
279 static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
281 return __raw_readl(addr + offset);
284 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
286 __raw_writel(data, addr + offset);
290 * Load an endpoint's FIFO
292 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
295 struct musb *musb = hw_ep->musb;
296 void __iomem *fifo = hw_ep->fifo;
298 if (unlikely(len == 0))
303 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
304 'T', hw_ep->epnum, fifo, len, src);
306 /* we can't assume unaligned reads work */
307 if (likely((0x01 & (unsigned long) src) == 0)) {
310 /* best case is 32bit-aligned source address */
311 if ((0x02 & (unsigned long) src) == 0) {
313 iowrite32_rep(fifo, src + index, len >> 2);
314 index += len & ~0x03;
317 __raw_writew(*(u16 *)&src[index], fifo);
322 iowrite16_rep(fifo, src + index, len >> 1);
323 index += len & ~0x01;
327 __raw_writeb(src[index], fifo);
330 iowrite8_rep(fifo, src, len);
335 * Unload an endpoint's FIFO
337 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
339 struct musb *musb = hw_ep->musb;
340 void __iomem *fifo = hw_ep->fifo;
342 if (unlikely(len == 0))
345 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
346 'R', hw_ep->epnum, fifo, len, dst);
348 /* we can't assume unaligned writes work */
349 if (likely((0x01 & (unsigned long) dst) == 0)) {
352 /* best case is 32bit-aligned destination address */
353 if ((0x02 & (unsigned long) dst) == 0) {
355 ioread32_rep(fifo, dst, len >> 2);
359 *(u16 *)&dst[index] = __raw_readw(fifo);
364 ioread16_rep(fifo, dst, len >> 1);
369 dst[index] = __raw_readb(fifo);
372 ioread8_rep(fifo, dst, len);
377 * Old style IO functions
379 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
380 EXPORT_SYMBOL_GPL(musb_readb);
382 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
383 EXPORT_SYMBOL_GPL(musb_writeb);
385 u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
386 EXPORT_SYMBOL_GPL(musb_readw);
388 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
389 EXPORT_SYMBOL_GPL(musb_writew);
391 u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
392 EXPORT_SYMBOL_GPL(musb_readl);
394 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
395 EXPORT_SYMBOL_GPL(musb_writel);
397 #ifndef CONFIG_MUSB_PIO_ONLY
398 struct dma_controller *
399 (*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
400 EXPORT_SYMBOL(musb_dma_controller_create);
402 void (*musb_dma_controller_destroy)(struct dma_controller *c);
403 EXPORT_SYMBOL(musb_dma_controller_destroy);
407 * New style IO functions
409 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
411 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
414 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
416 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
419 /*-------------------------------------------------------------------------*/
421 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
422 static const u8 musb_test_packet[53] = {
423 /* implicit SYNC then DATA0 to start */
426 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
428 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
430 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
431 /* JJJJJJJKKKKKKK x8 */
432 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
434 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
435 /* JKKKKKKK x10, JK */
436 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
438 /* implicit CRC16 then EOP to end */
441 void musb_load_testpacket(struct musb *musb)
443 void __iomem *regs = musb->endpoints[0].regs;
445 musb_ep_select(musb->mregs, 0);
446 musb_write_fifo(musb->control_ep,
447 sizeof(musb_test_packet), musb_test_packet);
448 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
451 /*-------------------------------------------------------------------------*/
454 * Handles OTG hnp timeouts, such as b_ase0_brst
456 static void musb_otg_timer_func(unsigned long data)
458 struct musb *musb = (struct musb *)data;
461 spin_lock_irqsave(&musb->lock, flags);
462 switch (musb->xceiv->otg->state) {
463 case OTG_STATE_B_WAIT_ACON:
464 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
465 musb_g_disconnect(musb);
466 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
469 case OTG_STATE_A_SUSPEND:
470 case OTG_STATE_A_WAIT_BCON:
471 dev_dbg(musb->controller, "HNP: %s timeout\n",
472 usb_otg_state_string(musb->xceiv->otg->state));
473 musb_platform_set_vbus(musb, 0);
474 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
477 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
478 usb_otg_state_string(musb->xceiv->otg->state));
480 spin_unlock_irqrestore(&musb->lock, flags);
484 * Stops the HNP transition. Caller must take care of locking.
486 void musb_hnp_stop(struct musb *musb)
488 struct usb_hcd *hcd = musb->hcd;
489 void __iomem *mbase = musb->mregs;
492 dev_dbg(musb->controller, "HNP: stop from %s\n",
493 usb_otg_state_string(musb->xceiv->otg->state));
495 switch (musb->xceiv->otg->state) {
496 case OTG_STATE_A_PERIPHERAL:
497 musb_g_disconnect(musb);
498 dev_dbg(musb->controller, "HNP: back to %s\n",
499 usb_otg_state_string(musb->xceiv->otg->state));
501 case OTG_STATE_B_HOST:
502 dev_dbg(musb->controller, "HNP: Disabling HR\n");
504 hcd->self.is_b_host = 0;
505 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
507 reg = musb_readb(mbase, MUSB_POWER);
508 reg |= MUSB_POWER_SUSPENDM;
509 musb_writeb(mbase, MUSB_POWER, reg);
510 /* REVISIT: Start SESSION_REQUEST here? */
513 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
514 usb_otg_state_string(musb->xceiv->otg->state));
518 * When returning to A state after HNP, avoid hub_port_rebounce(),
519 * which cause occasional OPT A "Did not receive reset after connect"
522 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
525 static void musb_recover_from_babble(struct musb *musb);
528 * Interrupt Service Routine to record USB "global" interrupts.
529 * Since these do not happen often and signify things of
530 * paramount importance, it seems OK to check them individually;
531 * the order of the tests is specified in the manual
533 * @param musb instance pointer
534 * @param int_usb register contents
539 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
542 irqreturn_t handled = IRQ_NONE;
544 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
547 /* in host mode, the peripheral may issue remote wakeup.
548 * in peripheral mode, the host may resume the link.
549 * spurious RESUME irqs happen too, paired with SUSPEND.
551 if (int_usb & MUSB_INTR_RESUME) {
552 handled = IRQ_HANDLED;
553 dev_dbg(musb->controller, "RESUME (%s)\n",
554 usb_otg_state_string(musb->xceiv->otg->state));
556 if (devctl & MUSB_DEVCTL_HM) {
557 switch (musb->xceiv->otg->state) {
558 case OTG_STATE_A_SUSPEND:
559 /* remote wakeup? later, GetPortStatus
560 * will stop RESUME signaling
563 musb->port1_status |=
564 (USB_PORT_STAT_C_SUSPEND << 16)
565 | MUSB_PORT_STAT_RESUME;
566 musb->rh_timer = jiffies
567 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
568 musb->need_finish_resume = 1;
570 musb->xceiv->otg->state = OTG_STATE_A_HOST;
572 musb_host_resume_root_hub(musb);
574 case OTG_STATE_B_WAIT_ACON:
575 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
580 WARNING("bogus %s RESUME (%s)\n",
582 usb_otg_state_string(musb->xceiv->otg->state));
585 switch (musb->xceiv->otg->state) {
586 case OTG_STATE_A_SUSPEND:
587 /* possibly DISCONNECT is upcoming */
588 musb->xceiv->otg->state = OTG_STATE_A_HOST;
589 musb_host_resume_root_hub(musb);
591 case OTG_STATE_B_WAIT_ACON:
592 case OTG_STATE_B_PERIPHERAL:
593 /* disconnect while suspended? we may
594 * not get a disconnect irq...
596 if ((devctl & MUSB_DEVCTL_VBUS)
597 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
599 musb->int_usb |= MUSB_INTR_DISCONNECT;
600 musb->int_usb &= ~MUSB_INTR_SUSPEND;
605 case OTG_STATE_B_IDLE:
606 musb->int_usb &= ~MUSB_INTR_SUSPEND;
609 WARNING("bogus %s RESUME (%s)\n",
611 usb_otg_state_string(musb->xceiv->otg->state));
616 /* see manual for the order of the tests */
617 if (int_usb & MUSB_INTR_SESSREQ) {
618 void __iomem *mbase = musb->mregs;
620 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
621 && (devctl & MUSB_DEVCTL_BDEVICE)) {
622 dev_dbg(musb->controller, "SessReq while on B state\n");
626 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
627 usb_otg_state_string(musb->xceiv->otg->state));
629 /* IRQ arrives from ID pin sense or (later, if VBUS power
630 * is removed) SRP. responses are time critical:
631 * - turn on VBUS (with silicon-specific mechanism)
632 * - go through A_WAIT_VRISE
633 * - ... to A_WAIT_BCON.
634 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
636 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
637 musb->ep0_stage = MUSB_EP0_START;
638 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
640 musb_platform_set_vbus(musb, 1);
642 handled = IRQ_HANDLED;
645 if (int_usb & MUSB_INTR_VBUSERROR) {
648 /* During connection as an A-Device, we may see a short
649 * current spikes causing voltage drop, because of cable
650 * and peripheral capacitance combined with vbus draw.
651 * (So: less common with truly self-powered devices, where
652 * vbus doesn't act like a power supply.)
654 * Such spikes are short; usually less than ~500 usec, max
655 * of ~2 msec. That is, they're not sustained overcurrent
656 * errors, though they're reported using VBUSERROR irqs.
658 * Workarounds: (a) hardware: use self powered devices.
659 * (b) software: ignore non-repeated VBUS errors.
661 * REVISIT: do delays from lots of DEBUG_KERNEL checks
662 * make trouble here, keeping VBUS < 4.4V ?
664 switch (musb->xceiv->otg->state) {
665 case OTG_STATE_A_HOST:
666 /* recovery is dicey once we've gotten past the
667 * initial stages of enumeration, but if VBUS
668 * stayed ok at the other end of the link, and
669 * another reset is due (at least for high speed,
670 * to redo the chirp etc), it might work OK...
672 case OTG_STATE_A_WAIT_BCON:
673 case OTG_STATE_A_WAIT_VRISE:
674 if (musb->vbuserr_retry) {
675 void __iomem *mbase = musb->mregs;
677 musb->vbuserr_retry--;
679 devctl |= MUSB_DEVCTL_SESSION;
680 musb_writeb(mbase, MUSB_DEVCTL, devctl);
682 musb->port1_status |=
683 USB_PORT_STAT_OVERCURRENT
684 | (USB_PORT_STAT_C_OVERCURRENT << 16);
691 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
692 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
693 usb_otg_state_string(musb->xceiv->otg->state),
696 switch (devctl & MUSB_DEVCTL_VBUS) {
697 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
698 s = "<SessEnd"; break;
699 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
700 s = "<AValid"; break;
701 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
702 s = "<VBusValid"; break;
703 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
707 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
710 /* go through A_WAIT_VFALL then start a new session */
712 musb_platform_set_vbus(musb, 0);
713 handled = IRQ_HANDLED;
716 if (int_usb & MUSB_INTR_SUSPEND) {
717 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
718 usb_otg_state_string(musb->xceiv->otg->state), devctl);
719 handled = IRQ_HANDLED;
721 switch (musb->xceiv->otg->state) {
722 case OTG_STATE_A_PERIPHERAL:
723 /* We also come here if the cable is removed, since
724 * this silicon doesn't report ID-no-longer-grounded.
726 * We depend on T(a_wait_bcon) to shut us down, and
727 * hope users don't do anything dicey during this
728 * undesired detour through A_WAIT_BCON.
731 musb_host_resume_root_hub(musb);
732 musb_root_disconnect(musb);
733 musb_platform_try_idle(musb, jiffies
734 + msecs_to_jiffies(musb->a_wait_bcon
735 ? : OTG_TIME_A_WAIT_BCON));
738 case OTG_STATE_B_IDLE:
739 if (!musb->is_active)
741 case OTG_STATE_B_PERIPHERAL:
742 musb_g_suspend(musb);
743 musb->is_active = musb->g.b_hnp_enable;
744 if (musb->is_active) {
745 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
746 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
747 mod_timer(&musb->otg_timer, jiffies
749 OTG_TIME_B_ASE0_BRST));
752 case OTG_STATE_A_WAIT_BCON:
753 if (musb->a_wait_bcon != 0)
754 musb_platform_try_idle(musb, jiffies
755 + msecs_to_jiffies(musb->a_wait_bcon));
757 case OTG_STATE_A_HOST:
758 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
759 musb->is_active = musb->hcd->self.b_hnp_enable;
761 case OTG_STATE_B_HOST:
762 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
763 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
766 /* "should not happen" */
771 if (int_usb & MUSB_INTR_CONNECT) {
772 struct usb_hcd *hcd = musb->hcd;
774 handled = IRQ_HANDLED;
777 musb->ep0_stage = MUSB_EP0_START;
779 musb->intrtxe = musb->epmask;
780 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
781 musb->intrrxe = musb->epmask & 0xfffe;
782 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
783 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
784 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
785 |USB_PORT_STAT_HIGH_SPEED
786 |USB_PORT_STAT_ENABLE
788 musb->port1_status |= USB_PORT_STAT_CONNECTION
789 |(USB_PORT_STAT_C_CONNECTION << 16);
791 /* high vs full speed is just a guess until after reset */
792 if (devctl & MUSB_DEVCTL_LSDEV)
793 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
795 /* indicate new connection to OTG machine */
796 switch (musb->xceiv->otg->state) {
797 case OTG_STATE_B_PERIPHERAL:
798 if (int_usb & MUSB_INTR_SUSPEND) {
799 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
800 int_usb &= ~MUSB_INTR_SUSPEND;
803 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
805 case OTG_STATE_B_WAIT_ACON:
806 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
808 musb->xceiv->otg->state = OTG_STATE_B_HOST;
810 musb->hcd->self.is_b_host = 1;
811 del_timer(&musb->otg_timer);
814 if ((devctl & MUSB_DEVCTL_VBUS)
815 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
816 musb->xceiv->otg->state = OTG_STATE_A_HOST;
818 hcd->self.is_b_host = 0;
822 musb_host_poke_root_hub(musb);
824 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
825 usb_otg_state_string(musb->xceiv->otg->state), devctl);
828 if (int_usb & MUSB_INTR_DISCONNECT) {
829 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
830 usb_otg_state_string(musb->xceiv->otg->state),
831 MUSB_MODE(musb), devctl);
832 handled = IRQ_HANDLED;
834 switch (musb->xceiv->otg->state) {
835 case OTG_STATE_A_HOST:
836 case OTG_STATE_A_SUSPEND:
837 musb_host_resume_root_hub(musb);
838 musb_root_disconnect(musb);
839 if (musb->a_wait_bcon != 0)
840 musb_platform_try_idle(musb, jiffies
841 + msecs_to_jiffies(musb->a_wait_bcon));
843 case OTG_STATE_B_HOST:
844 /* REVISIT this behaves for "real disconnect"
845 * cases; make sure the other transitions from
846 * from B_HOST act right too. The B_HOST code
847 * in hnp_stop() is currently not used...
849 musb_root_disconnect(musb);
851 musb->hcd->self.is_b_host = 0;
852 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
854 musb_g_disconnect(musb);
856 case OTG_STATE_A_PERIPHERAL:
858 musb_root_disconnect(musb);
860 case OTG_STATE_B_WAIT_ACON:
862 case OTG_STATE_B_PERIPHERAL:
863 case OTG_STATE_B_IDLE:
864 musb_g_disconnect(musb);
867 WARNING("unhandled DISCONNECT transition (%s)\n",
868 usb_otg_state_string(musb->xceiv->otg->state));
872 /* mentor saves a bit: bus reset and babble share the same irq.
873 * only host sees babble; only peripheral sees bus reset.
875 if (int_usb & MUSB_INTR_RESET) {
876 handled = IRQ_HANDLED;
877 if (devctl & MUSB_DEVCTL_HM) {
879 * When BABBLE happens what we can depends on which
880 * platform MUSB is running, because some platforms
881 * implemented proprietary means for 'recovering' from
882 * Babble conditions. One such platform is AM335x. In
883 * most cases, however, the only thing we can do is
886 dev_err(musb->controller, "Babble\n");
888 if (is_host_active(musb))
889 musb_recover_from_babble(musb);
891 dev_dbg(musb->controller, "BUS RESET as %s\n",
892 usb_otg_state_string(musb->xceiv->otg->state));
893 switch (musb->xceiv->otg->state) {
894 case OTG_STATE_A_SUSPEND:
897 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
898 /* never use invalid T(a_wait_bcon) */
899 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
900 usb_otg_state_string(musb->xceiv->otg->state),
902 mod_timer(&musb->otg_timer, jiffies
903 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
905 case OTG_STATE_A_PERIPHERAL:
906 del_timer(&musb->otg_timer);
909 case OTG_STATE_B_WAIT_ACON:
910 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
911 usb_otg_state_string(musb->xceiv->otg->state));
912 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
915 case OTG_STATE_B_IDLE:
916 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
918 case OTG_STATE_B_PERIPHERAL:
922 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
923 usb_otg_state_string(musb->xceiv->otg->state));
929 /* REVISIT ... this would be for multiplexing periodic endpoints, or
930 * supporting transfer phasing to prevent exceeding ISO bandwidth
931 * limits of a given frame or microframe.
933 * It's not needed for peripheral side, which dedicates endpoints;
934 * though it _might_ use SOF irqs for other purposes.
936 * And it's not currently needed for host side, which also dedicates
937 * endpoints, relies on TX/RX interval registers, and isn't claimed
938 * to support ISO transfers yet.
940 if (int_usb & MUSB_INTR_SOF) {
941 void __iomem *mbase = musb->mregs;
942 struct musb_hw_ep *ep;
946 dev_dbg(musb->controller, "START_OF_FRAME\n");
947 handled = IRQ_HANDLED;
949 /* start any periodic Tx transfers waiting for current frame */
950 frame = musb_readw(mbase, MUSB_FRAME);
951 ep = musb->endpoints;
952 for (epnum = 1; (epnum < musb->nr_endpoints)
953 && (musb->epmask >= (1 << epnum));
956 * FIXME handle framecounter wraps (12 bits)
957 * eliminate duplicated StartUrb logic
959 if (ep->dwWaitFrame >= frame) {
961 pr_debug("SOF --> periodic TX%s on %d\n",
962 ep->tx_channel ? " DMA" : "",
965 musb_h_tx_start(musb, epnum);
967 cppi_hostdma_start(musb, epnum);
969 } /* end of for loop */
973 schedule_work(&musb->irq_work);
978 /*-------------------------------------------------------------------------*/
980 static void musb_disable_interrupts(struct musb *musb)
982 void __iomem *mbase = musb->mregs;
985 /* disable interrupts */
986 musb_writeb(mbase, MUSB_INTRUSBE, 0);
988 musb_writew(mbase, MUSB_INTRTXE, 0);
990 musb_writew(mbase, MUSB_INTRRXE, 0);
992 /* flush pending interrupts */
993 temp = musb_readb(mbase, MUSB_INTRUSB);
994 temp = musb_readw(mbase, MUSB_INTRTX);
995 temp = musb_readw(mbase, MUSB_INTRRX);
998 static void musb_enable_interrupts(struct musb *musb)
1000 void __iomem *regs = musb->mregs;
1002 /* Set INT enable registers, enable interrupts */
1003 musb->intrtxe = musb->epmask;
1004 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1005 musb->intrrxe = musb->epmask & 0xfffe;
1006 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1007 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1011 static void musb_generic_disable(struct musb *musb)
1013 void __iomem *mbase = musb->mregs;
1015 musb_disable_interrupts(musb);
1018 musb_writeb(mbase, MUSB_DEVCTL, 0);
1022 * Program the HDRC to start (enable interrupts, dma, etc.).
1024 void musb_start(struct musb *musb)
1026 void __iomem *regs = musb->mregs;
1027 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1030 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1032 musb_enable_interrupts(musb);
1033 musb_writeb(regs, MUSB_TESTMODE, 0);
1035 power = MUSB_POWER_ISOUPDATE;
1037 * treating UNKNOWN as unspecified maximum speed, in which case
1038 * we will default to high-speed.
1040 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1041 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1042 power |= MUSB_POWER_HSENAB;
1043 musb_writeb(regs, MUSB_POWER, power);
1045 musb->is_active = 0;
1046 devctl = musb_readb(regs, MUSB_DEVCTL);
1047 devctl &= ~MUSB_DEVCTL_SESSION;
1049 /* session started after:
1050 * (a) ID-grounded irq, host mode;
1051 * (b) vbus present/connect IRQ, peripheral mode;
1052 * (c) peripheral initiates, using SRP
1054 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1055 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
1056 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1057 musb->is_active = 1;
1059 devctl |= MUSB_DEVCTL_SESSION;
1062 musb_platform_enable(musb);
1063 musb_writeb(regs, MUSB_DEVCTL, devctl);
1067 * Make the HDRC stop (disable interrupts, etc.);
1068 * reversible by musb_start
1069 * called on gadget driver unregister
1070 * with controller locked, irqs blocked
1071 * acts as a NOP unless some role activated the hardware
1073 void musb_stop(struct musb *musb)
1075 /* stop IRQs, timers, ... */
1076 musb_platform_disable(musb);
1077 musb_generic_disable(musb);
1078 dev_dbg(musb->controller, "HDRC disabled\n");
1081 * - mark host and/or peripheral drivers unusable/inactive
1082 * - disable DMA (and enable it in HdrcStart)
1083 * - make sure we can musb_start() after musb_stop(); with
1084 * OTG mode, gadget driver module rmmod/modprobe cycles that
1087 musb_platform_try_idle(musb, 0);
1090 static void musb_shutdown(struct platform_device *pdev)
1092 struct musb *musb = dev_to_musb(&pdev->dev);
1093 unsigned long flags;
1095 pm_runtime_get_sync(musb->controller);
1097 musb_host_cleanup(musb);
1098 musb_gadget_cleanup(musb);
1100 spin_lock_irqsave(&musb->lock, flags);
1101 musb_platform_disable(musb);
1102 musb_generic_disable(musb);
1103 spin_unlock_irqrestore(&musb->lock, flags);
1105 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1106 musb_platform_exit(musb);
1108 pm_runtime_put(musb->controller);
1109 /* FIXME power down */
1113 /*-------------------------------------------------------------------------*/
1116 * The silicon either has hard-wired endpoint configurations, or else
1117 * "dynamic fifo" sizing. The driver has support for both, though at this
1118 * writing only the dynamic sizing is very well tested. Since we switched
1119 * away from compile-time hardware parameters, we can no longer rely on
1120 * dead code elimination to leave only the relevant one in the object file.
1122 * We don't currently use dynamic fifo setup capability to do anything
1123 * more than selecting one of a bunch of predefined configurations.
1125 static ushort fifo_mode;
1127 /* "modprobe ... fifo_mode=1" etc */
1128 module_param(fifo_mode, ushort, 0);
1129 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1132 * tables defining fifo_mode values. define more if you like.
1133 * for host side, make sure both halves of ep1 are set up.
1136 /* mode 0 - fits in 2KB */
1137 static struct musb_fifo_cfg mode_0_cfg[] = {
1138 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1139 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1140 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1141 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1142 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1145 /* mode 1 - fits in 4KB */
1146 static struct musb_fifo_cfg mode_1_cfg[] = {
1147 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1148 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1149 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1150 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1151 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1154 /* mode 2 - fits in 4KB */
1155 static struct musb_fifo_cfg mode_2_cfg[] = {
1156 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1157 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1158 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1159 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1160 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1161 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1164 /* mode 3 - fits in 4KB */
1165 static struct musb_fifo_cfg mode_3_cfg[] = {
1166 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1167 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1168 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1169 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1170 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1171 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1174 /* mode 4 - fits in 16KB */
1175 static struct musb_fifo_cfg mode_4_cfg[] = {
1176 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1177 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1178 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1179 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1180 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1181 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1182 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1183 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1184 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1185 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1186 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1187 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1188 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1189 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1190 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1191 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1192 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1193 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1194 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1195 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1196 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1197 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1198 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1199 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1200 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1201 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1202 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1205 /* mode 5 - fits in 8KB */
1206 static struct musb_fifo_cfg mode_5_cfg[] = {
1207 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1208 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1209 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1210 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1211 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1212 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1213 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1214 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1215 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1216 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1217 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1218 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1219 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1220 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1221 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1222 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1223 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1224 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1225 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1226 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1227 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1228 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1229 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1230 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1231 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1232 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1233 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1237 * configure a fifo; for non-shared endpoints, this may be called
1238 * once for a tx fifo and once for an rx fifo.
1240 * returns negative errno or offset for next fifo.
1243 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1244 const struct musb_fifo_cfg *cfg, u16 offset)
1246 void __iomem *mbase = musb->mregs;
1248 u16 maxpacket = cfg->maxpacket;
1249 u16 c_off = offset >> 3;
1252 /* expect hw_ep has already been zero-initialized */
1254 size = ffs(max(maxpacket, (u16) 8)) - 1;
1255 maxpacket = 1 << size;
1258 if (cfg->mode == BUF_DOUBLE) {
1259 if ((offset + (maxpacket << 1)) >
1260 (1 << (musb->config->ram_bits + 2)))
1262 c_size |= MUSB_FIFOSZ_DPB;
1264 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1268 /* configure the FIFO */
1269 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1271 /* EP0 reserved endpoint for control, bidirectional;
1272 * EP1 reserved for bulk, two unidirectional halves.
1274 if (hw_ep->epnum == 1)
1275 musb->bulk_ep = hw_ep;
1276 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1277 switch (cfg->style) {
1279 musb_write_txfifosz(mbase, c_size);
1280 musb_write_txfifoadd(mbase, c_off);
1281 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1282 hw_ep->max_packet_sz_tx = maxpacket;
1285 musb_write_rxfifosz(mbase, c_size);
1286 musb_write_rxfifoadd(mbase, c_off);
1287 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1288 hw_ep->max_packet_sz_rx = maxpacket;
1291 musb_write_txfifosz(mbase, c_size);
1292 musb_write_txfifoadd(mbase, c_off);
1293 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1294 hw_ep->max_packet_sz_rx = maxpacket;
1296 musb_write_rxfifosz(mbase, c_size);
1297 musb_write_rxfifoadd(mbase, c_off);
1298 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1299 hw_ep->max_packet_sz_tx = maxpacket;
1301 hw_ep->is_shared_fifo = true;
1305 /* NOTE rx and tx endpoint irqs aren't managed separately,
1306 * which happens to be ok
1308 musb->epmask |= (1 << hw_ep->epnum);
1310 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1313 static struct musb_fifo_cfg ep0_cfg = {
1314 .style = FIFO_RXTX, .maxpacket = 64,
1317 static int ep_config_from_table(struct musb *musb)
1319 const struct musb_fifo_cfg *cfg;
1322 struct musb_hw_ep *hw_ep = musb->endpoints;
1324 if (musb->config->fifo_cfg) {
1325 cfg = musb->config->fifo_cfg;
1326 n = musb->config->fifo_cfg_size;
1330 switch (fifo_mode) {
1336 n = ARRAY_SIZE(mode_0_cfg);
1340 n = ARRAY_SIZE(mode_1_cfg);
1344 n = ARRAY_SIZE(mode_2_cfg);
1348 n = ARRAY_SIZE(mode_3_cfg);
1352 n = ARRAY_SIZE(mode_4_cfg);
1356 n = ARRAY_SIZE(mode_5_cfg);
1360 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1361 musb_driver_name, fifo_mode);
1365 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1366 /* assert(offset > 0) */
1368 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1369 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1372 for (i = 0; i < n; i++) {
1373 u8 epn = cfg->hw_ep_num;
1375 if (epn >= musb->config->num_eps) {
1376 pr_debug("%s: invalid ep %d\n",
1377 musb_driver_name, epn);
1380 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1382 pr_debug("%s: mem overrun, ep %d\n",
1383 musb_driver_name, epn);
1387 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1390 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1392 n + 1, musb->config->num_eps * 2 - 1,
1393 offset, (1 << (musb->config->ram_bits + 2)));
1395 if (!musb->bulk_ep) {
1396 pr_debug("%s: missing bulk\n", musb_driver_name);
1405 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1406 * @param musb the controller
1408 static int ep_config_from_hw(struct musb *musb)
1411 struct musb_hw_ep *hw_ep;
1412 void __iomem *mbase = musb->mregs;
1415 dev_dbg(musb->controller, "<== static silicon ep config\n");
1417 /* FIXME pick up ep0 maxpacket size */
1419 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1420 musb_ep_select(mbase, epnum);
1421 hw_ep = musb->endpoints + epnum;
1423 ret = musb_read_fifosize(musb, hw_ep, epnum);
1427 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1429 /* pick an RX/TX endpoint for bulk */
1430 if (hw_ep->max_packet_sz_tx < 512
1431 || hw_ep->max_packet_sz_rx < 512)
1434 /* REVISIT: this algorithm is lazy, we should at least
1435 * try to pick a double buffered endpoint.
1439 musb->bulk_ep = hw_ep;
1442 if (!musb->bulk_ep) {
1443 pr_debug("%s: missing bulk\n", musb_driver_name);
1450 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1452 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1453 * configure endpoints, or take their config from silicon
1455 static int musb_core_init(u16 musb_type, struct musb *musb)
1459 char aInfo[90], aRevision[32], aDate[12];
1460 void __iomem *mbase = musb->mregs;
1464 /* log core options (read using indexed model) */
1465 reg = musb_read_configdata(mbase);
1467 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1468 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1469 strcat(aInfo, ", dyn FIFOs");
1470 musb->dyn_fifo = true;
1472 if (reg & MUSB_CONFIGDATA_MPRXE) {
1473 strcat(aInfo, ", bulk combine");
1474 musb->bulk_combine = true;
1476 if (reg & MUSB_CONFIGDATA_MPTXE) {
1477 strcat(aInfo, ", bulk split");
1478 musb->bulk_split = true;
1480 if (reg & MUSB_CONFIGDATA_HBRXE) {
1481 strcat(aInfo, ", HB-ISO Rx");
1482 musb->hb_iso_rx = true;
1484 if (reg & MUSB_CONFIGDATA_HBTXE) {
1485 strcat(aInfo, ", HB-ISO Tx");
1486 musb->hb_iso_tx = true;
1488 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1489 strcat(aInfo, ", SoftConn");
1491 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1492 musb_driver_name, reg, aInfo);
1495 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1496 musb->is_multipoint = 1;
1499 musb->is_multipoint = 0;
1501 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1503 "%s: kernel must blacklist external hubs\n",
1508 /* log release info */
1509 musb->hwvers = musb_read_hwvers(mbase);
1510 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1511 MUSB_HWVERS_MINOR(musb->hwvers),
1512 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1513 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1514 musb_driver_name, type, aRevision, aDate);
1517 musb_configure_ep0(musb);
1519 /* discover endpoint configuration */
1520 musb->nr_endpoints = 1;
1524 status = ep_config_from_table(musb);
1526 status = ep_config_from_hw(musb);
1531 /* finish init, and print endpoint config */
1532 for (i = 0; i < musb->nr_endpoints; i++) {
1533 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1535 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1536 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1537 if (musb->io.quirks & MUSB_IN_TUSB) {
1538 hw_ep->fifo_async = musb->async + 0x400 +
1539 musb->io.fifo_offset(i);
1540 hw_ep->fifo_sync = musb->sync + 0x400 +
1541 musb->io.fifo_offset(i);
1542 hw_ep->fifo_sync_va =
1543 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1546 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1548 hw_ep->conf = mbase + 0x400 +
1549 (((i - 1) & 0xf) << 2);
1553 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1554 hw_ep->rx_reinit = 1;
1555 hw_ep->tx_reinit = 1;
1557 if (hw_ep->max_packet_sz_tx) {
1558 dev_dbg(musb->controller,
1559 "%s: hw_ep %d%s, %smax %d\n",
1560 musb_driver_name, i,
1561 hw_ep->is_shared_fifo ? "shared" : "tx",
1562 hw_ep->tx_double_buffered
1563 ? "doublebuffer, " : "",
1564 hw_ep->max_packet_sz_tx);
1566 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1567 dev_dbg(musb->controller,
1568 "%s: hw_ep %d%s, %smax %d\n",
1569 musb_driver_name, i,
1571 hw_ep->rx_double_buffered
1572 ? "doublebuffer, " : "",
1573 hw_ep->max_packet_sz_rx);
1575 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1576 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1582 /*-------------------------------------------------------------------------*/
1585 * handle all the irqs defined by the HDRC core. for now we expect: other
1586 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1587 * will be assigned, and the irq will already have been acked.
1589 * called in irq context with spinlock held, irqs blocked
1591 irqreturn_t musb_interrupt(struct musb *musb)
1593 irqreturn_t retval = IRQ_NONE;
1594 unsigned long status;
1595 unsigned long epnum;
1598 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1601 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1603 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1604 is_host_active(musb) ? "host" : "peripheral",
1605 musb->int_usb, musb->int_tx, musb->int_rx);
1608 * According to Mentor Graphics' documentation, flowchart on page 98,
1609 * IRQ should be handled as follows:
1612 * . Session Request IRQ
1617 * . Reset/Babble IRQ
1618 * . SOF IRQ (we're not using this one)
1623 * We will be following that flowchart in order to avoid any problems
1624 * that might arise with internal Finite State Machine.
1628 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1630 if (musb->int_tx & 1) {
1631 if (is_host_active(musb))
1632 retval |= musb_h_ep0_irq(musb);
1634 retval |= musb_g_ep0_irq(musb);
1636 /* we have just handled endpoint 0 IRQ, clear it */
1637 musb->int_tx &= ~BIT(0);
1640 status = musb->int_tx;
1642 for_each_set_bit(epnum, &status, 16) {
1643 retval = IRQ_HANDLED;
1644 if (is_host_active(musb))
1645 musb_host_tx(musb, epnum);
1647 musb_g_tx(musb, epnum);
1650 status = musb->int_rx;
1652 for_each_set_bit(epnum, &status, 16) {
1653 retval = IRQ_HANDLED;
1654 if (is_host_active(musb))
1655 musb_host_rx(musb, epnum);
1657 musb_g_rx(musb, epnum);
1662 EXPORT_SYMBOL_GPL(musb_interrupt);
1664 #ifndef CONFIG_MUSB_PIO_ONLY
1665 static bool use_dma = 1;
1667 /* "modprobe ... use_dma=0" etc */
1668 module_param(use_dma, bool, 0644);
1669 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1671 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1673 /* called with controller lock already held */
1676 if (!is_cppi_enabled(musb)) {
1678 if (is_host_active(musb))
1679 musb_h_ep0_irq(musb);
1681 musb_g_ep0_irq(musb);
1684 /* endpoints 1..15 */
1686 if (is_host_active(musb))
1687 musb_host_tx(musb, epnum);
1689 musb_g_tx(musb, epnum);
1692 if (is_host_active(musb))
1693 musb_host_rx(musb, epnum);
1695 musb_g_rx(musb, epnum);
1699 EXPORT_SYMBOL_GPL(musb_dma_completion);
1705 /*-------------------------------------------------------------------------*/
1708 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1710 struct musb *musb = dev_to_musb(dev);
1711 unsigned long flags;
1714 spin_lock_irqsave(&musb->lock, flags);
1715 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1716 spin_unlock_irqrestore(&musb->lock, flags);
1722 musb_mode_store(struct device *dev, struct device_attribute *attr,
1723 const char *buf, size_t n)
1725 struct musb *musb = dev_to_musb(dev);
1726 unsigned long flags;
1729 spin_lock_irqsave(&musb->lock, flags);
1730 if (sysfs_streq(buf, "host"))
1731 status = musb_platform_set_mode(musb, MUSB_HOST);
1732 else if (sysfs_streq(buf, "peripheral"))
1733 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1734 else if (sysfs_streq(buf, "otg"))
1735 status = musb_platform_set_mode(musb, MUSB_OTG);
1738 spin_unlock_irqrestore(&musb->lock, flags);
1740 return (status == 0) ? n : status;
1742 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1745 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1746 const char *buf, size_t n)
1748 struct musb *musb = dev_to_musb(dev);
1749 unsigned long flags;
1752 if (sscanf(buf, "%lu", &val) < 1) {
1753 dev_err(dev, "Invalid VBUS timeout ms value\n");
1757 spin_lock_irqsave(&musb->lock, flags);
1758 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1759 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1760 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1761 musb->is_active = 0;
1762 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1763 spin_unlock_irqrestore(&musb->lock, flags);
1769 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1771 struct musb *musb = dev_to_musb(dev);
1772 unsigned long flags;
1777 spin_lock_irqsave(&musb->lock, flags);
1778 val = musb->a_wait_bcon;
1779 vbus = musb_platform_get_vbus_status(musb);
1781 /* Use default MUSB method by means of DEVCTL register */
1782 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1783 if ((devctl & MUSB_DEVCTL_VBUS)
1784 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1789 spin_unlock_irqrestore(&musb->lock, flags);
1791 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1792 vbus ? "on" : "off", val);
1794 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1796 /* Gadget drivers can't know that a host is connected so they might want
1797 * to start SRP, but users can. This allows userspace to trigger SRP.
1800 musb_srp_store(struct device *dev, struct device_attribute *attr,
1801 const char *buf, size_t n)
1803 struct musb *musb = dev_to_musb(dev);
1806 if (sscanf(buf, "%hu", &srp) != 1
1808 dev_err(dev, "SRP: Value must be 1\n");
1813 musb_g_wakeup(musb);
1817 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1819 static struct attribute *musb_attributes[] = {
1820 &dev_attr_mode.attr,
1821 &dev_attr_vbus.attr,
1826 static const struct attribute_group musb_attr_group = {
1827 .attrs = musb_attributes,
1830 /* Only used to provide driver mode change events */
1831 static void musb_irq_work(struct work_struct *data)
1833 struct musb *musb = container_of(data, struct musb, irq_work);
1835 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1836 musb->xceiv_old_state = musb->xceiv->otg->state;
1837 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1841 static void musb_recover_from_babble(struct musb *musb)
1846 musb_disable_interrupts(musb);
1849 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1850 * it some slack and wait for 10us.
1854 ret = musb_platform_recover(musb);
1856 musb_enable_interrupts(musb);
1860 /* drop session bit */
1861 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1862 devctl &= ~MUSB_DEVCTL_SESSION;
1863 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1865 /* tell usbcore about it */
1866 musb_root_disconnect(musb);
1869 * When a babble condition occurs, the musb controller
1870 * removes the session bit and the endpoint config is lost.
1873 ret = ep_config_from_table(musb);
1875 ret = ep_config_from_hw(musb);
1877 /* restart session */
1882 /* --------------------------------------------------------------------------
1886 static struct musb *allocate_instance(struct device *dev,
1887 struct musb_hdrc_config *config, void __iomem *mbase)
1890 struct musb_hw_ep *ep;
1894 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1898 INIT_LIST_HEAD(&musb->control);
1899 INIT_LIST_HEAD(&musb->in_bulk);
1900 INIT_LIST_HEAD(&musb->out_bulk);
1902 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1903 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1904 musb->mregs = mbase;
1905 musb->ctrl_base = mbase;
1906 musb->nIrq = -ENODEV;
1907 musb->config = config;
1908 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1909 for (epnum = 0, ep = musb->endpoints;
1910 epnum < musb->config->num_eps;
1916 musb->controller = dev;
1918 ret = musb_host_alloc(musb);
1922 dev_set_drvdata(dev, musb);
1930 static void musb_free(struct musb *musb)
1932 /* this has multiple entry modes. it handles fault cleanup after
1933 * probe(), where things may be partially set up, as well as rmmod
1934 * cleanup after everything's been de-activated.
1938 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1941 if (musb->nIrq >= 0) {
1943 disable_irq_wake(musb->nIrq);
1944 free_irq(musb->nIrq, musb);
1947 musb_host_free(musb);
1950 static void musb_deassert_reset(struct work_struct *work)
1953 unsigned long flags;
1955 musb = container_of(work, struct musb, deassert_reset_work.work);
1957 spin_lock_irqsave(&musb->lock, flags);
1959 if (musb->port1_status & USB_PORT_STAT_RESET)
1960 musb_port_reset(musb, false);
1962 spin_unlock_irqrestore(&musb->lock, flags);
1966 * Perform generic per-controller initialization.
1968 * @dev: the controller (already clocked, etc)
1970 * @ctrl: virtual address of controller registers,
1971 * not yet corrected for platform-specific offsets
1974 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1978 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1980 /* The driver might handle more features than the board; OK.
1981 * Fail when the board needs a feature that's not enabled.
1984 dev_err(dev, "no platform_data?\n");
1990 musb = allocate_instance(dev, plat->config, ctrl);
1996 spin_lock_init(&musb->lock);
1997 musb->board_set_power = plat->set_power;
1998 musb->min_power = plat->min_power;
1999 musb->ops = plat->platform_ops;
2000 musb->port_mode = plat->mode;
2003 * Initialize the default IO functions. At least omap2430 needs
2004 * these early. We initialize the platform specific IO functions
2007 musb_readb = musb_default_readb;
2008 musb_writeb = musb_default_writeb;
2009 musb_readw = musb_default_readw;
2010 musb_writew = musb_default_writew;
2011 musb_readl = musb_default_readl;
2012 musb_writel = musb_default_writel;
2014 /* We need musb_read/write functions initialized for PM */
2015 pm_runtime_use_autosuspend(musb->controller);
2016 pm_runtime_set_autosuspend_delay(musb->controller, 200);
2017 pm_runtime_enable(musb->controller);
2019 /* The musb_platform_init() call:
2020 * - adjusts musb->mregs
2021 * - sets the musb->isr
2022 * - may initialize an integrated transceiver
2023 * - initializes musb->xceiv, usually by otg_get_phy()
2024 * - stops powering VBUS
2026 * There are various transceiver configurations. Blackfin,
2027 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2028 * external/discrete ones in various flavors (twl4030 family,
2029 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2031 status = musb_platform_init(musb);
2040 if (musb->ops->quirks)
2041 musb->io.quirks = musb->ops->quirks;
2043 /* Most devices use indexed offset or flat offset */
2044 if (musb->io.quirks & MUSB_INDEXED_EP) {
2045 musb->io.ep_offset = musb_indexed_ep_offset;
2046 musb->io.ep_select = musb_indexed_ep_select;
2048 musb->io.ep_offset = musb_flat_ep_offset;
2049 musb->io.ep_select = musb_flat_ep_select;
2051 /* And override them with platform specific ops if specified. */
2052 if (musb->ops->ep_offset)
2053 musb->io.ep_offset = musb->ops->ep_offset;
2054 if (musb->ops->ep_select)
2055 musb->io.ep_select = musb->ops->ep_select;
2057 /* At least tusb6010 has its own offsets */
2058 if (musb->ops->ep_offset)
2059 musb->io.ep_offset = musb->ops->ep_offset;
2060 if (musb->ops->ep_select)
2061 musb->io.ep_select = musb->ops->ep_select;
2063 if (musb->ops->fifo_mode)
2064 fifo_mode = musb->ops->fifo_mode;
2068 if (musb->ops->fifo_offset)
2069 musb->io.fifo_offset = musb->ops->fifo_offset;
2071 musb->io.fifo_offset = musb_default_fifo_offset;
2073 if (musb->ops->busctl_offset)
2074 musb->io.busctl_offset = musb->ops->busctl_offset;
2076 musb->io.busctl_offset = musb_default_busctl_offset;
2078 if (musb->ops->readb)
2079 musb_readb = musb->ops->readb;
2080 if (musb->ops->writeb)
2081 musb_writeb = musb->ops->writeb;
2082 if (musb->ops->readw)
2083 musb_readw = musb->ops->readw;
2084 if (musb->ops->writew)
2085 musb_writew = musb->ops->writew;
2086 if (musb->ops->readl)
2087 musb_readl = musb->ops->readl;
2088 if (musb->ops->writel)
2089 musb_writel = musb->ops->writel;
2091 #ifndef CONFIG_MUSB_PIO_ONLY
2092 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2093 dev_err(dev, "DMA controller not set\n");
2097 musb_dma_controller_create = musb->ops->dma_init;
2098 musb_dma_controller_destroy = musb->ops->dma_exit;
2101 if (musb->ops->read_fifo)
2102 musb->io.read_fifo = musb->ops->read_fifo;
2104 musb->io.read_fifo = musb_default_read_fifo;
2106 if (musb->ops->write_fifo)
2107 musb->io.write_fifo = musb->ops->write_fifo;
2109 musb->io.write_fifo = musb_default_write_fifo;
2111 if (!musb->xceiv->io_ops) {
2112 musb->xceiv->io_dev = musb->controller;
2113 musb->xceiv->io_priv = musb->mregs;
2114 musb->xceiv->io_ops = &musb_ulpi_access;
2117 pm_runtime_get_sync(musb->controller);
2119 if (use_dma && dev->dma_mask) {
2120 musb->dma_controller =
2121 musb_dma_controller_create(musb, musb->mregs);
2122 if (IS_ERR(musb->dma_controller)) {
2123 status = PTR_ERR(musb->dma_controller);
2128 /* be sure interrupts are disabled before connecting ISR */
2129 musb_platform_disable(musb);
2130 musb_generic_disable(musb);
2132 /* Init IRQ workqueue before request_irq */
2133 INIT_WORK(&musb->irq_work, musb_irq_work);
2134 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2135 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2137 /* setup musb parts of the core (especially endpoints) */
2138 status = musb_core_init(plat->config->multipoint
2139 ? MUSB_CONTROLLER_MHDRC
2140 : MUSB_CONTROLLER_HDRC, musb);
2144 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2146 /* attach to the IRQ */
2147 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2148 dev_err(dev, "request_irq %d failed!\n", nIrq);
2153 /* FIXME this handles wakeup irqs wrong */
2154 if (enable_irq_wake(nIrq) == 0) {
2156 device_init_wakeup(dev, 1);
2161 /* program PHY to use external vBus if required */
2162 if (plat->extvbus) {
2163 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2164 busctl |= MUSB_ULPI_USE_EXTVBUS;
2165 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2168 if (musb->xceiv->otg->default_a) {
2169 MUSB_HST_MODE(musb);
2170 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2172 MUSB_DEV_MODE(musb);
2173 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2176 switch (musb->port_mode) {
2177 case MUSB_PORT_MODE_HOST:
2178 status = musb_platform_set_mode(musb, MUSB_HOST);
2181 status = musb_host_setup(musb, plat->power);
2183 case MUSB_PORT_MODE_GADGET:
2184 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2187 status = musb_gadget_setup(musb);
2189 case MUSB_PORT_MODE_DUAL_ROLE:
2190 status = musb_platform_set_mode(musb, MUSB_OTG);
2193 status = musb_host_setup(musb, plat->power);
2196 status = musb_gadget_setup(musb);
2198 musb_host_cleanup(musb);
2203 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2209 status = musb_init_debugfs(musb);
2213 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2217 pm_runtime_put(musb->controller);
2220 * For why this is currently needed, see commit 3e43a0725637
2221 * ("usb: musb: core: add pm_runtime_irq_safe()")
2223 pm_runtime_irq_safe(musb->controller);
2228 musb_exit_debugfs(musb);
2231 musb_gadget_cleanup(musb);
2232 musb_host_cleanup(musb);
2235 cancel_work_sync(&musb->irq_work);
2236 cancel_delayed_work_sync(&musb->finish_resume_work);
2237 cancel_delayed_work_sync(&musb->deassert_reset_work);
2238 if (musb->dma_controller)
2239 musb_dma_controller_destroy(musb->dma_controller);
2241 pm_runtime_put_sync(musb->controller);
2245 device_init_wakeup(dev, 0);
2246 musb_platform_exit(musb);
2249 pm_runtime_disable(musb->controller);
2250 dev_err(musb->controller,
2251 "musb_init_controller failed with status %d\n", status);
2261 /*-------------------------------------------------------------------------*/
2263 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2264 * bridge to a platform device; this driver then suffices.
2266 static int musb_probe(struct platform_device *pdev)
2268 struct device *dev = &pdev->dev;
2269 int irq = platform_get_irq_byname(pdev, "mc");
2270 struct resource *iomem;
2276 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2277 base = devm_ioremap_resource(dev, iomem);
2279 return PTR_ERR(base);
2281 return musb_init_controller(dev, irq, base);
2284 static int musb_remove(struct platform_device *pdev)
2286 struct device *dev = &pdev->dev;
2287 struct musb *musb = dev_to_musb(dev);
2289 /* this gets called on rmmod.
2290 * - Host mode: host may still be active
2291 * - Peripheral mode: peripheral is deactivated (or never-activated)
2292 * - OTG mode: both roles are deactivated (or never-activated)
2294 musb_exit_debugfs(musb);
2295 musb_shutdown(pdev);
2297 if (musb->dma_controller)
2298 musb_dma_controller_destroy(musb->dma_controller);
2300 cancel_work_sync(&musb->irq_work);
2301 cancel_delayed_work_sync(&musb->finish_resume_work);
2302 cancel_delayed_work_sync(&musb->deassert_reset_work);
2304 device_init_wakeup(dev, 0);
2310 static void musb_save_context(struct musb *musb)
2313 void __iomem *musb_base = musb->mregs;
2316 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2317 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2318 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2319 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2320 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2321 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2322 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2324 for (i = 0; i < musb->config->num_eps; ++i) {
2325 struct musb_hw_ep *hw_ep;
2327 hw_ep = &musb->endpoints[i];
2335 musb_writeb(musb_base, MUSB_INDEX, i);
2336 musb->context.index_regs[i].txmaxp =
2337 musb_readw(epio, MUSB_TXMAXP);
2338 musb->context.index_regs[i].txcsr =
2339 musb_readw(epio, MUSB_TXCSR);
2340 musb->context.index_regs[i].rxmaxp =
2341 musb_readw(epio, MUSB_RXMAXP);
2342 musb->context.index_regs[i].rxcsr =
2343 musb_readw(epio, MUSB_RXCSR);
2345 if (musb->dyn_fifo) {
2346 musb->context.index_regs[i].txfifoadd =
2347 musb_read_txfifoadd(musb_base);
2348 musb->context.index_regs[i].rxfifoadd =
2349 musb_read_rxfifoadd(musb_base);
2350 musb->context.index_regs[i].txfifosz =
2351 musb_read_txfifosz(musb_base);
2352 musb->context.index_regs[i].rxfifosz =
2353 musb_read_rxfifosz(musb_base);
2356 musb->context.index_regs[i].txtype =
2357 musb_readb(epio, MUSB_TXTYPE);
2358 musb->context.index_regs[i].txinterval =
2359 musb_readb(epio, MUSB_TXINTERVAL);
2360 musb->context.index_regs[i].rxtype =
2361 musb_readb(epio, MUSB_RXTYPE);
2362 musb->context.index_regs[i].rxinterval =
2363 musb_readb(epio, MUSB_RXINTERVAL);
2365 musb->context.index_regs[i].txfunaddr =
2366 musb_read_txfunaddr(musb, i);
2367 musb->context.index_regs[i].txhubaddr =
2368 musb_read_txhubaddr(musb, i);
2369 musb->context.index_regs[i].txhubport =
2370 musb_read_txhubport(musb, i);
2372 musb->context.index_regs[i].rxfunaddr =
2373 musb_read_rxfunaddr(musb, i);
2374 musb->context.index_regs[i].rxhubaddr =
2375 musb_read_rxhubaddr(musb, i);
2376 musb->context.index_regs[i].rxhubport =
2377 musb_read_rxhubport(musb, i);
2381 static void musb_restore_context(struct musb *musb)
2384 void __iomem *musb_base = musb->mregs;
2388 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2389 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2390 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2392 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2393 power = musb_readb(musb_base, MUSB_POWER);
2394 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2395 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2396 power |= musb->context.power;
2397 musb_writeb(musb_base, MUSB_POWER, power);
2399 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2400 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2401 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2402 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2404 for (i = 0; i < musb->config->num_eps; ++i) {
2405 struct musb_hw_ep *hw_ep;
2407 hw_ep = &musb->endpoints[i];
2415 musb_writeb(musb_base, MUSB_INDEX, i);
2416 musb_writew(epio, MUSB_TXMAXP,
2417 musb->context.index_regs[i].txmaxp);
2418 musb_writew(epio, MUSB_TXCSR,
2419 musb->context.index_regs[i].txcsr);
2420 musb_writew(epio, MUSB_RXMAXP,
2421 musb->context.index_regs[i].rxmaxp);
2422 musb_writew(epio, MUSB_RXCSR,
2423 musb->context.index_regs[i].rxcsr);
2425 if (musb->dyn_fifo) {
2426 musb_write_txfifosz(musb_base,
2427 musb->context.index_regs[i].txfifosz);
2428 musb_write_rxfifosz(musb_base,
2429 musb->context.index_regs[i].rxfifosz);
2430 musb_write_txfifoadd(musb_base,
2431 musb->context.index_regs[i].txfifoadd);
2432 musb_write_rxfifoadd(musb_base,
2433 musb->context.index_regs[i].rxfifoadd);
2436 musb_writeb(epio, MUSB_TXTYPE,
2437 musb->context.index_regs[i].txtype);
2438 musb_writeb(epio, MUSB_TXINTERVAL,
2439 musb->context.index_regs[i].txinterval);
2440 musb_writeb(epio, MUSB_RXTYPE,
2441 musb->context.index_regs[i].rxtype);
2442 musb_writeb(epio, MUSB_RXINTERVAL,
2444 musb->context.index_regs[i].rxinterval);
2445 musb_write_txfunaddr(musb, i,
2446 musb->context.index_regs[i].txfunaddr);
2447 musb_write_txhubaddr(musb, i,
2448 musb->context.index_regs[i].txhubaddr);
2449 musb_write_txhubport(musb, i,
2450 musb->context.index_regs[i].txhubport);
2452 musb_write_rxfunaddr(musb, i,
2453 musb->context.index_regs[i].rxfunaddr);
2454 musb_write_rxhubaddr(musb, i,
2455 musb->context.index_regs[i].rxhubaddr);
2456 musb_write_rxhubport(musb, i,
2457 musb->context.index_regs[i].rxhubport);
2459 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2462 static int musb_suspend(struct device *dev)
2464 struct musb *musb = dev_to_musb(dev);
2465 unsigned long flags;
2467 musb_platform_disable(musb);
2468 musb_generic_disable(musb);
2470 spin_lock_irqsave(&musb->lock, flags);
2472 if (is_peripheral_active(musb)) {
2473 /* FIXME force disconnect unless we know USB will wake
2474 * the system up quickly enough to respond ...
2476 } else if (is_host_active(musb)) {
2477 /* we know all the children are suspended; sometimes
2478 * they will even be wakeup-enabled.
2482 musb_save_context(musb);
2484 spin_unlock_irqrestore(&musb->lock, flags);
2488 static int musb_resume(struct device *dev)
2490 struct musb *musb = dev_to_musb(dev);
2495 * For static cmos like DaVinci, register values were preserved
2496 * unless for some reason the whole soc powered down or the USB
2497 * module got reset through the PSC (vs just being disabled).
2499 * For the DSPS glue layer though, a full register restore has to
2500 * be done. As it shouldn't harm other platforms, we do it
2504 musb_restore_context(musb);
2506 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2507 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2508 if ((devctl & mask) != (musb->context.devctl & mask))
2509 musb->port1_status = 0;
2510 if (musb->need_finish_resume) {
2511 musb->need_finish_resume = 0;
2512 schedule_delayed_work(&musb->finish_resume_work,
2513 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2517 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2520 pm_runtime_disable(dev);
2521 pm_runtime_set_active(dev);
2522 pm_runtime_enable(dev);
2529 static int musb_runtime_suspend(struct device *dev)
2531 struct musb *musb = dev_to_musb(dev);
2533 musb_save_context(musb);
2538 static int musb_runtime_resume(struct device *dev)
2540 struct musb *musb = dev_to_musb(dev);
2541 static int first = 1;
2544 * When pm_runtime_get_sync called for the first time in driver
2545 * init, some of the structure is still not initialized which is
2546 * used in restore function. But clock needs to be
2547 * enabled before any register access, so
2548 * pm_runtime_get_sync has to be called.
2549 * Also context restore without save does not make
2553 musb_restore_context(musb);
2556 if (musb->need_finish_resume) {
2557 musb->need_finish_resume = 0;
2558 schedule_delayed_work(&musb->finish_resume_work,
2559 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2565 static const struct dev_pm_ops musb_dev_pm_ops = {
2566 .suspend = musb_suspend,
2567 .resume = musb_resume,
2568 .runtime_suspend = musb_runtime_suspend,
2569 .runtime_resume = musb_runtime_resume,
2572 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2574 #define MUSB_DEV_PM_OPS NULL
2577 static struct platform_driver musb_driver = {
2579 .name = (char *)musb_driver_name,
2580 .bus = &platform_bus_type,
2581 .pm = MUSB_DEV_PM_OPS,
2583 .probe = musb_probe,
2584 .remove = musb_remove,
2585 .shutdown = musb_shutdown,
2588 module_platform_driver(musb_driver);