drivers/usb/phy/phy-msm-usb.c

   1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15  * 02110-1301, USA.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/gpio/consumer.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/clk.h>
  24 #include <linux/slab.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/err.h>
  27 #include <linux/delay.h>
  28 #include <linux/io.h>
  29 #include <linux/ioport.h>
  30 #include <linux/uaccess.h>
  31 #include <linux/debugfs.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/of.h>
  35 #include <linux/of_device.h>
  36 #include <linux/reboot.h>
  37 #include <linux/reset.h>
  38
  39 #include <linux/usb.h>
  40 #include <linux/usb/otg.h>
  41 #include <linux/usb/of.h>
  42 #include <linux/usb/ulpi.h>
  43 #include <linux/usb/gadget.h>
  44 #include <linux/usb/hcd.h>
  45 #include <linux/usb/msm_hsusb.h>
  46 #include <linux/usb/msm_hsusb_hw.h>
  47 #include <linux/regulator/consumer.h>
  48 #include <linux/msm-bus.h>
  49
  50 #define MSM_USB_BASE    (motg->regs)
  51 #define DRIVER_NAME     "msm_otg"
  52
  53 #define ULPI_IO_TIMEOUT_USEC    (10 * 1000)
  54 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
  55
  56 #define USB_PHY_3P3_VOL_MIN     3050000 /* uV */
  57 #define USB_PHY_3P3_VOL_MAX     3300000 /* uV */
  58 #define USB_PHY_3P3_HPM_LOAD    50000   /* uA */
  59 #define USB_PHY_3P3_LPM_LOAD    4000    /* uA */
  60
  61 #define USB_PHY_1P8_VOL_MIN     1800000 /* uV */
  62 #define USB_PHY_1P8_VOL_MAX     1800000 /* uV */
  63 #define USB_PHY_1P8_HPM_LOAD    50000   /* uA */
  64 #define USB_PHY_1P8_LPM_LOAD    4000    /* uA */
  65
  66 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
  67 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
  68 #define USB_PHY_SUSP_DIG_VOL    500000  /* uV */
  69
  70 enum vdd_levels {
  71         VDD_LEVEL_NONE = 0,
  72         VDD_LEVEL_MIN,
  73         VDD_LEVEL_MAX,
  74 };
  75
  76 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
  77 {
  78         int ret = 0;
  79
  80         if (IS_ERR(motg->vddcx))
  81                 return 0;
  82
  83         if (init) {
  84                 ret = regulator_set_voltage(motg->vddcx,
  85                                 motg->vdd_levels[VDD_LEVEL_MIN],
  86                                 motg->vdd_levels[VDD_LEVEL_MAX]);
  87                 if (ret) {
  88                         dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
  89                         return ret;
  90                 }
  91
  92                 ret = regulator_enable(motg->vddcx);
  93                 if (ret)
  94                         dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
  95         } else {
  96                 ret = regulator_set_voltage(motg->vddcx, 0,
  97                                 motg->vdd_levels[VDD_LEVEL_MAX]);
  98                 if (ret)
  99                         dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
 100                 ret = regulator_disable(motg->vddcx);
 101                 if (ret)
 102                         dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
 103         }
 104
 105         return ret;
 106 }
 107
 108 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
 109 {
 110         int rc = 0;
 111
 112         if (init) {
 113                 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
 114                                 USB_PHY_3P3_VOL_MAX);
 115                 if (rc) {
 116                         dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n");
 117                         goto exit;
 118                 }
 119                 rc = regulator_enable(motg->v3p3);
 120                 if (rc) {
 121                         dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
 122                         goto exit;
 123                 }
 124                 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
 125                                 USB_PHY_1P8_VOL_MAX);
 126                 if (rc) {
 127                         dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n");
 128                         goto disable_3p3;
 129                 }
 130                 rc = regulator_enable(motg->v1p8);
 131                 if (rc) {
 132                         dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
 133                         goto disable_3p3;
 134                 }
 135
 136                 return 0;
 137         }
 138
 139         regulator_disable(motg->v1p8);
 140 disable_3p3:
 141         regulator_disable(motg->v3p3);
 142 exit:
 143         return rc;
 144 }
 145
 146 static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
 147 {
 148         int ret = 0;
 149
 150         if (on) {
 151                 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_HPM_LOAD);
 152                 if (ret < 0) {
 153                         pr_err("Could not set HPM for v1p8\n");
 154                         return ret;
 155                 }
 156                 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_HPM_LOAD);
 157                 if (ret < 0) {
 158                         pr_err("Could not set HPM for v3p3\n");
 159                         regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
 160                         return ret;
 161                 }
 162         } else {
 163                 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
 164                 if (ret < 0)
 165                         pr_err("Could not set LPM for v1p8\n");
 166                 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_LPM_LOAD);
 167                 if (ret < 0)
 168                         pr_err("Could not set LPM for v3p3\n");
 169         }
 170
 171         pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
 172         return ret < 0 ? ret : 0;
 173 }
 174
 175 static int ulpi_read(struct usb_phy *phy, u32 reg)
 176 {
 177         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 178         int cnt = 0;
 179
 180         /* initiate read operation */
 181         writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
 182                USB_ULPI_VIEWPORT);
 183
 184         /* wait for completion */
 185         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 186                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 187                         break;
 188                 udelay(1);
 189                 cnt++;
 190         }
 191
 192         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 193                 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
 194                         readl(USB_ULPI_VIEWPORT));
 195                 return -ETIMEDOUT;
 196         }
 197         return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
 198 }
 199
 200 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
 201 {
 202         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 203         int cnt = 0;
 204
 205         /* initiate write operation */
 206         writel(ULPI_RUN | ULPI_WRITE |
 207                ULPI_ADDR(reg) | ULPI_DATA(val),
 208                USB_ULPI_VIEWPORT);
 209
 210         /* wait for completion */
 211         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 212                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 213                         break;
 214                 udelay(1);
 215                 cnt++;
 216         }
 217
 218         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 219                 dev_err(phy->dev, "ulpi_write: timeout\n");
 220                 return -ETIMEDOUT;
 221         }
 222         return 0;
 223 }
 224
 225 static struct usb_phy_io_ops msm_otg_io_ops = {
 226         .read = ulpi_read,
 227         .write = ulpi_write,
 228 };
 229
 230 static void ulpi_init(struct msm_otg *motg)
 231 {
 232         struct msm_otg_platform_data *pdata = motg->pdata;
 233         int *seq = pdata->phy_init_seq, idx;
 234         u32 addr = ULPI_EXT_VENDOR_SPECIFIC;
 235
 236         for (idx = 0; idx < pdata->phy_init_sz; idx++) {
 237                 if (seq[idx] == -1)
 238                         continue;
 239
 240                 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
 241                                 seq[idx], addr + idx);
 242                 ulpi_write(&motg->phy, seq[idx], addr + idx);
 243         }
 244 }
 245
 246 static int msm_phy_notify_disconnect(struct usb_phy *phy,
 247                                    enum usb_device_speed speed)
 248 {
 249         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 250         int val;
 251
 252         if (motg->manual_pullup) {
 253                 val = ULPI_MISC_A_VBUSVLDEXT | ULPI_MISC_A_VBUSVLDEXTSEL;
 254                 usb_phy_io_write(phy, val, ULPI_CLR(ULPI_MISC_A));
 255         }
 256
 257         /*
 258          * Put the transceiver in non-driving mode. Otherwise host
 259          * may not detect soft-disconnection.
 260          */
 261         val = ulpi_read(phy, ULPI_FUNC_CTRL);
 262         val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
 263         val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
 264         ulpi_write(phy, val, ULPI_FUNC_CTRL);
 265
 266         return 0;
 267 }
 268
 269 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
 270 {
 271         int ret;
 272
 273         if (assert)
 274                 ret = reset_control_assert(motg->link_rst);
 275         else
 276                 ret = reset_control_deassert(motg->link_rst);
 277
 278         if (ret)
 279                 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
 280                         assert ? "assert" : "deassert");
 281
 282         return ret;
 283 }
 284
 285 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
 286 {
 287         int ret = 0;
 288
 289         if (motg->phy_rst)
 290                 ret = reset_control_reset(motg->phy_rst);
 291
 292         if (ret)
 293                 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
 294
 295         return ret;
 296 }
 297
 298 static int msm_link_reset(struct msm_otg *motg)
 299 {
 300         u32 val;
 301         int ret;
 302
 303         ret = msm_otg_link_clk_reset(motg, 1);
 304         if (ret)
 305                 return ret;
 306
 307         /* wait for 1ms delay as suggested in HPG. */
 308         usleep_range(1000, 1200);
 309
 310         ret = msm_otg_link_clk_reset(motg, 0);
 311         if (ret)
 312                 return ret;
 313
 314         if (motg->phy_number)
 315                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 316
 317         /* put transceiver in serial mode as part of reset */
 318         val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
 319         writel(val | PORTSC_PTS_SERIAL, USB_PORTSC);
 320
 321         return 0;
 322 }
 323
 324 static int msm_otg_reset(struct usb_phy *phy)
 325 {
 326         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 327         int cnt = 0;
 328
 329         writel(USBCMD_RESET, USB_USBCMD);
 330         while (cnt < LINK_RESET_TIMEOUT_USEC) {
 331                 if (!(readl(USB_USBCMD) & USBCMD_RESET))
 332                         break;
 333                 udelay(1);
 334                 cnt++;
 335         }
 336         if (cnt >= LINK_RESET_TIMEOUT_USEC)
 337                 return -ETIMEDOUT;
 338
 339         /* select ULPI phy and clear other status/control bits in PORTSC */
 340         writel(PORTSC_PTS_ULPI, USB_PORTSC);
 341
 342         writel(0x0, USB_AHBBURST);
 343         writel(0x08, USB_AHBMODE);
 344
 345         if (motg->phy_number)
 346                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 347         return 0;
 348 }
 349
 350 static void msm_phy_reset(struct msm_otg *motg)
 351 {
 352         void __iomem *addr;
 353
 354         if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) {
 355                 msm_otg_phy_clk_reset(motg);
 356                 return;
 357         }
 358
 359         addr = USB_PHY_CTRL;
 360         if (motg->phy_number)
 361                 addr = USB_PHY_CTRL2;
 362
 363         /* Assert USB PHY_POR */
 364         writel(readl(addr) | PHY_POR_ASSERT, addr);
 365
 366         /*
 367          * wait for minimum 10 microseconds as suggested in HPG.
 368          * Use a slightly larger value since the exact value didn't
 369          * work 100% of the time.
 370          */
 371         udelay(12);
 372
 373         /* Deassert USB PHY_POR */
 374         writel(readl(addr) & ~PHY_POR_ASSERT, addr);
 375 }
 376
 377 static int msm_usb_reset(struct usb_phy *phy)
 378 {
 379         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 380         int ret;
 381
 382         if (!IS_ERR(motg->core_clk))
 383                 clk_prepare_enable(motg->core_clk);
 384
 385         ret = msm_link_reset(motg);
 386         if (ret) {
 387                 dev_err(phy->dev, "phy_reset failed\n");
 388                 return ret;
 389         }
 390
 391         ret = msm_otg_reset(&motg->phy);
 392         if (ret) {
 393                 dev_err(phy->dev, "link reset failed\n");
 394                 return ret;
 395         }
 396
 397         msleep(100);
 398
 399         /* Reset USB PHY after performing USB Link RESET */
 400         msm_phy_reset(motg);
 401
 402         if (!IS_ERR(motg->core_clk))
 403                 clk_disable_unprepare(motg->core_clk);
 404
 405         return 0;
 406 }
 407
 408 static int msm_phy_init(struct usb_phy *phy)
 409 {
 410         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 411         struct msm_otg_platform_data *pdata = motg->pdata;
 412         u32 val, ulpi_val = 0;
 413
 414         /* Program USB PHY Override registers. */
 415         ulpi_init(motg);
 416
 417         /*
 418          * It is recommended in HPG to reset USB PHY after programming
 419          * USB PHY Override registers.
 420          */
 421         msm_phy_reset(motg);
 422
 423         if (pdata->otg_control == OTG_PHY_CONTROL) {
 424                 val = readl(USB_OTGSC);
 425                 if (pdata->mode == USB_DR_MODE_OTG) {
 426                         ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
 427                         val |= OTGSC_IDIE | OTGSC_BSVIE;
 428                 } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) {
 429                         ulpi_val = ULPI_INT_SESS_VALID;
 430                         val |= OTGSC_BSVIE;
 431                 }
 432                 writel(val, USB_OTGSC);
 433                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
 434                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
 435         }
 436
 437         if (motg->manual_pullup) {
 438                 val = ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT;
 439                 ulpi_write(phy, val, ULPI_SET(ULPI_MISC_A));
 440
 441                 val = readl(USB_GENCONFIG_2);
 442                 val |= GENCONFIG_2_SESS_VLD_CTRL_EN;
 443                 writel(val, USB_GENCONFIG_2);
 444
 445                 val = readl(USB_USBCMD);
 446                 val |= USBCMD_SESS_VLD_CTRL;
 447                 writel(val, USB_USBCMD);
 448
 449                 val = ulpi_read(phy, ULPI_FUNC_CTRL);
 450                 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
 451                 val |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
 452                 ulpi_write(phy, val, ULPI_FUNC_CTRL);
 453         }
 454
 455         if (motg->phy_number)
 456                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 457
 458         return 0;
 459 }
 460
 461 #define PHY_SUSPEND_TIMEOUT_USEC        (500 * 1000)
 462 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
 463
 464 #ifdef CONFIG_PM
 465
 466 static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
 467 {
 468         int max_vol = motg->vdd_levels[VDD_LEVEL_MAX];
 469         int min_vol;
 470         int ret;
 471
 472         if (high)
 473                 min_vol = motg->vdd_levels[VDD_LEVEL_MIN];
 474         else
 475                 min_vol = motg->vdd_levels[VDD_LEVEL_NONE];
 476
 477         ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
 478         if (ret) {
 479                 pr_err("Cannot set vddcx voltage\n");
 480                 return ret;
 481         }
 482
 483         pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
 484
 485         return ret;
 486 }
 487
 488 static int msm_otg_suspend(struct msm_otg *motg)
 489 {
 490         struct usb_phy *phy = &motg->phy;
 491         struct usb_bus *bus = phy->otg->host;
 492         struct msm_otg_platform_data *pdata = motg->pdata;
 493         void __iomem *addr;
 494         int cnt = 0;
 495
 496         if (atomic_read(&motg->in_lpm))
 497                 return 0;
 498
 499         disable_irq(motg->irq);
 500         /*
 501          * Chipidea 45-nm PHY suspend sequence:
 502          *
 503          * Interrupt Latch Register auto-clear feature is not present
 504          * in all PHY versions. Latch register is clear on read type.
 505          * Clear latch register to avoid spurious wakeup from
 506          * low power mode (LPM).
 507          *
 508          * PHY comparators are disabled when PHY enters into low power
 509          * mode (LPM). Keep PHY comparators ON in LPM only when we expect
 510          * VBUS/Id notifications from USB PHY. Otherwise turn off USB
 511          * PHY comparators. This save significant amount of power.
 512          *
 513          * PLL is not turned off when PHY enters into low power mode (LPM).
 514          * Disable PLL for maximum power savings.
 515          */
 516
 517         if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
 518                 ulpi_read(phy, 0x14);
 519                 if (pdata->otg_control == OTG_PHY_CONTROL)
 520                         ulpi_write(phy, 0x01, 0x30);
 521                 ulpi_write(phy, 0x08, 0x09);
 522         }
 523
 524         /*
 525          * PHY may take some time or even fail to enter into low power
 526          * mode (LPM). Hence poll for 500 msec and reset the PHY and link
 527          * in failure case.
 528          */
 529         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
 530         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
 531                 if (readl(USB_PORTSC) & PORTSC_PHCD)
 532                         break;
 533                 udelay(1);
 534                 cnt++;
 535         }
 536
 537         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
 538                 dev_err(phy->dev, "Unable to suspend PHY\n");
 539                 msm_otg_reset(phy);
 540                 enable_irq(motg->irq);
 541                 return -ETIMEDOUT;
 542         }
 543
 544         /*
 545          * PHY has capability to generate interrupt asynchronously in low
 546          * power mode (LPM). This interrupt is level triggered. So USB IRQ
 547          * line must be disabled till async interrupt enable bit is cleared
 548          * in USBCMD register. Assert STP (ULPI interface STOP signal) to
 549          * block data communication from PHY.
 550          */
 551         writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
 552
 553         addr = USB_PHY_CTRL;
 554         if (motg->phy_number)
 555                 addr = USB_PHY_CTRL2;
 556
 557         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 558                         motg->pdata->otg_control == OTG_PMIC_CONTROL)
 559                 writel(readl(addr) | PHY_RETEN, addr);
 560
 561         clk_disable_unprepare(motg->pclk);
 562         clk_disable_unprepare(motg->clk);
 563         if (!IS_ERR(motg->core_clk))
 564                 clk_disable_unprepare(motg->core_clk);
 565
 566         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 567                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 568                 msm_hsusb_ldo_set_mode(motg, 0);
 569                 msm_hsusb_config_vddcx(motg, 0);
 570         }
 571
 572         if (device_may_wakeup(phy->dev))
 573                 enable_irq_wake(motg->irq);
 574         if (bus)
 575                 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 576
 577         atomic_set(&motg->in_lpm, 1);
 578         enable_irq(motg->irq);
 579
 580         dev_info(phy->dev, "USB in low power mode\n");
 581
 582         return 0;
 583 }
 584
 585 static int msm_otg_resume(struct msm_otg *motg)
 586 {
 587         struct usb_phy *phy = &motg->phy;
 588         struct usb_bus *bus = phy->otg->host;
 589         void __iomem *addr;
 590         int cnt = 0;
 591         unsigned temp;
 592
 593         if (!atomic_read(&motg->in_lpm))
 594                 return 0;
 595
 596         clk_prepare_enable(motg->pclk);
 597         clk_prepare_enable(motg->clk);
 598         if (!IS_ERR(motg->core_clk))
 599                 clk_prepare_enable(motg->core_clk);
 600
 601         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 602                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 603
 604                 addr = USB_PHY_CTRL;
 605                 if (motg->phy_number)
 606                         addr = USB_PHY_CTRL2;
 607
 608                 msm_hsusb_ldo_set_mode(motg, 1);
 609                 msm_hsusb_config_vddcx(motg, 1);
 610                 writel(readl(addr) & ~PHY_RETEN, addr);
 611         }
 612
 613         temp = readl(USB_USBCMD);
 614         temp &= ~ASYNC_INTR_CTRL;
 615         temp &= ~ULPI_STP_CTRL;
 616         writel(temp, USB_USBCMD);
 617
 618         /*
 619          * PHY comes out of low power mode (LPM) in case of wakeup
 620          * from asynchronous interrupt.
 621          */
 622         if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 623                 goto skip_phy_resume;
 624
 625         writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
 626         while (cnt < PHY_RESUME_TIMEOUT_USEC) {
 627                 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 628                         break;
 629                 udelay(1);
 630                 cnt++;
 631         }
 632
 633         if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
 634                 /*
 635                  * This is a fatal error. Reset the link and
 636                  * PHY. USB state can not be restored. Re-insertion
 637                  * of USB cable is the only way to get USB working.
 638                  */
 639                 dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n");
 640                 msm_otg_reset(phy);
 641         }
 642
 643 skip_phy_resume:
 644         if (device_may_wakeup(phy->dev))
 645                 disable_irq_wake(motg->irq);
 646         if (bus)
 647                 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 648
 649         atomic_set(&motg->in_lpm, 0);
 650
 651         if (motg->async_int) {
 652                 motg->async_int = 0;
 653                 pm_runtime_put(phy->dev);
 654                 enable_irq(motg->irq);
 655         }
 656
 657         dev_info(phy->dev, "USB exited from low power mode\n");
 658
 659         return 0;
 660 }
 661 #endif
 662
 663 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
 664 {
 665         if (motg->cur_power == mA)
 666                 return;
 667
 668         /* TODO: Notify PMIC about available current */
 669         dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
 670         motg->cur_power = mA;
 671 }
 672
 673 static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
 674 {
 675         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 676
 677         /*
 678          * Gadget driver uses set_power method to notify about the
 679          * available current based on suspend/configured states.
 680          *
 681          * IDEV_CHG can be drawn irrespective of suspend/un-configured
 682          * states when CDP/ACA is connected.
 683          */
 684         if (motg->chg_type == USB_SDP_CHARGER)
 685                 msm_otg_notify_charger(motg, mA);
 686
 687         return 0;
 688 }
 689
 690 static void msm_otg_start_host(struct usb_phy *phy, int on)
 691 {
 692         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 693         struct msm_otg_platform_data *pdata = motg->pdata;
 694         struct usb_hcd *hcd;
 695
 696         if (!phy->otg->host)
 697                 return;
 698
 699         hcd = bus_to_hcd(phy->otg->host);
 700
 701         if (on) {
 702                 dev_dbg(phy->dev, "host on\n");
 703
 704                 if (pdata->vbus_power)
 705                         pdata->vbus_power(1);
 706                 /*
 707                  * Some boards have a switch cotrolled by gpio
 708                  * to enable/disable internal HUB. Enable internal
 709                  * HUB before kicking the host.
 710                  */
 711                 if (pdata->setup_gpio)
 712                         pdata->setup_gpio(OTG_STATE_A_HOST);
 713 #ifdef CONFIG_USB
 714                 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 715                 device_wakeup_enable(hcd->self.controller);
 716 #endif
 717         } else {
 718                 dev_dbg(phy->dev, "host off\n");
 719
 720 #ifdef CONFIG_USB
 721                 usb_remove_hcd(hcd);
 722 #endif
 723                 if (pdata->setup_gpio)
 724                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 725                 if (pdata->vbus_power)
 726                         pdata->vbus_power(0);
 727         }
 728 }
 729
 730 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
 731 {
 732         struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
 733         struct usb_hcd *hcd;
 734
 735         /*
 736          * Fail host registration if this board can support
 737          * only peripheral configuration.
 738          */
 739         if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) {
 740                 dev_info(otg->usb_phy->dev, "Host mode is not supported\n");
 741                 return -ENODEV;
 742         }
 743
 744         if (!host) {
 745                 if (otg->state == OTG_STATE_A_HOST) {
 746                         pm_runtime_get_sync(otg->usb_phy->dev);
 747                         msm_otg_start_host(otg->usb_phy, 0);
 748                         otg->host = NULL;
 749                         otg->state = OTG_STATE_UNDEFINED;
 750                         schedule_work(&motg->sm_work);
 751                 } else {
 752                         otg->host = NULL;
 753                 }
 754
 755                 return 0;
 756         }
 757
 758         hcd = bus_to_hcd(host);
 759         hcd->power_budget = motg->pdata->power_budget;
 760
 761         otg->host = host;
 762         dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n");
 763
 764         /*
 765          * Kick the state machine work, if peripheral is not supported
 766          * or peripheral is already registered with us.
 767          */
 768         if (motg->pdata->mode == USB_DR_MODE_HOST ||
 769                         motg->pdata->mode == USB_DR_MODE_OTG || otg->gadget) {
 770                 pm_runtime_get_sync(otg->usb_phy->dev);
 771                 schedule_work(&motg->sm_work);
 772         }
 773
 774         return 0;
 775 }
 776
 777 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
 778 {
 779         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 780         struct msm_otg_platform_data *pdata = motg->pdata;
 781
 782         if (!phy->otg->gadget)
 783                 return;
 784
 785         if (on) {
 786                 dev_dbg(phy->dev, "gadget on\n");
 787                 /*
 788                  * Some boards have a switch cotrolled by gpio
 789                  * to enable/disable internal HUB. Disable internal
 790                  * HUB before kicking the gadget.
 791                  */
 792                 if (pdata->setup_gpio)
 793                         pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
 794                 usb_gadget_vbus_connect(phy->otg->gadget);
 795         } else {
 796                 dev_dbg(phy->dev, "gadget off\n");
 797                 usb_gadget_vbus_disconnect(phy->otg->gadget);
 798                 if (pdata->setup_gpio)
 799                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 800         }
 801
 802 }
 803
 804 static int msm_otg_set_peripheral(struct usb_otg *otg,
 805                                         struct usb_gadget *gadget)
 806 {
 807         struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
 808
 809         /*
 810          * Fail peripheral registration if this board can support
 811          * only host configuration.
 812          */
 813         if (motg->pdata->mode == USB_DR_MODE_HOST) {
 814                 dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n");
 815                 return -ENODEV;
 816         }
 817
 818         if (!gadget) {
 819                 if (otg->state == OTG_STATE_B_PERIPHERAL) {
 820                         pm_runtime_get_sync(otg->usb_phy->dev);
 821                         msm_otg_start_peripheral(otg->usb_phy, 0);
 822                         otg->gadget = NULL;
 823                         otg->state = OTG_STATE_UNDEFINED;
 824                         schedule_work(&motg->sm_work);
 825                 } else {
 826                         otg->gadget = NULL;
 827                 }
 828
 829                 return 0;
 830         }
 831         otg->gadget = gadget;
 832         dev_dbg(otg->usb_phy->dev,
 833                 "peripheral driver registered w/ tranceiver\n");
 834
 835         /*
 836          * Kick the state machine work, if host is not supported
 837          * or host is already registered with us.
 838          */
 839         if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL ||
 840                 motg->pdata->mode == USB_DR_MODE_OTG || otg->host) {
 841                 pm_runtime_get_sync(otg->usb_phy->dev);
 842                 schedule_work(&motg->sm_work);
 843         }
 844
 845         return 0;
 846 }
 847
 848 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
 849 {
 850         struct usb_phy *phy = &motg->phy;
 851         u32 chg_det;
 852         bool ret = false;
 853
 854         switch (motg->pdata->phy_type) {
 855         case CI_45NM_INTEGRATED_PHY:
 856                 chg_det = ulpi_read(phy, 0x34);
 857                 ret = chg_det & (1 << 4);
 858                 break;
 859         case SNPS_28NM_INTEGRATED_PHY:
 860                 chg_det = ulpi_read(phy, 0x87);
 861                 ret = chg_det & 1;
 862                 break;
 863         default:
 864                 break;
 865         }
 866         return ret;
 867 }
 868
 869 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
 870 {
 871         struct usb_phy *phy = &motg->phy;
 872         u32 chg_det;
 873
 874         switch (motg->pdata->phy_type) {
 875         case CI_45NM_INTEGRATED_PHY:
 876                 chg_det = ulpi_read(phy, 0x34);
 877                 /* Turn off charger block */
 878                 chg_det |= ~(1 << 1);
 879                 ulpi_write(phy, chg_det, 0x34);
 880                 udelay(20);
 881                 /* control chg block via ULPI */
 882                 chg_det &= ~(1 << 3);
 883                 ulpi_write(phy, chg_det, 0x34);
 884                 /* put it in host mode for enabling D- source */
 885                 chg_det &= ~(1 << 2);
 886                 ulpi_write(phy, chg_det, 0x34);
 887                 /* Turn on chg detect block */
 888                 chg_det &= ~(1 << 1);
 889                 ulpi_write(phy, chg_det, 0x34);
 890                 udelay(20);
 891                 /* enable chg detection */
 892                 chg_det &= ~(1 << 0);
 893                 ulpi_write(phy, chg_det, 0x34);
 894                 break;
 895         case SNPS_28NM_INTEGRATED_PHY:
 896                 /*
 897                  * Configure DM as current source, DP as current sink
 898                  * and enable battery charging comparators.
 899                  */
 900                 ulpi_write(phy, 0x8, 0x85);
 901                 ulpi_write(phy, 0x2, 0x85);
 902                 ulpi_write(phy, 0x1, 0x85);
 903                 break;
 904         default:
 905                 break;
 906         }
 907 }
 908
 909 static bool msm_chg_check_primary_det(struct msm_otg *motg)
 910 {
 911         struct usb_phy *phy = &motg->phy;
 912         u32 chg_det;
 913         bool ret = false;
 914
 915         switch (motg->pdata->phy_type) {
 916         case CI_45NM_INTEGRATED_PHY:
 917                 chg_det = ulpi_read(phy, 0x34);
 918                 ret = chg_det & (1 << 4);
 919                 break;
 920         case SNPS_28NM_INTEGRATED_PHY:
 921                 chg_det = ulpi_read(phy, 0x87);
 922                 ret = chg_det & 1;
 923                 break;
 924         default:
 925                 break;
 926         }
 927         return ret;
 928 }
 929
 930 static void msm_chg_enable_primary_det(struct msm_otg *motg)
 931 {
 932         struct usb_phy *phy = &motg->phy;
 933         u32 chg_det;
 934
 935         switch (motg->pdata->phy_type) {
 936         case CI_45NM_INTEGRATED_PHY:
 937                 chg_det = ulpi_read(phy, 0x34);
 938                 /* enable chg detection */
 939                 chg_det &= ~(1 << 0);
 940                 ulpi_write(phy, chg_det, 0x34);
 941                 break;
 942         case SNPS_28NM_INTEGRATED_PHY:
 943                 /*
 944                  * Configure DP as current source, DM as current sink
 945                  * and enable battery charging comparators.
 946                  */
 947                 ulpi_write(phy, 0x2, 0x85);
 948                 ulpi_write(phy, 0x1, 0x85);
 949                 break;
 950         default:
 951                 break;
 952         }
 953 }
 954
 955 static bool msm_chg_check_dcd(struct msm_otg *motg)
 956 {
 957         struct usb_phy *phy = &motg->phy;
 958         u32 line_state;
 959         bool ret = false;
 960
 961         switch (motg->pdata->phy_type) {
 962         case CI_45NM_INTEGRATED_PHY:
 963                 line_state = ulpi_read(phy, 0x15);
 964                 ret = !(line_state & 1);
 965                 break;
 966         case SNPS_28NM_INTEGRATED_PHY:
 967                 line_state = ulpi_read(phy, 0x87);
 968                 ret = line_state & 2;
 969                 break;
 970         default:
 971                 break;
 972         }
 973         return ret;
 974 }
 975
 976 static void msm_chg_disable_dcd(struct msm_otg *motg)
 977 {
 978         struct usb_phy *phy = &motg->phy;
 979         u32 chg_det;
 980
 981         switch (motg->pdata->phy_type) {
 982         case CI_45NM_INTEGRATED_PHY:
 983                 chg_det = ulpi_read(phy, 0x34);
 984                 chg_det &= ~(1 << 5);
 985                 ulpi_write(phy, chg_det, 0x34);
 986                 break;
 987         case SNPS_28NM_INTEGRATED_PHY:
 988                 ulpi_write(phy, 0x10, 0x86);
 989                 break;
 990         default:
 991                 break;
 992         }
 993 }
 994
 995 static void msm_chg_enable_dcd(struct msm_otg *motg)
 996 {
 997         struct usb_phy *phy = &motg->phy;
 998         u32 chg_det;
 999
1000         switch (motg->pdata->phy_type) {
1001         case CI_45NM_INTEGRATED_PHY:
1002                 chg_det = ulpi_read(phy, 0x34);
1003                 /* Turn on D+ current source */
1004                 chg_det |= (1 << 5);
1005                 ulpi_write(phy, chg_det, 0x34);
1006                 break;
1007         case SNPS_28NM_INTEGRATED_PHY:
1008                 /* Data contact detection enable */
1009                 ulpi_write(phy, 0x10, 0x85);
1010                 break;
1011         default:
1012                 break;
1013         }
1014 }
1015
1016 static void msm_chg_block_on(struct msm_otg *motg)
1017 {
1018         struct usb_phy *phy = &motg->phy;
1019         u32 func_ctrl, chg_det;
1020
1021         /* put the controller in non-driving mode */
1022         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1023         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1024         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
1025         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1026
1027         switch (motg->pdata->phy_type) {
1028         case CI_45NM_INTEGRATED_PHY:
1029                 chg_det = ulpi_read(phy, 0x34);
1030                 /* control chg block via ULPI */
1031                 chg_det &= ~(1 << 3);
1032                 ulpi_write(phy, chg_det, 0x34);
1033                 /* Turn on chg detect block */
1034                 chg_det &= ~(1 << 1);
1035                 ulpi_write(phy, chg_det, 0x34);
1036                 udelay(20);
1037                 break;
1038         case SNPS_28NM_INTEGRATED_PHY:
1039                 /* Clear charger detecting control bits */
1040                 ulpi_write(phy, 0x3F, 0x86);
1041                 /* Clear alt interrupt latch and enable bits */
1042                 ulpi_write(phy, 0x1F, 0x92);
1043                 ulpi_write(phy, 0x1F, 0x95);
1044                 udelay(100);
1045                 break;
1046         default:
1047                 break;
1048         }
1049 }
1050
1051 static void msm_chg_block_off(struct msm_otg *motg)
1052 {
1053         struct usb_phy *phy = &motg->phy;
1054         u32 func_ctrl, chg_det;
1055
1056         switch (motg->pdata->phy_type) {
1057         case CI_45NM_INTEGRATED_PHY:
1058                 chg_det = ulpi_read(phy, 0x34);
1059                 /* Turn off charger block */
1060                 chg_det |= ~(1 << 1);
1061                 ulpi_write(phy, chg_det, 0x34);
1062                 break;
1063         case SNPS_28NM_INTEGRATED_PHY:
1064                 /* Clear charger detecting control bits */
1065                 ulpi_write(phy, 0x3F, 0x86);
1066                 /* Clear alt interrupt latch and enable bits */
1067                 ulpi_write(phy, 0x1F, 0x92);
1068                 ulpi_write(phy, 0x1F, 0x95);
1069                 break;
1070         default:
1071                 break;
1072         }
1073
1074         /* put the controller in normal mode */
1075         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1076         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1077         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1078         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1079 }
1080
1081 #define MSM_CHG_DCD_POLL_TIME           (100 * HZ/1000) /* 100 msec */
1082 #define MSM_CHG_DCD_MAX_RETRIES         6 /* Tdcd_tmout = 6 * 100 msec */
1083 #define MSM_CHG_PRIMARY_DET_TIME        (40 * HZ/1000) /* TVDPSRC_ON */
1084 #define MSM_CHG_SECONDARY_DET_TIME      (40 * HZ/1000) /* TVDMSRC_ON */
1085 static void msm_chg_detect_work(struct work_struct *w)
1086 {
1087         struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1088         struct usb_phy *phy = &motg->phy;
1089         bool is_dcd, tmout, vout;
1090         unsigned long delay;
1091
1092         dev_dbg(phy->dev, "chg detection work\n");
1093         switch (motg->chg_state) {
1094         case USB_CHG_STATE_UNDEFINED:
1095                 pm_runtime_get_sync(phy->dev);
1096                 msm_chg_block_on(motg);
1097                 msm_chg_enable_dcd(motg);
1098                 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1099                 motg->dcd_retries = 0;
1100                 delay = MSM_CHG_DCD_POLL_TIME;
1101                 break;
1102         case USB_CHG_STATE_WAIT_FOR_DCD:
1103                 is_dcd = msm_chg_check_dcd(motg);
1104                 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1105                 if (is_dcd || tmout) {
1106                         msm_chg_disable_dcd(motg);
1107                         msm_chg_enable_primary_det(motg);
1108                         delay = MSM_CHG_PRIMARY_DET_TIME;
1109                         motg->chg_state = USB_CHG_STATE_DCD_DONE;
1110                 } else {
1111                         delay = MSM_CHG_DCD_POLL_TIME;
1112                 }
1113                 break;
1114         case USB_CHG_STATE_DCD_DONE:
1115                 vout = msm_chg_check_primary_det(motg);
1116                 if (vout) {
1117                         msm_chg_enable_secondary_det(motg);
1118                         delay = MSM_CHG_SECONDARY_DET_TIME;
1119                         motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1120                 } else {
1121                         motg->chg_type = USB_SDP_CHARGER;
1122                         motg->chg_state = USB_CHG_STATE_DETECTED;
1123                         delay = 0;
1124                 }
1125                 break;
1126         case USB_CHG_STATE_PRIMARY_DONE:
1127                 vout = msm_chg_check_secondary_det(motg);
1128                 if (vout)
1129                         motg->chg_type = USB_DCP_CHARGER;
1130                 else
1131                         motg->chg_type = USB_CDP_CHARGER;
1132                 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1133                 /* fall through */
1134         case USB_CHG_STATE_SECONDARY_DONE:
1135                 motg->chg_state = USB_CHG_STATE_DETECTED;
1136         case USB_CHG_STATE_DETECTED:
1137                 msm_chg_block_off(motg);
1138                 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1139                 schedule_work(&motg->sm_work);
1140                 return;
1141         default:
1142                 return;
1143         }
1144
1145         schedule_delayed_work(&motg->chg_work, delay);
1146 }
1147
1148 /*
1149  * We support OTG, Peripheral only and Host only configurations. In case
1150  * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1151  * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1152  * enabled when switch is controlled by user and default mode is supplied
1153  * by board file, which can be changed by userspace later.
1154  */
1155 static void msm_otg_init_sm(struct msm_otg *motg)
1156 {
1157         struct msm_otg_platform_data *pdata = motg->pdata;
1158         u32 otgsc = readl(USB_OTGSC);
1159
1160         switch (pdata->mode) {
1161         case USB_DR_MODE_OTG:
1162                 if (pdata->otg_control == OTG_PHY_CONTROL) {
1163                         if (otgsc & OTGSC_ID)
1164                                 set_bit(ID, &motg->inputs);
1165                         else
1166                                 clear_bit(ID, &motg->inputs);
1167
1168                         if (otgsc & OTGSC_BSV)
1169                                 set_bit(B_SESS_VLD, &motg->inputs);
1170                         else
1171                                 clear_bit(B_SESS_VLD, &motg->inputs);
1172                 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1173                                 set_bit(ID, &motg->inputs);
1174                                 clear_bit(B_SESS_VLD, &motg->inputs);
1175                 }
1176                 break;
1177         case USB_DR_MODE_HOST:
1178                 clear_bit(ID, &motg->inputs);
1179                 break;
1180         case USB_DR_MODE_PERIPHERAL:
1181                 set_bit(ID, &motg->inputs);
1182                 if (otgsc & OTGSC_BSV)
1183                         set_bit(B_SESS_VLD, &motg->inputs);
1184                 else
1185                         clear_bit(B_SESS_VLD, &motg->inputs);
1186                 break;
1187         default:
1188                 break;
1189         }
1190 }
1191
1192 static void msm_otg_sm_work(struct work_struct *w)
1193 {
1194         struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1195         struct usb_otg *otg = motg->phy.otg;
1196
1197         switch (otg->state) {
1198         case OTG_STATE_UNDEFINED:
1199                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_UNDEFINED state\n");
1200                 msm_otg_reset(otg->usb_phy);
1201                 msm_otg_init_sm(motg);
1202                 otg->state = OTG_STATE_B_IDLE;
1203                 /* FALL THROUGH */
1204         case OTG_STATE_B_IDLE:
1205                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_IDLE state\n");
1206                 if (!test_bit(ID, &motg->inputs) && otg->host) {
1207                         /* disable BSV bit */
1208                         writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1209                         msm_otg_start_host(otg->usb_phy, 1);
1210                         otg->state = OTG_STATE_A_HOST;
1211                 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1212                         switch (motg->chg_state) {
1213                         case USB_CHG_STATE_UNDEFINED:
1214                                 msm_chg_detect_work(&motg->chg_work.work);
1215                                 break;
1216                         case USB_CHG_STATE_DETECTED:
1217                                 switch (motg->chg_type) {
1218                                 case USB_DCP_CHARGER:
1219                                         msm_otg_notify_charger(motg,
1220                                                         IDEV_CHG_MAX);
1221                                         break;
1222                                 case USB_CDP_CHARGER:
1223                                         msm_otg_notify_charger(motg,
1224                                                         IDEV_CHG_MAX);
1225                                         msm_otg_start_peripheral(otg->usb_phy,
1226                                                                  1);
1227                                         otg->state
1228                                                 = OTG_STATE_B_PERIPHERAL;
1229                                         break;
1230                                 case USB_SDP_CHARGER:
1231                                         msm_otg_notify_charger(motg, IUNIT);
1232                                         msm_otg_start_peripheral(otg->usb_phy,
1233                                                                  1);
1234                                         otg->state
1235                                                 = OTG_STATE_B_PERIPHERAL;
1236                                         break;
1237                                 default:
1238                                         break;
1239                                 }
1240                                 break;
1241                         default:
1242                                 break;
1243                         }
1244                 } else {
1245                         /*
1246                          * If charger detection work is pending, decrement
1247                          * the pm usage counter to balance with the one that
1248                          * is incremented in charger detection work.
1249                          */
1250                         if (cancel_delayed_work_sync(&motg->chg_work)) {
1251                                 pm_runtime_put_sync(otg->usb_phy->dev);
1252                                 msm_otg_reset(otg->usb_phy);
1253                         }
1254                         msm_otg_notify_charger(motg, 0);
1255                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1256                         motg->chg_type = USB_INVALID_CHARGER;
1257                 }
1258
1259                 if (otg->state == OTG_STATE_B_IDLE)
1260                         pm_runtime_put_sync(otg->usb_phy->dev);
1261                 break;
1262         case OTG_STATE_B_PERIPHERAL:
1263                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1264                 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1265                                 !test_bit(ID, &motg->inputs)) {
1266                         msm_otg_notify_charger(motg, 0);
1267                         msm_otg_start_peripheral(otg->usb_phy, 0);
1268                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1269                         motg->chg_type = USB_INVALID_CHARGER;
1270                         otg->state = OTG_STATE_B_IDLE;
1271                         msm_otg_reset(otg->usb_phy);
1272                         schedule_work(w);
1273                 }
1274                 break;
1275         case OTG_STATE_A_HOST:
1276                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_A_HOST state\n");
1277                 if (test_bit(ID, &motg->inputs)) {
1278                         msm_otg_start_host(otg->usb_phy, 0);
1279                         otg->state = OTG_STATE_B_IDLE;
1280                         msm_otg_reset(otg->usb_phy);
1281                         schedule_work(w);
1282                 }
1283                 break;
1284         default:
1285                 break;
1286         }
1287 }
1288
1289 static irqreturn_t msm_otg_irq(int irq, void *data)
1290 {
1291         struct msm_otg *motg = data;
1292         struct usb_phy *phy = &motg->phy;
1293         u32 otgsc = 0;
1294
1295         if (atomic_read(&motg->in_lpm)) {
1296                 disable_irq_nosync(irq);
1297                 motg->async_int = 1;
1298                 pm_runtime_get(phy->dev);
1299                 return IRQ_HANDLED;
1300         }
1301
1302         otgsc = readl(USB_OTGSC);
1303         if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1304                 return IRQ_NONE;
1305
1306         if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1307                 if (otgsc & OTGSC_ID)
1308                         set_bit(ID, &motg->inputs);
1309                 else
1310                         clear_bit(ID, &motg->inputs);
1311                 dev_dbg(phy->dev, "ID set/clear\n");
1312                 pm_runtime_get_noresume(phy->dev);
1313         } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1314                 if (otgsc & OTGSC_BSV)
1315                         set_bit(B_SESS_VLD, &motg->inputs);
1316                 else
1317                         clear_bit(B_SESS_VLD, &motg->inputs);
1318                 dev_dbg(phy->dev, "BSV set/clear\n");
1319                 pm_runtime_get_noresume(phy->dev);
1320         }
1321
1322         writel(otgsc, USB_OTGSC);
1323         schedule_work(&motg->sm_work);
1324         return IRQ_HANDLED;
1325 }
1326
1327 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1328 {
1329         struct msm_otg *motg = s->private;
1330         struct usb_otg *otg = motg->phy.otg;
1331
1332         switch (otg->state) {
1333         case OTG_STATE_A_HOST:
1334                 seq_puts(s, "host\n");
1335                 break;
1336         case OTG_STATE_B_PERIPHERAL:
1337                 seq_puts(s, "peripheral\n");
1338                 break;
1339         default:
1340                 seq_puts(s, "none\n");
1341                 break;
1342         }
1343
1344         return 0;
1345 }
1346
1347 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1348 {
1349         return single_open(file, msm_otg_mode_show, inode->i_private);
1350 }
1351
1352 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1353                                 size_t count, loff_t *ppos)
1354 {
1355         struct seq_file *s = file->private_data;
1356         struct msm_otg *motg = s->private;
1357         char buf[16];
1358         struct usb_otg *otg = motg->phy.otg;
1359         int status = count;
1360         enum usb_dr_mode req_mode;
1361
1362         memset(buf, 0x00, sizeof(buf));
1363
1364         if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1365                 status = -EFAULT;
1366                 goto out;
1367         }
1368
1369         if (!strncmp(buf, "host", 4)) {
1370                 req_mode = USB_DR_MODE_HOST;
1371         } else if (!strncmp(buf, "peripheral", 10)) {
1372                 req_mode = USB_DR_MODE_PERIPHERAL;
1373         } else if (!strncmp(buf, "none", 4)) {
1374                 req_mode = USB_DR_MODE_UNKNOWN;
1375         } else {
1376                 status = -EINVAL;
1377                 goto out;
1378         }
1379
1380         switch (req_mode) {
1381         case USB_DR_MODE_UNKNOWN:
1382                 switch (otg->state) {
1383                 case OTG_STATE_A_HOST:
1384                 case OTG_STATE_B_PERIPHERAL:
1385                         set_bit(ID, &motg->inputs);
1386                         clear_bit(B_SESS_VLD, &motg->inputs);
1387                         break;
1388                 default:
1389                         goto out;
1390                 }
1391                 break;
1392         case USB_DR_MODE_PERIPHERAL:
1393                 switch (otg->state) {
1394                 case OTG_STATE_B_IDLE:
1395                 case OTG_STATE_A_HOST:
1396                         set_bit(ID, &motg->inputs);
1397                         set_bit(B_SESS_VLD, &motg->inputs);
1398                         break;
1399                 default:
1400                         goto out;
1401                 }
1402                 break;
1403         case USB_DR_MODE_HOST:
1404                 switch (otg->state) {
1405                 case OTG_STATE_B_IDLE:
1406                 case OTG_STATE_B_PERIPHERAL:
1407                         clear_bit(ID, &motg->inputs);
1408                         break;
1409                 default:
1410                         goto out;
1411                 }
1412                 break;
1413         default:
1414                 goto out;
1415         }
1416
1417         pm_runtime_get_sync(otg->usb_phy->dev);
1418         schedule_work(&motg->sm_work);
1419 out:
1420         return status;
1421 }
1422
1423 static const struct file_operations msm_otg_mode_fops = {
1424         .open = msm_otg_mode_open,
1425         .read = seq_read,
1426         .write = msm_otg_mode_write,
1427         .llseek = seq_lseek,
1428         .release = single_release,
1429 };
1430
1431 static struct dentry *msm_otg_dbg_root;
1432 static struct dentry *msm_otg_dbg_mode;
1433
1434 static int msm_otg_debugfs_init(struct msm_otg *motg)
1435 {
1436         msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1437
1438         if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1439                 return -ENODEV;
1440
1441         msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1442                                 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1443         if (!msm_otg_dbg_mode) {
1444                 debugfs_remove(msm_otg_dbg_root);
1445                 msm_otg_dbg_root = NULL;
1446                 return -ENODEV;
1447         }
1448
1449         return 0;
1450 }
1451
1452 static void msm_otg_debugfs_cleanup(void)
1453 {
1454         debugfs_remove(msm_otg_dbg_mode);
1455         debugfs_remove(msm_otg_dbg_root);
1456 }
1457
1458 static const struct of_device_id msm_otg_dt_match[] = {
1459         {
1460                 .compatible = "qcom,usb-otg-ci",
1461                 .data = (void *) CI_45NM_INTEGRATED_PHY
1462         },
1463         {
1464                 .compatible = "qcom,usb-otg-snps",
1465                 .data = (void *) SNPS_28NM_INTEGRATED_PHY
1466         },
1467         { }
1468 };
1469 MODULE_DEVICE_TABLE(of, msm_otg_dt_match);
1470
1471 static int msm_otg_vbus_notifier(struct notifier_block *nb, unsigned long event,
1472                                 void *ptr)
1473 {
1474         struct msm_usb_cable *vbus = container_of(nb, struct msm_usb_cable, nb);
1475         struct msm_otg *motg = container_of(vbus, struct msm_otg, vbus);
1476
1477         if (event)
1478                 set_bit(B_SESS_VLD, &motg->inputs);
1479         else
1480                 clear_bit(B_SESS_VLD, &motg->inputs);
1481
1482         if (test_bit(B_SESS_VLD, &motg->inputs)) {
1483                 /* Switch D+/D- lines to Device connector */
1484                 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1485         } else {
1486                 /* Switch D+/D- lines to Hub */
1487                 gpiod_set_value_cansleep(motg->switch_gpio, 1);
1488         }
1489
1490         schedule_work(&motg->sm_work);
1491
1492         return NOTIFY_DONE;
1493 }
1494
1495 static int msm_otg_id_notifier(struct notifier_block *nb, unsigned long event,
1496                                 void *ptr)
1497 {
1498         struct msm_usb_cable *id = container_of(nb, struct msm_usb_cable, nb);
1499         struct msm_otg *motg = container_of(id, struct msm_otg, id);
1500
1501         if (event)
1502                 clear_bit(ID, &motg->inputs);
1503         else
1504                 set_bit(ID, &motg->inputs);
1505
1506         schedule_work(&motg->sm_work);
1507
1508         return NOTIFY_DONE;
1509 }
1510
1511 static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
1512 {
1513         struct msm_otg_platform_data *pdata;
1514         struct extcon_dev *ext_id, *ext_vbus;
1515         struct device_node *node = pdev->dev.of_node;
1516         struct property *prop;
1517         int len, ret, words;
1518         u32 val, tmp[3];
1519
1520         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1521         if (!pdata)
1522                 return -ENOMEM;
1523
1524         motg->pdata = pdata;
1525
1526         pdata->phy_type = (enum msm_usb_phy_type)of_device_get_match_data(&pdev->dev);
1527         if (!pdata->phy_type)
1528                 return 1;
1529
1530         motg->link_rst = devm_reset_control_get(&pdev->dev, "link");
1531         if (IS_ERR(motg->link_rst))
1532                 return PTR_ERR(motg->link_rst);
1533
1534         motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy");
1535         if (IS_ERR(motg->phy_rst))
1536                 motg->phy_rst = NULL;
1537
1538         pdata->mode = usb_get_dr_mode(&pdev->dev);
1539         if (pdata->mode == USB_DR_MODE_UNKNOWN)
1540                 pdata->mode = USB_DR_MODE_OTG;
1541
1542         pdata->otg_control = OTG_PHY_CONTROL;
1543         if (!of_property_read_u32(node, "qcom,otg-control", &val))
1544                 if (val == OTG_PMIC_CONTROL)
1545                         pdata->otg_control = val;
1546
1547         if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2)
1548                 motg->phy_number = val;
1549
1550         motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL;
1551         motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN;
1552         motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX;
1553
1554         if (of_get_property(node, "qcom,vdd-levels", &len) &&
1555             len == sizeof(tmp)) {
1556                 of_property_read_u32_array(node, "qcom,vdd-levels",
1557                                            tmp, len / sizeof(*tmp));
1558                 motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE];
1559                 motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN];
1560                 motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
1561         }
1562
1563         motg->manual_pullup = of_property_read_bool(node, "qcom,manual-pullup");
1564
1565         motg->switch_gpio = devm_gpiod_get_optional(&pdev->dev, "switch",
1566                                                     GPIOD_OUT_LOW);
1567         if (IS_ERR(motg->switch_gpio))
1568                 return PTR_ERR(motg->switch_gpio);
1569
1570         ext_id = ERR_PTR(-ENODEV);
1571         ext_vbus = ERR_PTR(-ENODEV);
1572         if (of_property_read_bool(node, "extcon")) {
1573
1574                 /* Each one of them is not mandatory */
1575                 ext_vbus = extcon_get_edev_by_phandle(&pdev->dev, 0);
1576                 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
1577                         return PTR_ERR(ext_vbus);
1578
1579                 ext_id = extcon_get_edev_by_phandle(&pdev->dev, 1);
1580                 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
1581                         return PTR_ERR(ext_id);
1582         }
1583
1584         if (!IS_ERR(ext_vbus)) {
1585                 motg->vbus.extcon = ext_vbus;
1586                 motg->vbus.nb.notifier_call = msm_otg_vbus_notifier;
1587                 ret = extcon_register_notifier(ext_vbus, EXTCON_USB,
1588                                                 &motg->vbus.nb);
1589                 if (ret < 0) {
1590                         dev_err(&pdev->dev, "register VBUS notifier failed\n");
1591                         return ret;
1592                 }
1593
1594                 ret = extcon_get_cable_state_(ext_vbus, EXTCON_USB);
1595                 if (ret)
1596                         set_bit(B_SESS_VLD, &motg->inputs);
1597                 else
1598                         clear_bit(B_SESS_VLD, &motg->inputs);
1599         }
1600
1601         if (!IS_ERR(ext_id)) {
1602                 motg->id.extcon = ext_id;
1603                 motg->id.nb.notifier_call = msm_otg_id_notifier;
1604                 ret = extcon_register_notifier(ext_id, EXTCON_USB_HOST,
1605                                                 &motg->id.nb);
1606                 if (ret < 0) {
1607                         dev_err(&pdev->dev, "register ID notifier failed\n");
1608                         extcon_unregister_notifier(motg->vbus.extcon,
1609                                                    EXTCON_USB, &motg->vbus.nb);
1610                         return ret;
1611                 }
1612
1613                 ret = extcon_get_cable_state_(ext_id, EXTCON_USB_HOST);
1614                 if (ret)
1615                         clear_bit(ID, &motg->inputs);
1616                 else
1617                         set_bit(ID, &motg->inputs);
1618         }
1619
1620         prop = of_find_property(node, "qcom,phy-init-sequence", &len);
1621         if (!prop || !len)
1622                 return 0;
1623
1624         words = len / sizeof(u32);
1625
1626         if (words >= ULPI_EXT_VENDOR_SPECIFIC) {
1627                 dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words);
1628                 return 0;
1629         }
1630
1631         pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1632         if (!pdata->phy_init_seq)
1633                 return 0;
1634
1635         ret = of_property_read_u32_array(node, "qcom,phy-init-sequence",
1636                                          pdata->phy_init_seq, words);
1637         if (!ret)
1638                 pdata->phy_init_sz = words;
1639
1640         return 0;
1641 }
1642
1643 static int msm_otg_reboot_notify(struct notifier_block *this,
1644                                  unsigned long code, void *unused)
1645 {
1646         struct msm_otg *motg = container_of(this, struct msm_otg, reboot);
1647
1648         /*
1649          * Ensure that D+/D- lines are routed to uB connector, so
1650          * we could load bootloader/kernel at next reboot
1651          */
1652         gpiod_set_value_cansleep(motg->switch_gpio, 0);
1653         return NOTIFY_DONE;
1654 }
1655
1656 static void msm_otg_bus_vote(struct msm_otg *motg, enum usb_bus_vote vote)
1657 {
1658         int ret;
1659
1660         if (motg->bus_perf_client) {
1661                 ret = msm_bus_scale_client_update_request(
1662                                 motg->bus_perf_client, vote);
1663                 if (ret)
1664                         dev_err(motg->phy.dev, "%s: Failed to vote (%d)\n"
1665                                         "for bus bw %d\n", __func__, vote, ret);
1666         }
1667 }
1668
1669 static int msm_otg_probe(struct platform_device *pdev)
1670 {
1671         struct regulator_bulk_data regs[2];
1672         int ret = 0;
1673         struct device_node *np = pdev->dev.of_node;
1674         struct msm_otg_platform_data *pdata;
1675         struct resource *res;
1676         struct msm_otg *motg;
1677         struct usb_phy *phy;
1678         void __iomem *phy_select;
1679
1680         motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1681         if (!motg)
1682                 return -ENOMEM;
1683
1684         motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1685                                      GFP_KERNEL);
1686         if (!motg->phy.otg)
1687                 return -ENOMEM;
1688
1689         phy = &motg->phy;
1690         phy->dev = &pdev->dev;
1691         INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1692         INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1693
1694         motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk");
1695         if (IS_ERR(motg->clk)) {
1696                 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1697                 return PTR_ERR(motg->clk);
1698         }
1699
1700         /*
1701          * If USB Core is running its protocol engine based on CORE CLK,
1702          * CORE CLK  must be running at >55Mhz for correct HSUSB
1703          * operation and USB core cannot tolerate frequency changes on
1704          * CORE CLK.
1705          */
1706         motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk");
1707         if (IS_ERR(motg->pclk)) {
1708                 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1709                 return PTR_ERR(motg->pclk);
1710         }
1711
1712         /*
1713          * USB core clock is not present on all MSM chips. This
1714          * clock is introduced to remove the dependency on AXI
1715          * bus frequency.
1716          */
1717         motg->core_clk = devm_clk_get(&pdev->dev,
1718                                       np ? "alt_core" : "usb_hs_core_clk");
1719
1720         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1721         if (!res)
1722                 return -EINVAL;
1723         motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1724         if (!motg->regs)
1725                 return -ENOMEM;
1726
1727         pdata = dev_get_platdata(&pdev->dev);
1728         if (!pdata) {
1729                 if (!np)
1730                         return -ENXIO;
1731                 ret = msm_otg_read_dt(pdev, motg);
1732                 if (ret)
1733                         return ret;
1734         }
1735
1736         /*
1737          * NOTE: The PHYs can be multiplexed between the chipidea controller
1738          * and the dwc3 controller, using a single bit. It is important that
1739          * the dwc3 driver does not set this bit in an incompatible way.
1740          */
1741         if (motg->phy_number) {
1742                 phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
1743                 if (!phy_select) {
1744                         ret = -ENOMEM;
1745                         goto unregister_extcon;
1746                 }
1747                 /* Enable second PHY with the OTG port */
1748                 writel(0x1, phy_select);
1749         }
1750
1751         dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1752
1753         motg->irq = platform_get_irq(pdev, 0);
1754         if (motg->irq < 0) {
1755                 dev_err(&pdev->dev, "platform_get_irq failed\n");
1756                 ret = motg->irq;
1757                 goto unregister_extcon;
1758         }
1759
1760         regs[0].supply = "v3p3";
1761         regs[1].supply = "v1p8";
1762
1763         ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs);
1764         if (ret) {
1765                 dev_err(&pdev->dev, "no v3p3 or v1p8\n");
1766                 goto unregister_extcon;
1767         }
1768
1769         motg->v3p3  = regs[0].consumer;
1770         motg->v1p8  = regs[1].consumer;
1771
1772         motg->vddcx = devm_regulator_get_optional(motg->phy.dev, "vddcx");
1773         if (IS_ERR(motg->vddcx))
1774                 dev_info(&pdev->dev, "no vddcx\n");
1775
1776         clk_set_rate(motg->clk, 60000000);
1777
1778         clk_prepare_enable(motg->clk);
1779         clk_prepare_enable(motg->pclk);
1780
1781         if (!IS_ERR(motg->core_clk))
1782                 clk_prepare_enable(motg->core_clk);
1783
1784         ret = msm_hsusb_init_vddcx(motg, 1);
1785         if (ret) {
1786                 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1787                 goto disable_clks;
1788         }
1789
1790         ret = msm_hsusb_ldo_init(motg, 1);
1791         if (ret) {
1792                 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1793                 goto disable_vddcx;
1794         }
1795         ret = msm_hsusb_ldo_set_mode(motg, 1);
1796         if (ret) {
1797                 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1798                 goto disable_ldo;
1799         }
1800
1801         writel(0, USB_USBINTR);
1802         writel(0, USB_OTGSC);
1803
1804         ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
1805                                         "msm_otg", motg);
1806         if (ret) {
1807                 dev_err(&pdev->dev, "request irq failed\n");
1808                 goto disable_ldo;
1809         }
1810
1811         phy->init = msm_phy_init;
1812         phy->set_power = msm_otg_set_power;
1813         phy->notify_disconnect = msm_phy_notify_disconnect;
1814         phy->type = USB_PHY_TYPE_USB2;
1815
1816         phy->io_ops = &msm_otg_io_ops;
1817
1818         phy->otg->usb_phy = &motg->phy;
1819         phy->otg->set_host = msm_otg_set_host;
1820         phy->otg->set_peripheral = msm_otg_set_peripheral;
1821
1822         msm_usb_reset(phy);
1823
1824         ret = usb_add_phy_dev(&motg->phy);
1825         if (ret) {
1826                 dev_err(&pdev->dev, "usb_add_phy failed\n");
1827                 goto disable_ldo;
1828         }
1829
1830         motg->pdata->bus_scale_table = msm_bus_cl_get_pdata(pdev);
1831         if (!motg->pdata->bus_scale_table)
1832                 dev_dbg(&pdev->dev, "bus scaling is disabled\n");
1833         else {
1834                 motg->bus_perf_client =
1835                         msm_bus_scale_register_client(motg->pdata->bus_scale_table);
1836                 if (!motg->bus_perf_client)
1837                         dev_err(motg->phy.dev, "%s: Failed to register BUS\n"
1838                                         "scaling client!!\n", __func__);
1839         }
1840         /* Hack to max out usb performace */
1841         msm_otg_bus_vote(motg, USB_MAX_PERF_VOTE);
1842
1843         platform_set_drvdata(pdev, motg);
1844         device_init_wakeup(&pdev->dev, 1);
1845
1846         if (motg->pdata->mode == USB_DR_MODE_OTG &&
1847                 motg->pdata->otg_control == OTG_USER_CONTROL) {
1848                 ret = msm_otg_debugfs_init(motg);
1849                 if (ret)
1850                         dev_dbg(&pdev->dev, "Can not create mode change file\n");
1851         }
1852
1853         if (test_bit(B_SESS_VLD, &motg->inputs)) {
1854                 /* Switch D+/D- lines to Device connector */
1855                 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1856         } else {
1857                 /* Switch D+/D- lines to Hub */
1858                 gpiod_set_value_cansleep(motg->switch_gpio, 1);
1859         }
1860
1861         motg->reboot.notifier_call = msm_otg_reboot_notify;
1862         register_reboot_notifier(&motg->reboot);
1863
1864         pm_runtime_set_active(&pdev->dev);
1865
1866         return 0;
1867
1868 disable_ldo:
1869         msm_hsusb_ldo_init(motg, 0);
1870 disable_vddcx:
1871         msm_hsusb_init_vddcx(motg, 0);
1872 disable_clks:
1873         clk_disable_unprepare(motg->pclk);
1874         clk_disable_unprepare(motg->clk);
1875         if (!IS_ERR(motg->core_clk))
1876                 clk_disable_unprepare(motg->core_clk);
1877 unregister_extcon:
1878         extcon_unregister_notifier(motg->id.extcon,
1879                                    EXTCON_USB_HOST, &motg->id.nb);
1880         extcon_unregister_notifier(motg->vbus.extcon,
1881                                    EXTCON_USB, &motg->vbus.nb);
1882
1883         return ret;
1884 }
1885
1886 static int msm_otg_remove(struct platform_device *pdev)
1887 {
1888         struct msm_otg *motg = platform_get_drvdata(pdev);
1889         struct usb_phy *phy = &motg->phy;
1890         int cnt = 0;
1891
1892         if (phy->otg->host || phy->otg->gadget)
1893                 return -EBUSY;
1894
1895         unregister_reboot_notifier(&motg->reboot);
1896
1897         /*
1898          * Ensure that D+/D- lines are routed to uB connector, so
1899          * we could load bootloader/kernel at next reboot
1900          */
1901         gpiod_set_value_cansleep(motg->switch_gpio, 0);
1902
1903         extcon_unregister_notifier(motg->id.extcon, EXTCON_USB_HOST, &motg->id.nb);
1904         extcon_unregister_notifier(motg->vbus.extcon, EXTCON_USB, &motg->vbus.nb);
1905
1906         msm_otg_debugfs_cleanup();
1907         cancel_delayed_work_sync(&motg->chg_work);
1908         cancel_work_sync(&motg->sm_work);
1909
1910         pm_runtime_resume(&pdev->dev);
1911
1912         device_init_wakeup(&pdev->dev, 0);
1913         pm_runtime_disable(&pdev->dev);
1914
1915         usb_remove_phy(phy);
1916         disable_irq(motg->irq);
1917         msm_bus_scale_unregister_client(motg->bus_perf_client);
1918
1919         /*
1920          * Put PHY in low power mode.
1921          */
1922         ulpi_read(phy, 0x14);
1923         ulpi_write(phy, 0x08, 0x09);
1924
1925         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1926         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1927                 if (readl(USB_PORTSC) & PORTSC_PHCD)
1928                         break;
1929                 udelay(1);
1930                 cnt++;
1931         }
1932         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1933                 dev_err(phy->dev, "Unable to suspend PHY\n");
1934
1935         clk_disable_unprepare(motg->pclk);
1936         clk_disable_unprepare(motg->clk);
1937         if (!IS_ERR(motg->core_clk))
1938                 clk_disable_unprepare(motg->core_clk);
1939         msm_hsusb_ldo_init(motg, 0);
1940
1941         pm_runtime_set_suspended(&pdev->dev);
1942
1943         return 0;
1944 }
1945
1946 #ifdef CONFIG_PM
1947 static int msm_otg_runtime_idle(struct device *dev)
1948 {
1949         struct msm_otg *motg = dev_get_drvdata(dev);
1950         struct usb_otg *otg = motg->phy.otg;
1951
1952         dev_dbg(dev, "OTG runtime idle\n");
1953
1954         /*
1955          * It is observed some times that a spurious interrupt
1956          * comes when PHY is put into LPM immediately after PHY reset.
1957          * This 1 sec delay also prevents entering into LPM immediately
1958          * after asynchronous interrupt.
1959          */
1960         if (otg->state != OTG_STATE_UNDEFINED)
1961                 pm_schedule_suspend(dev, 1000);
1962
1963         return -EAGAIN;
1964 }
1965
1966 static int msm_otg_runtime_suspend(struct device *dev)
1967 {
1968         struct msm_otg *motg = dev_get_drvdata(dev);
1969
1970         dev_dbg(dev, "OTG runtime suspend\n");
1971         return msm_otg_suspend(motg);
1972 }
1973
1974 static int msm_otg_runtime_resume(struct device *dev)
1975 {
1976         struct msm_otg *motg = dev_get_drvdata(dev);
1977
1978         dev_dbg(dev, "OTG runtime resume\n");
1979         return msm_otg_resume(motg);
1980 }
1981 #endif
1982
1983 #ifdef CONFIG_PM_SLEEP
1984 static int msm_otg_pm_suspend(struct device *dev)
1985 {
1986         struct msm_otg *motg = dev_get_drvdata(dev);
1987
1988         dev_dbg(dev, "OTG PM suspend\n");
1989         return msm_otg_suspend(motg);
1990 }
1991
1992 static int msm_otg_pm_resume(struct device *dev)
1993 {
1994         struct msm_otg *motg = dev_get_drvdata(dev);
1995         int ret;
1996
1997         dev_dbg(dev, "OTG PM resume\n");
1998
1999         ret = msm_otg_resume(motg);
2000         if (ret)
2001                 return ret;
2002
2003         /*
2004          * Runtime PM Documentation recommends bringing the
2005          * device to full powered state upon resume.
2006          */
2007         pm_runtime_disable(dev);
2008         pm_runtime_set_active(dev);
2009         pm_runtime_enable(dev);
2010
2011         return 0;
2012 }
2013 #endif
2014
2015 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
2016         SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
2017         SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
2018                                 msm_otg_runtime_idle)
2019 };
2020
2021 static struct platform_driver msm_otg_driver = {
2022         .probe = msm_otg_probe,
2023         .remove = msm_otg_remove,
2024         .driver = {
2025                 .name = DRIVER_NAME,
2026                 .pm = &msm_otg_dev_pm_ops,
2027                 .of_match_table = msm_otg_dt_match,
2028         },
2029 };
2030
2031 module_platform_driver(msm_otg_driver);
2032
2033 MODULE_LICENSE("GPL v2");
2034 MODULE_DESCRIPTION("MSM USB transceiver driver");