drivers/video/fbdev/mxsfb.c

   1 /*
   2  * Copyright (C) 2010 Juergen Beisert, Pengutronix
   3  *
   4  * This code is based on:
   5  * Author: Vitaly Wool <vital@embeddedalley.com>
   6  *
   7  * Copyright 2008-2014 Freescale Semiconductor, Inc. All Rights Reserved.
   8  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version 2
  13  * of the License, or (at your option) any later version.
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #define DRIVER_NAME "mxsfb"
  21
  22 /**
  23  * @file
  24  * @brief LCDIF driver for i.MX23 and i.MX28
  25  *
  26  * The LCDIF support four modes of operation
  27  * - MPU interface (to drive smart displays) -> not supported yet
  28  * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet
  29  * - Dotclock interface (to drive LC displays with RGB data and sync signals)
  30  * - DVI (to drive ITU-R BT656)  -> not supported yet
  31  *
  32  * This driver depends on a correct setup of the pins used for this purpose
  33  * (platform specific).
  34  *
  35  * For the developer: Don't forget to set the data bus width to the display
  36  * in the imx_fb_videomode structure. You will else end up with ugly colours.
  37  * If you fight against jitter you can vary the clock delay. This is a feature
  38  * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give
  39  * the required value in the imx_fb_videomode structure.
  40  */
  41
  42 #include <linux/module.h>
  43 #include <linux/kernel.h>
  44 #include <linux/of_device.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/clk.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/io.h>
  49 #include <linux/fb.h>
  50 #include <linux/regulator/consumer.h>
  51 #include <video/of_display_timing.h>
  52 #include <video/of_videomode.h>
  53 #include <video/videomode.h>
  54
  55 #define REG_SET 4
  56 #define REG_CLR 8
  57
  58 #define LCDC_CTRL                       0x00
  59 #define LCDC_CTRL1                      0x10
  60 #define LCDC_V4_CTRL2                   0x20
  61 #define LCDC_V3_TRANSFER_COUNT          0x20
  62 #define LCDC_V4_TRANSFER_COUNT          0x30
  63 #define LCDC_V4_CUR_BUF                 0x40
  64 #define LCDC_V4_NEXT_BUF                0x50
  65 #define LCDC_V3_CUR_BUF                 0x30
  66 #define LCDC_V3_NEXT_BUF                0x40
  67 #define LCDC_TIMING                     0x60
  68 #define LCDC_VDCTRL0                    0x70
  69 #define LCDC_VDCTRL1                    0x80
  70 #define LCDC_VDCTRL2                    0x90
  71 #define LCDC_VDCTRL3                    0xa0
  72 #define LCDC_VDCTRL4                    0xb0
  73 #define LCDC_DVICTRL0                   0xc0
  74 #define LCDC_DVICTRL1                   0xd0
  75 #define LCDC_DVICTRL2                   0xe0
  76 #define LCDC_DVICTRL3                   0xf0
  77 #define LCDC_DVICTRL4                   0x100
  78 #define LCDC_V4_DATA                    0x180
  79 #define LCDC_V3_DATA                    0x1b0
  80 #define LCDC_V4_DEBUG0                  0x1d0
  81 #define LCDC_V3_DEBUG0                  0x1f0
  82
  83 #define CTRL_SFTRST                     (1 << 31)
  84 #define CTRL_CLKGATE                    (1 << 30)
  85 #define CTRL_BYPASS_COUNT               (1 << 19)
  86 #define CTRL_VSYNC_MODE                 (1 << 18)
  87 #define CTRL_DOTCLK_MODE                (1 << 17)
  88 #define CTRL_DATA_SELECT                (1 << 16)
  89 #define CTRL_SET_BUS_WIDTH(x)           (((x) & 0x3) << 10)
  90 #define CTRL_GET_BUS_WIDTH(x)           (((x) >> 10) & 0x3)
  91 #define CTRL_SET_WORD_LENGTH(x)         (((x) & 0x3) << 8)
  92 #define CTRL_GET_WORD_LENGTH(x)         (((x) >> 8) & 0x3)
  93 #define CTRL_MASTER                     (1 << 5)
  94 #define CTRL_DF16                       (1 << 3)
  95 #define CTRL_DF18                       (1 << 2)
  96 #define CTRL_DF24                       (1 << 1)
  97 #define CTRL_RUN                        (1 << 0)
  98
  99 #define CTRL1_FIFO_CLEAR                (1 << 21)
 100 #define CTRL1_SET_BYTE_PACKAGING(x)     (((x) & 0xf) << 16)
 101 #define CTRL1_GET_BYTE_PACKAGING(x)     (((x) >> 16) & 0xf)
 102
 103 #define TRANSFER_COUNT_SET_VCOUNT(x)    (((x) & 0xffff) << 16)
 104 #define TRANSFER_COUNT_GET_VCOUNT(x)    (((x) >> 16) & 0xffff)
 105 #define TRANSFER_COUNT_SET_HCOUNT(x)    ((x) & 0xffff)
 106 #define TRANSFER_COUNT_GET_HCOUNT(x)    ((x) & 0xffff)
 107
 108
 109 #define VDCTRL0_ENABLE_PRESENT          (1 << 28)
 110 #define VDCTRL0_VSYNC_ACT_HIGH          (1 << 27)
 111 #define VDCTRL0_HSYNC_ACT_HIGH          (1 << 26)
 112 #define VDCTRL0_DOTCLK_ACT_FALLING      (1 << 25)
 113 #define VDCTRL0_ENABLE_ACT_HIGH         (1 << 24)
 114 #define VDCTRL0_VSYNC_PERIOD_UNIT       (1 << 21)
 115 #define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT  (1 << 20)
 116 #define VDCTRL0_HALF_LINE               (1 << 19)
 117 #define VDCTRL0_HALF_LINE_MODE          (1 << 18)
 118 #define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
 119 #define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
 120
 121 #define VDCTRL2_SET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
 122 #define VDCTRL2_GET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
 123
 124 #define VDCTRL3_MUX_SYNC_SIGNALS        (1 << 29)
 125 #define VDCTRL3_VSYNC_ONLY              (1 << 28)
 126 #define SET_HOR_WAIT_CNT(x)             (((x) & 0xfff) << 16)
 127 #define GET_HOR_WAIT_CNT(x)             (((x) >> 16) & 0xfff)
 128 #define SET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
 129 #define GET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
 130
 131 #define VDCTRL4_SET_DOTCLK_DLY(x)       (((x) & 0x7) << 29) /* v4 only */
 132 #define VDCTRL4_GET_DOTCLK_DLY(x)       (((x) >> 29) & 0x7) /* v4 only */
 133 #define VDCTRL4_SYNC_SIGNALS_ON         (1 << 18)
 134 #define SET_DOTCLK_H_VALID_DATA_CNT(x)  ((x) & 0x3ffff)
 135
 136 #define DEBUG0_HSYNC                    (1 < 26)
 137 #define DEBUG0_VSYNC                    (1 < 25)
 138
 139 #define MIN_XRES                        120
 140 #define MIN_YRES                        120
 141
 142 #define RED 0
 143 #define GREEN 1
 144 #define BLUE 2
 145 #define TRANSP 3
 146
 147 #define STMLCDIF_8BIT  1 /** pixel data bus to the display is of 8 bit width */
 148 #define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
 149 #define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
 150 #define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
 151
 152 #define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
 153 #define MXSFB_SYNC_DOTCLK_FALLING_ACT   (1 << 7) /* negtive edge sampling */
 154
 155 enum mxsfb_devtype {
 156         MXSFB_V3,
 157         MXSFB_V4,
 158 };
 159
 160 /* CPU dependent register offsets */
 161 struct mxsfb_devdata {
 162         unsigned transfer_count;
 163         unsigned cur_buf;
 164         unsigned next_buf;
 165         unsigned debug0;
 166         unsigned hs_wdth_mask;
 167         unsigned hs_wdth_shift;
 168         unsigned ipversion;
 169 };
 170
 171 struct mxsfb_info {
 172         struct fb_info fb_info;
 173         struct platform_device *pdev;
 174         struct clk *clk_pix;
 175         struct clk *clk_axi;
 176         bool clk_axi_enabled;
 177         void __iomem *base;     /* registers */
 178         unsigned allocated_size;
 179         int enabled;
 180         unsigned ld_intf_width;
 181         unsigned dotclk_delay;
 182         const struct mxsfb_devdata *devdata;
 183         u32 sync;
 184         struct regulator *reg_lcd;
 185 };
 186
 187 #define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
 188 #define mxsfb_is_v4(host) (host->devdata->ipversion == 4)
 189
 190 static const struct mxsfb_devdata mxsfb_devdata[] = {
 191         [MXSFB_V3] = {
 192                 .transfer_count = LCDC_V3_TRANSFER_COUNT,
 193                 .cur_buf = LCDC_V3_CUR_BUF,
 194                 .next_buf = LCDC_V3_NEXT_BUF,
 195                 .debug0 = LCDC_V3_DEBUG0,
 196                 .hs_wdth_mask = 0xff,
 197                 .hs_wdth_shift = 24,
 198                 .ipversion = 3,
 199         },
 200         [MXSFB_V4] = {
 201                 .transfer_count = LCDC_V4_TRANSFER_COUNT,
 202                 .cur_buf = LCDC_V4_CUR_BUF,
 203                 .next_buf = LCDC_V4_NEXT_BUF,
 204                 .debug0 = LCDC_V4_DEBUG0,
 205                 .hs_wdth_mask = 0x3fff,
 206                 .hs_wdth_shift = 18,
 207                 .ipversion = 4,
 208         },
 209 };
 210
 211 #define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info))
 212
 213 /* enable lcdif axi clock */
 214 static inline void clk_enable_axi(struct mxsfb_info *host)
 215 {
 216         if (!host->clk_axi_enabled && host &&
 217                 host->clk_axi && !IS_ERR(host->clk_axi)) {
 218                 clk_prepare_enable(host->clk_axi);
 219                 host->clk_axi_enabled = true;
 220         }
 221 }
 222
 223 /* disable lcdif axi clock */
 224 static inline void clk_disable_axi(struct mxsfb_info *host)
 225 {
 226         if (host->clk_axi_enabled && host &&
 227                 host->clk_axi && !IS_ERR(host->clk_axi)) {
 228                 clk_disable_unprepare(host->clk_axi);
 229                 host->clk_axi_enabled = false;
 230         }
 231 }
 232
 233 /* mask and shift depends on architecture */
 234 static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
 235 {
 236         return (val & host->devdata->hs_wdth_mask) <<
 237                 host->devdata->hs_wdth_shift;
 238 }
 239
 240 static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
 241 {
 242         return (val >> host->devdata->hs_wdth_shift) &
 243                 host->devdata->hs_wdth_mask;
 244 }
 245
 246 static const struct fb_bitfield def_rgb565[] = {
 247         [RED] = {
 248                 .offset = 11,
 249                 .length = 5,
 250         },
 251         [GREEN] = {
 252                 .offset = 5,
 253                 .length = 6,
 254         },
 255         [BLUE] = {
 256                 .offset = 0,
 257                 .length = 5,
 258         },
 259         [TRANSP] = {    /* no support for transparency */
 260                 .length = 0,
 261         }
 262 };
 263
 264 static const struct fb_bitfield def_rgb888[] = {
 265         [RED] = {
 266                 .offset = 16,
 267                 .length = 8,
 268         },
 269         [GREEN] = {
 270                 .offset = 8,
 271                 .length = 8,
 272         },
 273         [BLUE] = {
 274                 .offset = 0,
 275                 .length = 8,
 276         },
 277         [TRANSP] = {    /* no support for transparency */
 278                 .length = 0,
 279         }
 280 };
 281
 282 static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf)
 283 {
 284         chan &= 0xffff;
 285         chan >>= 16 - bf->length;
 286         return chan << bf->offset;
 287 }
 288
 289 static int mxsfb_check_var(struct fb_var_screeninfo *var,
 290                 struct fb_info *fb_info)
 291 {
 292         struct mxsfb_info *host = to_imxfb_host(fb_info);
 293         const struct fb_bitfield *rgb = NULL;
 294
 295         if (var->xres < MIN_XRES)
 296                 var->xres = MIN_XRES;
 297         if (var->yres < MIN_YRES)
 298                 var->yres = MIN_YRES;
 299
 300         var->xres_virtual = var->xres;
 301
 302         var->yres_virtual = var->yres;
 303
 304         switch (var->bits_per_pixel) {
 305         case 16:
 306                 /* always expect RGB 565 */
 307                 rgb = def_rgb565;
 308                 break;
 309         case 32:
 310                 switch (host->ld_intf_width) {
 311                 case STMLCDIF_8BIT:
 312                         pr_debug("Unsupported LCD bus width mapping\n");
 313                         break;
 314                 case STMLCDIF_16BIT:
 315                 case STMLCDIF_18BIT:
 316                 case STMLCDIF_24BIT:
 317                         /* real 24 bit */
 318                         rgb = def_rgb888;
 319                         break;
 320                 }
 321                 break;
 322         default:
 323                 pr_err("Unsupported colour depth: %u\n", var->bits_per_pixel);
 324                 return -EINVAL;
 325         }
 326
 327         /*
 328          * Copy the RGB parameters for this display
 329          * from the machine specific parameters.
 330          */
 331         var->red    = rgb[RED];
 332         var->green  = rgb[GREEN];
 333         var->blue   = rgb[BLUE];
 334         var->transp = rgb[TRANSP];
 335
 336         return 0;
 337 }
 338
 339 static void mxsfb_enable_controller(struct fb_info *fb_info)
 340 {
 341         struct mxsfb_info *host = to_imxfb_host(fb_info);
 342         u32 reg;
 343         int ret;
 344
 345         dev_dbg(&host->pdev->dev, "%s\n", __func__);
 346
 347         if (host->reg_lcd) {
 348                 ret = regulator_enable(host->reg_lcd);
 349                 if (ret) {
 350                         dev_err(&host->pdev->dev,
 351                                 "lcd regulator enable failed:   %d\n", ret);
 352                         return;
 353                 }
 354         }
 355
 356         clk_enable_axi(host);
 357
 358         clk_prepare_enable(host->clk_pix);
 359         clk_set_rate(host->clk_pix, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
 360
 361         /* Clean soft reset and clock gate bit if it was enabled  */
 362         writel(CTRL_SFTRST | CTRL_CLKGATE, host->base + LCDC_CTRL + REG_CLR);
 363
 364         /* if it was disabled, re-enable the mode again */
 365         writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
 366
 367         /* enable the SYNC signals first, then the DMA engine */
 368         reg = readl(host->base + LCDC_VDCTRL4);
 369         reg |= VDCTRL4_SYNC_SIGNALS_ON;
 370         writel(reg, host->base + LCDC_VDCTRL4);
 371
 372         writel(CTRL_MASTER, host->base + LCDC_CTRL + REG_SET);
 373         writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
 374
 375         host->enabled = 1;
 376 }
 377
 378 static void mxsfb_disable_controller(struct fb_info *fb_info)
 379 {
 380         struct mxsfb_info *host = to_imxfb_host(fb_info);
 381         unsigned loop;
 382         u32 reg;
 383         int ret;
 384
 385         dev_dbg(&host->pdev->dev, "%s\n", __func__);
 386
 387         clk_enable_axi(host);
 388         /*
 389          * Even if we disable the controller here, it will still continue
 390          * until its FIFOs are running out of data
 391          */
 392         writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR);
 393
 394         loop = 1000;
 395         while (loop) {
 396                 reg = readl(host->base + LCDC_CTRL);
 397                 if (!(reg & CTRL_RUN))
 398                         break;
 399                 loop--;
 400         }
 401
 402         writel(CTRL_MASTER, host->base + LCDC_CTRL + REG_CLR);
 403
 404         reg = readl(host->base + LCDC_VDCTRL4);
 405         writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4);
 406
 407         clk_disable_unprepare(host->clk_pix);
 408
 409         host->enabled = 0;
 410
 411         if (host->reg_lcd) {
 412                 ret = regulator_disable(host->reg_lcd);
 413                 if (ret)
 414                         dev_err(&host->pdev->dev,
 415                                 "lcd regulator disable failed: %d\n", ret);
 416         }
 417 }
 418
 419 static int mxsfb_set_par(struct fb_info *fb_info)
 420 {
 421         struct mxsfb_info *host = to_imxfb_host(fb_info);
 422         u32 ctrl, vdctrl0, vdctrl4;
 423         int line_size, fb_size;
 424         int reenable = 0;
 425
 426         clk_enable_axi(host);
 427
 428         line_size =  fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
 429         fb_size = fb_info->var.yres_virtual * line_size;
 430
 431         if (fb_size > fb_info->fix.smem_len)
 432                 return -ENOMEM;
 433
 434         fb_info->fix.line_length = line_size;
 435
 436         /*
 437          * It seems, you can't re-program the controller if it is still running.
 438          * This may lead into shifted pictures (FIFO issue?).
 439          * So, first stop the controller and drain its FIFOs
 440          */
 441         if (host->enabled) {
 442                 reenable = 1;
 443                 mxsfb_disable_controller(fb_info);
 444         }
 445
 446         /* clear the FIFOs */
 447         writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
 448
 449         ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER |
 450                 CTRL_SET_BUS_WIDTH(host->ld_intf_width);
 451
 452         switch (fb_info->var.bits_per_pixel) {
 453         case 16:
 454                 dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n");
 455                 ctrl |= CTRL_SET_WORD_LENGTH(0);
 456                 writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1);
 457                 break;
 458         case 32:
 459                 dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
 460                 ctrl |= CTRL_SET_WORD_LENGTH(3);
 461                 switch (host->ld_intf_width) {
 462                 case STMLCDIF_8BIT:
 463                         dev_err(&host->pdev->dev,
 464                                         "Unsupported LCD bus width mapping\n");
 465                         return -EINVAL;
 466                 case STMLCDIF_16BIT:
 467                 case STMLCDIF_18BIT:
 468                 case STMLCDIF_24BIT:
 469                         /* real 24 bit */
 470                         break;
 471                 }
 472                 /* do not use packed pixels = one pixel per word instead */
 473                 writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
 474                 break;
 475         default:
 476                 dev_err(&host->pdev->dev, "Unhandled color depth of %u\n",
 477                                 fb_info->var.bits_per_pixel);
 478                 return -EINVAL;
 479         }
 480
 481         writel(ctrl, host->base + LCDC_CTRL);
 482
 483         writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) |
 484                         TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres),
 485                         host->base + host->devdata->transfer_count);
 486
 487         vdctrl0 = VDCTRL0_ENABLE_PRESENT |      /* always in DOTCLOCK mode */
 488                 VDCTRL0_VSYNC_PERIOD_UNIT |
 489                 VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 490                 VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len);
 491         if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 492                 vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
 493         if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 494                 vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
 495         if (host->sync & MXSFB_SYNC_DATA_ENABLE_HIGH_ACT)
 496                 vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
 497         if (host->sync & MXSFB_SYNC_DOTCLK_FALLING_ACT)
 498                 vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING;
 499
 500         writel(vdctrl0, host->base + LCDC_VDCTRL0);
 501
 502         /* frame length in lines */
 503         writel(fb_info->var.upper_margin + fb_info->var.vsync_len +
 504                 fb_info->var.lower_margin + fb_info->var.yres,
 505                 host->base + LCDC_VDCTRL1);
 506
 507         /* line length in units of clocks or pixels */
 508         writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) |
 509                 VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin +
 510                 fb_info->var.hsync_len + fb_info->var.right_margin +
 511                 fb_info->var.xres),
 512                 host->base + LCDC_VDCTRL2);
 513
 514         writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin +
 515                 fb_info->var.hsync_len) |
 516                 SET_VERT_WAIT_CNT(fb_info->var.upper_margin +
 517                         fb_info->var.vsync_len),
 518                 host->base + LCDC_VDCTRL3);
 519
 520         vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres);
 521         if (mxsfb_is_v4(host))
 522                 vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay);
 523         writel(vdctrl4, host->base + LCDC_VDCTRL4);
 524
 525         writel(fb_info->fix.smem_start +
 526                         fb_info->fix.line_length * fb_info->var.yoffset,
 527                         host->base + host->devdata->next_buf);
 528
 529         if (reenable)
 530                 mxsfb_enable_controller(fb_info);
 531
 532         return 0;
 533 }
 534
 535 static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 536                 u_int transp, struct fb_info *fb_info)
 537 {
 538         unsigned int val;
 539         int ret = -EINVAL;
 540
 541         /*
 542          * If greyscale is true, then we convert the RGB value
 543          * to greyscale no matter what visual we are using.
 544          */
 545         if (fb_info->var.grayscale)
 546                 red = green = blue = (19595 * red + 38470 * green +
 547                                         7471 * blue) >> 16;
 548
 549         switch (fb_info->fix.visual) {
 550         case FB_VISUAL_TRUECOLOR:
 551                 /*
 552                  * 12 or 16-bit True Colour.  We encode the RGB value
 553                  * according to the RGB bitfield information.
 554                  */
 555                 if (regno < 16) {
 556                         u32 *pal = fb_info->pseudo_palette;
 557
 558                         val  = chan_to_field(red, &fb_info->var.red);
 559                         val |= chan_to_field(green, &fb_info->var.green);
 560                         val |= chan_to_field(blue, &fb_info->var.blue);
 561
 562                         pal[regno] = val;
 563                         ret = 0;
 564                 }
 565                 break;
 566
 567         case FB_VISUAL_STATIC_PSEUDOCOLOR:
 568         case FB_VISUAL_PSEUDOCOLOR:
 569                 break;
 570         }
 571
 572         return ret;
 573 }
 574
 575 static int mxsfb_blank(int blank, struct fb_info *fb_info)
 576 {
 577         struct mxsfb_info *host = to_imxfb_host(fb_info);
 578
 579         switch (blank) {
 580         case FB_BLANK_POWERDOWN:
 581         case FB_BLANK_VSYNC_SUSPEND:
 582         case FB_BLANK_HSYNC_SUSPEND:
 583         case FB_BLANK_NORMAL:
 584                 if (host->enabled)
 585                         mxsfb_disable_controller(fb_info);
 586
 587                 clk_disable_axi(host);
 588                 break;
 589
 590         case FB_BLANK_UNBLANK:
 591                 if (!host->enabled)
 592                         mxsfb_enable_controller(fb_info);
 593                 mxsfb_set_par(&host->fb_info);
 594                 break;
 595         }
 596         return 0;
 597 }
 598
 599 static int mxsfb_pan_display(struct fb_var_screeninfo *var,
 600                 struct fb_info *fb_info)
 601 {
 602         struct mxsfb_info *host = to_imxfb_host(fb_info);
 603         unsigned offset;
 604
 605         if (var->xoffset != 0)
 606                 return -EINVAL;
 607
 608         clk_enable_axi(host);
 609
 610         offset = fb_info->fix.line_length * var->yoffset;
 611
 612         /* update on next VSYNC */
 613         writel(fb_info->fix.smem_start + offset,
 614                         host->base + host->devdata->next_buf);
 615
 616         return 0;
 617 }
 618
 619 static struct fb_ops mxsfb_ops = {
 620         .owner = THIS_MODULE,
 621         .fb_check_var = mxsfb_check_var,
 622         .fb_set_par = mxsfb_set_par,
 623         .fb_setcolreg = mxsfb_setcolreg,
 624         .fb_blank = mxsfb_blank,
 625         .fb_pan_display = mxsfb_pan_display,
 626         .fb_fillrect = cfb_fillrect,
 627         .fb_copyarea = cfb_copyarea,
 628         .fb_imageblit = cfb_imageblit,
 629 };
 630
 631 static int mxsfb_restore_mode(struct mxsfb_info *host,
 632                         struct fb_videomode *vmode)
 633 {
 634         struct fb_info *fb_info = &host->fb_info;
 635         unsigned line_count;
 636         unsigned period;
 637         unsigned long pa, fbsize;
 638         int bits_per_pixel, ofs;
 639         u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
 640
 641         clk_enable_axi(host);
 642
 643         /* Only restore the mode when the controller is running */
 644         ctrl = readl(host->base + LCDC_CTRL);
 645         if (!(ctrl & CTRL_RUN))
 646                 return -EINVAL;
 647
 648         vdctrl0 = readl(host->base + LCDC_VDCTRL0);
 649         vdctrl2 = readl(host->base + LCDC_VDCTRL2);
 650         vdctrl3 = readl(host->base + LCDC_VDCTRL3);
 651         vdctrl4 = readl(host->base + LCDC_VDCTRL4);
 652
 653         transfer_count = readl(host->base + host->devdata->transfer_count);
 654
 655         vmode->xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count);
 656         vmode->yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count);
 657
 658         switch (CTRL_GET_WORD_LENGTH(ctrl)) {
 659         case 0:
 660                 bits_per_pixel = 16;
 661                 break;
 662         case 3:
 663                 bits_per_pixel = 32;
 664                 break;
 665         case 1:
 666         default:
 667                 return -EINVAL;
 668         }
 669
 670         fb_info->var.bits_per_pixel = bits_per_pixel;
 671
 672         vmode->pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U);
 673         vmode->hsync_len = get_hsync_pulse_width(host, vdctrl2);
 674         vmode->left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode->hsync_len;
 675         vmode->right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) -
 676                 vmode->hsync_len - vmode->left_margin - vmode->xres;
 677         vmode->vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0);
 678         period = readl(host->base + LCDC_VDCTRL1);
 679         vmode->upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode->vsync_len;
 680         vmode->lower_margin = period - vmode->vsync_len -
 681                 vmode->upper_margin - vmode->yres;
 682
 683         vmode->vmode = FB_VMODE_NONINTERLACED;
 684
 685         vmode->sync = 0;
 686         if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH)
 687                 vmode->sync |= FB_SYNC_HOR_HIGH_ACT;
 688         if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH)
 689                 vmode->sync |= FB_SYNC_VERT_HIGH_ACT;
 690
 691         pr_debug("Reconstructed video mode:\n");
 692         pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n",
 693                 vmode->xres, vmode->yres, vmode->hsync_len, vmode->left_margin,
 694                 vmode->right_margin, vmode->vsync_len, vmode->upper_margin,
 695                 vmode->lower_margin);
 696         pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode->pixclock));
 697
 698         host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl);
 699         host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4);
 700
 701         fb_info->fix.line_length = vmode->xres * (bits_per_pixel >> 3);
 702
 703         pa = readl(host->base + host->devdata->cur_buf);
 704         fbsize = fb_info->fix.line_length * vmode->yres;
 705         if (pa < fb_info->fix.smem_start)
 706                 return -EINVAL;
 707         if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len)
 708                 return -EINVAL;
 709         ofs = pa - fb_info->fix.smem_start;
 710         if (ofs) {
 711                 memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize);
 712                 writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf);
 713         }
 714
 715         line_count = fb_info->fix.smem_len / fb_info->fix.line_length;
 716         fb_info->fix.ypanstep = 1;
 717
 718         clk_prepare_enable(host->clk_pix);
 719         host->enabled = 1;
 720
 721         return 0;
 722 }
 723
 724 static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host,
 725                                 struct fb_videomode *vmode)
 726 {
 727         struct fb_info *fb_info = &host->fb_info;
 728         struct fb_var_screeninfo *var = &fb_info->var;
 729         struct device *dev = &host->pdev->dev;
 730         struct device_node *np = host->pdev->dev.of_node;
 731         struct device_node *display_np;
 732         struct videomode vm;
 733         u32 width;
 734         int ret;
 735
 736         display_np = of_parse_phandle(np, "display", 0);
 737         if (!display_np) {
 738                 dev_err(dev, "failed to find display phandle\n");
 739                 return -ENOENT;
 740         }
 741
 742         ret = of_property_read_u32(display_np, "bus-width", &width);
 743         if (ret < 0) {
 744                 dev_err(dev, "failed to get property bus-width\n");
 745                 goto put_display_node;
 746         }
 747
 748         switch (width) {
 749         case 8:
 750                 host->ld_intf_width = STMLCDIF_8BIT;
 751                 break;
 752         case 16:
 753                 host->ld_intf_width = STMLCDIF_16BIT;
 754                 break;
 755         case 18:
 756                 host->ld_intf_width = STMLCDIF_18BIT;
 757                 break;
 758         case 24:
 759                 host->ld_intf_width = STMLCDIF_24BIT;
 760                 break;
 761         default:
 762                 dev_err(dev, "invalid bus-width value\n");
 763                 ret = -EINVAL;
 764                 goto put_display_node;
 765         }
 766
 767         ret = of_property_read_u32(display_np, "bits-per-pixel",
 768                                    &var->bits_per_pixel);
 769         if (ret < 0) {
 770                 dev_err(dev, "failed to get property bits-per-pixel\n");
 771                 goto put_display_node;
 772         }
 773
 774         ret = of_get_videomode(display_np, &vm, OF_USE_NATIVE_MODE);
 775         if (ret) {
 776                 dev_err(dev, "failed to get videomode from DT\n");
 777                 goto put_display_node;
 778         }
 779
 780         ret = fb_videomode_from_videomode(&vm, vmode);
 781         if (ret < 0)
 782                 goto put_display_node;
 783
 784         if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
 785                 host->sync |= MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
 786         if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 787                 host->sync |= MXSFB_SYNC_DOTCLK_FALLING_ACT;
 788
 789 put_display_node:
 790         of_node_put(display_np);
 791         return ret;
 792 }
 793
 794 static int mxsfb_init_fbinfo(struct mxsfb_info *host,
 795                         struct fb_videomode *vmode)
 796 {
 797         int ret;
 798         struct fb_info *fb_info = &host->fb_info;
 799         struct fb_var_screeninfo *var = &fb_info->var;
 800         dma_addr_t fb_phys;
 801         void *fb_virt;
 802         unsigned fb_size;
 803
 804         fb_info->fbops = &mxsfb_ops;
 805         fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
 806         strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id));
 807         fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
 808         fb_info->fix.ypanstep = 1;
 809         fb_info->fix.visual = FB_VISUAL_TRUECOLOR,
 810         fb_info->fix.accel = FB_ACCEL_NONE;
 811
 812         ret = mxsfb_init_fbinfo_dt(host, vmode);
 813         if (ret)
 814                 return ret;
 815
 816         var->nonstd = 0;
 817         var->activate = FB_ACTIVATE_NOW;
 818         var->accel_flags = 0;
 819         var->vmode = FB_VMODE_NONINTERLACED;
 820
 821         /* Memory allocation for framebuffer */
 822         fb_size = SZ_2M;
 823         fb_virt = alloc_pages_exact(fb_size, GFP_DMA);
 824         if (!fb_virt)
 825                 return -ENOMEM;
 826
 827         fb_phys = virt_to_phys(fb_virt);
 828
 829         fb_info->fix.smem_start = fb_phys;
 830         fb_info->screen_base = fb_virt;
 831         fb_info->screen_size = fb_info->fix.smem_len = fb_size;
 832
 833         if (mxsfb_restore_mode(host, vmode))
 834                 memset(fb_virt, 0, fb_size);
 835
 836         return 0;
 837 }
 838
 839 static void mxsfb_free_videomem(struct mxsfb_info *host)
 840 {
 841         struct fb_info *fb_info = &host->fb_info;
 842
 843         free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len);
 844 }
 845
 846 static struct platform_device_id mxsfb_devtype[] = {
 847         {
 848                 .name = "imx23-fb",
 849                 .driver_data = MXSFB_V3,
 850         }, {
 851                 .name = "imx28-fb",
 852                 .driver_data = MXSFB_V4,
 853         }, {
 854                 /* sentinel */
 855         }
 856 };
 857 MODULE_DEVICE_TABLE(platform, mxsfb_devtype);
 858
 859 static const struct of_device_id mxsfb_dt_ids[] = {
 860         { .compatible = "fsl,imx23-lcdif", .data = &mxsfb_devtype[0], },
 861         { .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devtype[1], },
 862         { /* sentinel */ }
 863 };
 864 MODULE_DEVICE_TABLE(of, mxsfb_dt_ids);
 865
 866 static int mxsfb_probe(struct platform_device *pdev)
 867 {
 868         const struct of_device_id *of_id =
 869                         of_match_device(mxsfb_dt_ids, &pdev->dev);
 870         struct resource *res;
 871         struct mxsfb_info *host;
 872         struct fb_info *fb_info;
 873         struct fb_videomode *mode;
 874         int ret;
 875
 876         if (of_id)
 877                 pdev->id_entry = of_id->data;
 878
 879         fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev);
 880         if (!fb_info) {
 881                 dev_err(&pdev->dev, "Failed to allocate fbdev\n");
 882                 return -ENOMEM;
 883         }
 884
 885         mode = devm_kzalloc(&pdev->dev, sizeof(struct fb_videomode),
 886                         GFP_KERNEL);
 887         if (mode == NULL)
 888                 return -ENOMEM;
 889
 890         host = to_imxfb_host(fb_info);
 891
 892         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 893         host->base = devm_ioremap_resource(&pdev->dev, res);
 894         if (IS_ERR(host->base)) {
 895                 ret = PTR_ERR(host->base);
 896                 goto fb_release;
 897         }
 898
 899         host->pdev = pdev;
 900         platform_set_drvdata(pdev, host);
 901
 902         host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
 903
 904         host->clk_pix = devm_clk_get(&host->pdev->dev, "pix");
 905         if (IS_ERR(host->clk_pix)) {
 906                 ret = PTR_ERR(host->clk_pix);
 907                 goto fb_release;
 908         }
 909
 910         host->clk_axi = devm_clk_get(&host->pdev->dev, "axi");
 911         if (IS_ERR(host->clk_axi)) {
 912                 ret = PTR_ERR(host->clk_axi);
 913                 goto fb_release;
 914         }
 915
 916         host->reg_lcd = devm_regulator_get(&pdev->dev, "lcd");
 917         if (IS_ERR(host->reg_lcd))
 918                 host->reg_lcd = NULL;
 919
 920         fb_info->pseudo_palette = devm_kzalloc(&pdev->dev, sizeof(u32) * 16,
 921                                                GFP_KERNEL);
 922         if (!fb_info->pseudo_palette) {
 923                 ret = -ENOMEM;
 924                 goto fb_release;
 925         }
 926
 927         ret = mxsfb_init_fbinfo(host, mode);
 928         if (ret != 0)
 929                 goto fb_release;
 930
 931         fb_videomode_to_var(&fb_info->var, mode);
 932
 933         /* init the color fields */
 934         mxsfb_check_var(&fb_info->var, fb_info);
 935
 936         platform_set_drvdata(pdev, fb_info);
 937
 938         ret = register_framebuffer(fb_info);
 939         if (ret != 0) {
 940                 dev_err(&pdev->dev,"Failed to register framebuffer\n");
 941                 goto fb_destroy;
 942         }
 943
 944         if (!host->enabled) {
 945                 writel(0, host->base + LCDC_CTRL);
 946                 mxsfb_set_par(fb_info);
 947                 mxsfb_enable_controller(fb_info);
 948         }
 949
 950         dev_info(&pdev->dev, "initialized\n");
 951
 952         return 0;
 953
 954 fb_destroy:
 955         if (host->enabled)
 956                 clk_disable_unprepare(host->clk_pix);
 957 fb_release:
 958         framebuffer_release(fb_info);
 959
 960         return ret;
 961 }
 962
 963 static int mxsfb_remove(struct platform_device *pdev)
 964 {
 965         struct fb_info *fb_info = platform_get_drvdata(pdev);
 966         struct mxsfb_info *host = to_imxfb_host(fb_info);
 967
 968         if (host->enabled)
 969                 mxsfb_disable_controller(fb_info);
 970
 971         unregister_framebuffer(fb_info);
 972         mxsfb_free_videomem(host);
 973
 974         framebuffer_release(fb_info);
 975
 976         return 0;
 977 }
 978
 979 static void mxsfb_shutdown(struct platform_device *pdev)
 980 {
 981         struct fb_info *fb_info = platform_get_drvdata(pdev);
 982         struct mxsfb_info *host = to_imxfb_host(fb_info);
 983
 984         clk_enable_axi(host);
 985         /*
 986          * Force stop the LCD controller as keeping it running during reboot
 987          * might interfere with the BootROM's boot mode pads sampling.
 988          */
 989         writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR);
 990         writel(CTRL_MASTER, host->base + LCDC_CTRL + REG_CLR);
 991         clk_disable_axi(host);
 992 }
 993
 994 static struct platform_driver mxsfb_driver = {
 995         .probe = mxsfb_probe,
 996         .remove = mxsfb_remove,
 997         .shutdown = mxsfb_shutdown,
 998         .id_table = mxsfb_devtype,
 999         .driver = {
1000                    .name = DRIVER_NAME,
1001                    .of_match_table = mxsfb_dt_ids,
1002         },
1003 };
1004
1005 module_platform_driver(mxsfb_driver);
1006
1007 MODULE_DESCRIPTION("Freescale mxs framebuffer driver");
1008 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1009 MODULE_LICENSE("GPL");