include/asm-x86_64/system.h

   1 #ifndef __ASM_SYSTEM_H
   2 #define __ASM_SYSTEM_H
   3
   4 #include <linux/config.h>
   5 #include <linux/kernel.h>
   6 #include <asm/segment.h>
   7
   8 #ifdef __KERNEL__
   9
  10 #ifdef CONFIG_SMP
  11 #define LOCK_PREFIX "lock ; "
  12 #else
  13 #define LOCK_PREFIX ""
  14 #endif
  15
  16 #define __STR(x) #x
  17 #define STR(x) __STR(x)
  18
  19 #define __SAVE(reg,offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  20 #define __RESTORE(reg,offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  21
  22 /* frame pointer must be last for get_wchan */
  23 #define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
  24 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
  25
  26 #define __EXTRA_CLOBBER  \
  27         ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
  28
  29 /* Save restore flags to clear handle leaking NT */
  30 #define switch_to(prev,next,last) \
  31         asm volatile(SAVE_CONTEXT                                                   \
  32                      "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
  33                      "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
  34                      "call __switch_to\n\t"                                       \
  35                      ".globl thread_return\n"                                   \
  36                      "thread_return:\n\t"                                           \
  37                      "movq %%gs:%P[pda_pcurrent],%%rsi\n\t"                       \
  38                      "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
  39                      LOCK "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"               \
  40                      "movq %%rax,%%rdi\n\t"                                       \
  41                      "jc   ret_from_fork\n\t"                                     \
  42                      RESTORE_CONTEXT                                                \
  43                      : "=a" (last)                                                \
  44                      : [next] "S" (next), [prev] "D" (prev),                      \
  45                        [threadrsp] "i" (offsetof(struct task_struct, thread.rsp)), \
  46                        [ti_flags] "i" (offsetof(struct thread_info, flags)),\
  47                        [tif_fork] "i" (TIF_FORK),                         \
  48                        [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
  49                        [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent))   \
  50                      : "memory", "cc" __EXTRA_CLOBBER)
  51
  52 extern void load_gs_index(unsigned);
  53
  54 /*
  55  * Load a segment. Fall back on loading the zero
  56  * segment if something goes wrong..
  57  */
  58 #define loadsegment(seg,value)  \
  59         asm volatile("\n"                       \
  60                 "1:\t"                          \
  61                 "movl %k0,%%" #seg "\n"         \
  62                 "2:\n"                          \
  63                 ".section .fixup,\"ax\"\n"      \
  64                 "3:\t"                          \
  65                 "movl %1,%%" #seg "\n\t"        \
  66                 "jmp 2b\n"                      \
  67                 ".previous\n"                   \
  68                 ".section __ex_table,\"a\"\n\t" \
  69                 ".align 8\n\t"                  \
  70                 ".quad 1b,3b\n"                 \
  71                 ".previous"                     \
  72                 : :"r" (value), "r" (0))
  73
  74 #define set_debug(value,register) \
  75                 __asm__("movq %0,%%db" #register  \
  76                 : /* no output */ \
  77                 :"r" ((unsigned long) value))
  78
  79
  80 #ifdef __KERNEL__
  81 struct alt_instr {
  82         __u8 *instr;            /* original instruction */
  83         __u8 *replacement;
  84         __u8  cpuid;            /* cpuid bit set for replacement */
  85         __u8  instrlen;         /* length of original instruction */
  86         __u8  replacementlen;   /* length of new instruction, <= instrlen */
  87         __u8  pad[5];
  88 };
  89 #endif
  90
  91 /*
  92  * Alternative instructions for different CPU types or capabilities.
  93  *
  94  * This allows to use optimized instructions even on generic binary
  95  * kernels.
  96  *
  97  * length of oldinstr must be longer or equal the length of newinstr
  98  * It can be padded with nops as needed.
  99  *
 100  * For non barrier like inlines please define new variants
 101  * without volatile and memory clobber.
 102  */
 103 #define alternative(oldinstr, newinstr, feature)        \
 104         asm volatile ("661:\n\t" oldinstr "\n662:\n"                 \
 105                       ".section .altinstructions,\"a\"\n"            \
 106                       "  .align 8\n"                                   \
 107                       "  .quad 661b\n"            /* label */          \
 108                       "  .quad 663f\n"            /* new instruction */ \
 109                       "  .byte %c0\n"             /* feature bit */    \
 110                       "  .byte 662b-661b\n"       /* sourcelen */      \
 111                       "  .byte 664f-663f\n"       /* replacementlen */ \
 112                       ".previous\n"                                     \
 113                       ".section .altinstr_replacement,\"ax\"\n"         \
 114                       "663:\n\t" newinstr "\n664:\n"   /* replacement */ \
 115                       ".previous" :: "i" (feature) : "memory")
 116
 117 /*
 118  * Alternative inline assembly with input.
 119  *
 120  * Peculiarities:
 121  * No memory clobber here.
 122  * Argument numbers start with 1.
 123  * Best is to use constraints that are fixed size (like (%1) ... "r")
 124  * If you use variable sized constraints like "m" or "g" in the
 125  * replacement make sure to pad to the worst case length.
 126  */
 127 #define alternative_input(oldinstr, newinstr, feature, input...)        \
 128         asm volatile ("661:\n\t" oldinstr "\n662:\n"                    \
 129                       ".section .altinstructions,\"a\"\n"               \
 130                       "  .align 8\n"                                    \
 131                       "  .quad 661b\n"            /* label */           \
 132                       "  .quad 663f\n"            /* new instruction */ \
 133                       "  .byte %c0\n"             /* feature bit */     \
 134                       "  .byte 662b-661b\n"       /* sourcelen */       \
 135                       "  .byte 664f-663f\n"       /* replacementlen */  \
 136                       ".previous\n"                                     \
 137                       ".section .altinstr_replacement,\"ax\"\n"         \
 138                       "663:\n\t" newinstr "\n664:\n"   /* replacement */ \
 139                       ".previous" :: "i" (feature), ##input)
 140
 141 /* Like alternative_input, but with a single output argument */
 142 #define alternative_io(oldinstr, newinstr, feature, output, input...) \
 143         asm volatile ("661:\n\t" oldinstr "\n662:\n"                    \
 144                       ".section .altinstructions,\"a\"\n"               \
 145                       "  .align 8\n"                                    \
 146                       "  .quad 661b\n"            /* label */           \
 147                       "  .quad 663f\n"            /* new instruction */ \
 148                       "  .byte %c[feat]\n"        /* feature bit */     \
 149                       "  .byte 662b-661b\n"       /* sourcelen */       \
 150                       "  .byte 664f-663f\n"       /* replacementlen */  \
 151                       ".previous\n"                                     \
 152                       ".section .altinstr_replacement,\"ax\"\n"         \
 153                       "663:\n\t" newinstr "\n664:\n"   /* replacement */ \
 154                       ".previous" : output : [feat] "i" (feature), ##input)
 155
 156 /*
 157  * Clear and set 'TS' bit respectively
 158  */
 159 #define clts() __asm__ __volatile__ ("clts")
 160
 161 static inline unsigned long __raw_local_save_flags(void)
 162 {
 163         unsigned long flags;
 164
 165         __asm__ __volatile__(
 166                 "# __raw_save_flags\n\t"
 167                 "pushfq ; popq %q0"
 168                 : "=g" (flags)
 169                 : /* no input */
 170                 : "memory"
 171         );
 172
 173         return flags;
 174 }
 175 #define raw_local_save_flags(flags) \
 176                 do { (flags) = __raw_local_save_flags(); } while (0)
 177
 178 static inline unsigned long read_cr0(void)
 179 {
 180         unsigned long cr0;
 181         asm volatile("movq %%cr0,%0" : "=r" (cr0));
 182         return cr0;
 183 }
 184
 185 static inline void write_cr0(unsigned long val)
 186 {
 187         asm volatile("movq %0,%%cr0" :: "r" (val));
 188 }
 189
 190 static inline unsigned long read_cr3(void)
 191 {
 192         unsigned long cr3;
 193         asm("movq %%cr3,%0" : "=r" (cr3));
 194         return cr3;
 195 }
 196
 197 static inline unsigned long read_cr4(void)
 198 {
 199         unsigned long cr4;
 200         asm("movq %%cr4,%0" : "=r" (cr4));
 201         return cr4;
 202 }
 203
 204 static inline void write_cr4(unsigned long val)
 205 {
 206         asm volatile("movq %0,%%cr4" :: "r" (val));
 207 }
 208
 209 #define stts() write_cr0(8 | read_cr0())
 210
 211 #define wbinvd() \
 212         __asm__ __volatile__ ("wbinvd": : :"memory");
 213
 214 /*
 215  * On SMP systems, when the scheduler does migration-cost autodetection,
 216  * it needs a way to flush as much of the CPU's caches as possible.
 217  */
 218 static inline void sched_cacheflush(void)
 219 {
 220         wbinvd();
 221 }
 222
 223 #endif  /* __KERNEL__ */
 224
 225 #define nop() __asm__ __volatile__ ("nop")
 226
 227 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 228
 229 #define tas(ptr) (xchg((ptr),1))
 230
 231 #define __xg(x) ((volatile long *)(x))
 232
 233 static inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
 234 {
 235         *ptr = val;
 236 }
 237
 238 #define _set_64bit set_64bit
 239
 240 /*
 241  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
 242  * Note 2: xchg has side effect, so that attribute volatile is necessary,
 243  *        but generally the primitive is invalid, *ptr is output argument. --ANK
 244  */
 245 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 246 {
 247         switch (size) {
 248                 case 1:
 249                         __asm__ __volatile__("xchgb %b0,%1"
 250                                 :"=q" (x)
 251                                 :"m" (*__xg(ptr)), "0" (x)
 252                                 :"memory");
 253                         break;
 254                 case 2:
 255                         __asm__ __volatile__("xchgw %w0,%1"
 256                                 :"=r" (x)
 257                                 :"m" (*__xg(ptr)), "0" (x)
 258                                 :"memory");
 259                         break;
 260                 case 4:
 261                         __asm__ __volatile__("xchgl %k0,%1"
 262                                 :"=r" (x)
 263                                 :"m" (*__xg(ptr)), "0" (x)
 264                                 :"memory");
 265                         break;
 266                 case 8:
 267                         __asm__ __volatile__("xchgq %0,%1"
 268                                 :"=r" (x)
 269                                 :"m" (*__xg(ptr)), "0" (x)
 270                                 :"memory");
 271                         break;
 272         }
 273         return x;
 274 }
 275
 276 /*
 277  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 278  * store NEW in MEM.  Return the initial value in MEM.  Success is
 279  * indicated by comparing RETURN with OLD.
 280  */
 281
 282 #define __HAVE_ARCH_CMPXCHG 1
 283
 284 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 285                                       unsigned long new, int size)
 286 {
 287         unsigned long prev;
 288         switch (size) {
 289         case 1:
 290                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
 291                                      : "=a"(prev)
 292                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
 293                                      : "memory");
 294                 return prev;
 295         case 2:
 296                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
 297                                      : "=a"(prev)
 298                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 299                                      : "memory");
 300                 return prev;
 301         case 4:
 302                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %k1,%2"
 303                                      : "=a"(prev)
 304                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 305                                      : "memory");
 306                 return prev;
 307         case 8:
 308                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgq %1,%2"
 309                                      : "=a"(prev)
 310                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 311                                      : "memory");
 312                 return prev;
 313         }
 314         return old;
 315 }
 316
 317 #define cmpxchg(ptr,o,n)\
 318         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 319                                         (unsigned long)(n),sizeof(*(ptr))))
 320
 321 #ifdef CONFIG_SMP
 322 #define smp_mb()        mb()
 323 #define smp_rmb()       rmb()
 324 #define smp_wmb()       wmb()
 325 #define smp_read_barrier_depends()      do {} while(0)
 326 #else
 327 #define smp_mb()        barrier()
 328 #define smp_rmb()       barrier()
 329 #define smp_wmb()       barrier()
 330 #define smp_read_barrier_depends()      do {} while(0)
 331 #endif
 332
 333
 334 /*
 335  * Force strict CPU ordering.
 336  * And yes, this is required on UP too when we're talking
 337  * to devices.
 338  */
 339 #define mb()    asm volatile("mfence":::"memory")
 340 #define rmb()   asm volatile("lfence":::"memory")
 341
 342 #ifdef CONFIG_UNORDERED_IO
 343 #define wmb()   asm volatile("sfence" ::: "memory")
 344 #else
 345 #define wmb()   asm volatile("" ::: "memory")
 346 #endif
 347 #define read_barrier_depends()  do {} while(0)
 348 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
 349 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
 350
 351 #define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
 352
 353 /* interrupt control.. */
 354 #define local_save_flags(x)     do { warn_if_not_ulong(x); __asm__ __volatile__("# save_flags \n\t pushfq ; popq %q0":"=g" (x): /* no input */ :"memory"); } while (0)
 355 #define local_irq_restore(x)    __asm__ __volatile__("# restore_flags \n\t pushq %0 ; popfq": /* no output */ :"g" (x):"memory", "cc")
 356
 357 #ifdef CONFIG_X86_VSMP
 358 /* Interrupt control for VSMP  architecture */
 359 #define local_irq_disable()     do { unsigned long flags; local_save_flags(flags); local_irq_restore((flags & ~(1 << 9)) | (1 << 18)); } while (0)
 360 #define local_irq_enable()      do { unsigned long flags; local_save_flags(flags); local_irq_restore((flags | (1 << 9)) & ~(1 << 18)); } while (0)
 361
 362 #define irqs_disabled()                                 \
 363 ({                                                      \
 364         unsigned long flags;                            \
 365         local_save_flags(flags);                        \
 366         (flags & (1<<18)) || !(flags & (1<<9));         \
 367 })
 368
 369 /* For spinlocks etc */
 370 #define local_irq_save(x)       do { local_save_flags(x); local_irq_restore((x & ~(1 << 9)) | (1 << 18)); } while (0)
 371 #else  /* CONFIG_X86_VSMP */
 372 #define local_irq_disable()     __asm__ __volatile__("cli": : :"memory")
 373 #define local_irq_enable()      __asm__ __volatile__("sti": : :"memory")
 374
 375 #define irqs_disabled()                 \
 376 ({                                      \
 377         unsigned long flags;            \
 378         local_save_flags(flags);        \
 379         !(flags & (1<<9));              \
 380 })
 381
 382 /* For spinlocks etc */
 383 #define local_irq_save(x)       do { warn_if_not_ulong(x); __asm__ __volatile__("# local_irq_save \n\t pushfq ; popq %0 ; cli":"=g" (x): /* no input */ :"memory"); } while (0)
 384 #endif
 385
 386 /* used in the idle loop; sti takes one instruction cycle to complete */
 387 #define safe_halt()             __asm__ __volatile__("sti; hlt": : :"memory")
 388 /* used when interrupts are already enabled or to shutdown the processor */
 389 #define halt()                  __asm__ __volatile__("hlt": : :"memory")
 390
 391 void cpu_idle_wait(void);
 392
 393 extern unsigned long arch_align_stack(unsigned long sp);
 394
 395 #endif