4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
31 #include <linux/interrupt.h>
33 #include <linux/resource_ext.h>
34 #include <uapi/linux/pci.h>
36 #include <linux/pci_ids.h>
39 * The PCI interface treats multi-function devices as independent
40 * devices. The slot/function address of each device is encoded
41 * in a single byte as follows:
46 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
47 * In the interest of not exposing interfaces to user-space unnecessarily,
48 * the following kernel-only defines are being added here.
50 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
51 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
52 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54 /* pci_slot represents a physical slot */
56 struct pci_bus *bus; /* The bus this slot is on */
57 struct list_head list; /* node in list of slots on this bus */
58 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
59 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
63 static inline const char *pci_slot_name(const struct pci_slot *slot)
65 return kobject_name(&slot->kobj);
68 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 * For PCI devices, the region numbers are assigned this way:
78 /* #0-5: standard PCI resources */
80 PCI_STD_RESOURCE_END = 5,
82 /* #6: expansion ROM resource */
85 /* device specific resources */
88 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
91 /* resources assigned to buses behind the bridge */
92 #define PCI_BRIDGE_RESOURCE_NUM 4
95 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
96 PCI_BRIDGE_RESOURCE_NUM - 1,
98 /* total resources associated with a PCI device */
101 /* preserve this for compatibility */
102 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
106 * pci_power_t values must match the bits in the Capabilities PME_Support
107 * and Control/Status PowerState fields in the Power Management capability.
109 typedef int __bitwise pci_power_t;
111 #define PCI_D0 ((pci_power_t __force) 0)
112 #define PCI_D1 ((pci_power_t __force) 1)
113 #define PCI_D2 ((pci_power_t __force) 2)
114 #define PCI_D3hot ((pci_power_t __force) 3)
115 #define PCI_D3cold ((pci_power_t __force) 4)
116 #define PCI_UNKNOWN ((pci_power_t __force) 5)
117 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
119 /* Remember to update this when the list above changes! */
120 extern const char *pci_power_names[];
122 static inline const char *pci_power_name(pci_power_t state)
124 return pci_power_names[1 + (__force int) state];
127 #define PCI_PM_D2_DELAY 200
128 #define PCI_PM_D3_WAIT 10
129 #define PCI_PM_D3COLD_WAIT 100
130 #define PCI_PM_BUS_WAIT 50
132 /** The pci_channel state describes connectivity between the CPU and
133 * the pci device. If some PCI bus between here and the pci device
134 * has crashed or locked up, this info is reflected here.
136 typedef unsigned int __bitwise pci_channel_state_t;
138 enum pci_channel_state {
139 /* I/O channel is in normal state */
140 pci_channel_io_normal = (__force pci_channel_state_t) 1,
142 /* I/O to channel is blocked */
143 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
145 /* PCI card is dead */
146 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
149 typedef unsigned int __bitwise pcie_reset_state_t;
151 enum pcie_reset_state {
152 /* Reset is NOT asserted (Use to deassert reset) */
153 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
155 /* Use #PERST to reset PCIe device */
156 pcie_warm_reset = (__force pcie_reset_state_t) 2,
158 /* Use PCIe Hot Reset to reset device */
159 pcie_hot_reset = (__force pcie_reset_state_t) 3
162 typedef unsigned short __bitwise pci_dev_flags_t;
164 /* INTX_DISABLE in PCI_COMMAND register disables MSI
167 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
168 /* Device configuration is irrevocably lost if disabled into D3 */
169 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
170 /* Provide indication device is assigned by a Virtual Machine Manager */
171 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
172 /* Flag for quirk use to store if quirk-specific ACS is enabled */
173 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
174 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
175 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
176 /* Do not use bus resets for device */
177 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
178 /* Do not use PM reset even if device advertises NoSoftRst- */
179 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
180 /* Get VPD from function 0 VPD */
181 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
182 /* a non-root bridge where translation occurs, stop alias search here */
183 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
184 /* Do not use FLR even if device advertises PCI_AF_CAP */
185 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
187 * Resume before calling the driver's system suspend hooks, disabling
188 * the direct_complete optimization.
190 PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11),
193 enum pci_irq_reroute_variant {
194 INTEL_IRQ_REROUTE_VARIANT = 1,
195 MAX_IRQ_REROUTE_VARIANTS = 3
198 typedef unsigned short __bitwise pci_bus_flags_t;
200 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
201 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
202 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
205 /* These values come from the PCI Express Spec */
206 enum pcie_link_width {
207 PCIE_LNK_WIDTH_RESRV = 0x00,
215 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
218 /* Based on the PCI Hotplug Spec, but some values are made up by us */
220 PCI_SPEED_33MHz = 0x00,
221 PCI_SPEED_66MHz = 0x01,
222 PCI_SPEED_66MHz_PCIX = 0x02,
223 PCI_SPEED_100MHz_PCIX = 0x03,
224 PCI_SPEED_133MHz_PCIX = 0x04,
225 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
226 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
227 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
228 PCI_SPEED_66MHz_PCIX_266 = 0x09,
229 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
230 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
236 PCI_SPEED_66MHz_PCIX_533 = 0x11,
237 PCI_SPEED_100MHz_PCIX_533 = 0x12,
238 PCI_SPEED_133MHz_PCIX_533 = 0x13,
239 PCIE_SPEED_2_5GT = 0x14,
240 PCIE_SPEED_5_0GT = 0x15,
241 PCIE_SPEED_8_0GT = 0x16,
242 PCI_SPEED_UNKNOWN = 0xff,
245 struct pci_cap_saved_data {
252 struct pci_cap_saved_state {
253 struct hlist_node next;
254 struct pci_cap_saved_data cap;
258 struct pcie_link_state;
264 * The pci_dev structure is used to describe PCI devices.
267 struct list_head bus_list; /* node in per-bus list */
268 struct pci_bus *bus; /* bus this device is on */
269 struct pci_bus *subordinate; /* bus this device bridges to */
271 void *sysdata; /* hook for sys-specific extension */
272 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
273 struct pci_slot *slot; /* Physical slot this device is in */
275 unsigned int devfn; /* encoded device & function index */
276 unsigned short vendor;
277 unsigned short device;
278 unsigned short subsystem_vendor;
279 unsigned short subsystem_device;
280 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
281 u8 revision; /* PCI revision, low byte of class word */
282 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
283 #ifdef CONFIG_PCIEAER
284 u16 aer_cap; /* AER capability offset */
286 u8 pcie_cap; /* PCIe capability offset */
287 u8 msi_cap; /* MSI capability offset */
288 u8 msix_cap; /* MSI-X capability offset */
289 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
290 u8 rom_base_reg; /* which config register controls the ROM */
291 u8 pin; /* which interrupt pin this device uses */
292 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
293 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */
295 struct pci_driver *driver; /* which driver has allocated this device */
296 u64 dma_mask; /* Mask of the bits of bus address this
297 device implements. Normally this is
298 0xffffffff. You only need to change
299 this if your device has broken DMA
300 or supports 64-bit transfers. */
302 struct device_dma_parameters dma_parms;
304 pci_power_t current_state; /* Current operating state. In ACPI-speak,
305 this is D0-D3, D0 being fully functional,
307 u8 pm_cap; /* PM capability offset */
308 unsigned int pme_support:5; /* Bitmask of states from which PME#
310 unsigned int pme_poll:1; /* Poll device's PME status bit */
311 unsigned int d1_support:1; /* Low power state D1 is supported */
312 unsigned int d2_support:1; /* Low power state D2 is supported */
313 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
314 unsigned int no_d3cold:1; /* D3cold is forbidden */
315 unsigned int bridge_d3:1; /* Allow D3 for bridge */
316 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
317 unsigned int mmio_always_on:1; /* disallow turning off io/mem
318 decoding during bar sizing */
319 unsigned int wakeup_prepared:1;
320 unsigned int runtime_d3cold:1; /* whether go through runtime
321 D3cold, not set for devices
322 powered on/off by the
323 corresponding bridge */
324 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
325 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
326 controlled exclusively by
328 unsigned int d3_delay; /* D3->D0 transition time in ms */
329 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
331 #ifdef CONFIG_PCIEASPM
332 struct pcie_link_state *link_state; /* ASPM link state */
335 pci_channel_state_t error_state; /* current connectivity state */
336 struct device dev; /* Generic device interface */
338 int cfg_size; /* Size of configuration space */
341 * Instead of touching interrupt line and base address registers
342 * directly, use the values stored here. They might be different!
345 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
347 bool match_driver; /* Skip attaching driver */
348 /* These fields are used by common fixups */
349 unsigned int transparent:1; /* Subtractive decode PCI bridge */
350 unsigned int multifunction:1;/* Part of multi-function device */
351 /* keep track of device state */
352 unsigned int is_added:1;
353 unsigned int is_busmaster:1; /* device is busmaster */
354 unsigned int no_msi:1; /* device may not use msi */
355 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
356 unsigned int block_cfg_access:1; /* config space access is blocked */
357 unsigned int broken_parity_status:1; /* Device generates false positive parity */
358 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
359 unsigned int msi_enabled:1;
360 unsigned int msix_enabled:1;
361 unsigned int ari_enabled:1; /* ARI forwarding */
362 unsigned int ats_enabled:1; /* Address Translation Service */
363 unsigned int is_managed:1;
364 unsigned int needs_freset:1; /* Dev requires fundamental reset */
365 unsigned int state_saved:1;
366 unsigned int is_physfn:1;
367 unsigned int is_virtfn:1;
368 unsigned int reset_fn:1;
369 unsigned int is_hotplug_bridge:1;
370 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
371 unsigned int __aer_firmware_first_valid:1;
372 unsigned int __aer_firmware_first:1;
373 unsigned int broken_intx_masking:1;
374 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
375 unsigned int irq_managed:1;
376 unsigned int has_secondary_link:1;
377 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
378 unsigned int is_probed:1; /* device probing in progress */
379 pci_dev_flags_t dev_flags;
380 atomic_t enable_cnt; /* pci_enable_device has been called */
382 u32 saved_config_space[16]; /* config space saved at suspend time */
383 struct hlist_head saved_cap_space;
384 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
385 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
386 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
387 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
389 #ifdef CONFIG_PCIE_PTM
390 unsigned int ptm_root:1;
391 unsigned int ptm_enabled:1;
394 #ifdef CONFIG_PCI_MSI
395 const struct attribute_group **msi_irq_groups;
398 #ifdef CONFIG_PCI_ATS
400 struct pci_sriov *sriov; /* SR-IOV capability related */
401 struct pci_dev *physfn; /* the PF this VF is associated with */
403 u16 ats_cap; /* ATS Capability offset */
404 u8 ats_stu; /* ATS Smallest Translation Unit */
405 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
407 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
408 size_t romlen; /* Length of ROM if it's not from the BAR */
409 char *driver_override; /* Driver name to force a match */
411 unsigned long priv_flags; /* Private flags for the pci driver */
414 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
416 #ifdef CONFIG_PCI_IOV
423 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
425 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
426 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
428 static inline int pci_channel_offline(struct pci_dev *pdev)
430 return (pdev->error_state != pci_channel_io_normal);
433 struct pci_host_bridge {
435 struct pci_bus *bus; /* root bus */
439 struct list_head windows; /* resource_entry */
440 void (*release_fn)(struct pci_host_bridge *);
442 struct msi_controller *msi;
443 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
444 /* Resource alignment requirements */
445 resource_size_t (*align_resource)(struct pci_dev *dev,
446 const struct resource *res,
447 resource_size_t start,
448 resource_size_t size,
449 resource_size_t align);
450 unsigned long private[0] ____cacheline_aligned;
453 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
455 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
457 return (void *)bridge->private;
460 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
462 return container_of(priv, struct pci_host_bridge, private);
465 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
466 int pci_register_host_bridge(struct pci_host_bridge *bridge);
467 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
469 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
470 void (*release_fn)(struct pci_host_bridge *),
473 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
476 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
477 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
478 * buses below host bridges or subtractive decode bridges) go in the list.
479 * Use pci_bus_for_each_resource() to iterate through all the resources.
483 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
484 * and there's no way to program the bridge with the details of the window.
485 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
486 * decode bit set, because they are explicit and can be programmed with _SRS.
488 #define PCI_SUBTRACTIVE_DECODE 0x1
490 struct pci_bus_resource {
491 struct list_head list;
492 struct resource *res;
496 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
499 struct list_head node; /* node in list of buses */
500 struct pci_bus *parent; /* parent bus this bridge is on */
501 struct list_head children; /* list of child buses */
502 struct list_head devices; /* list of devices on this bus */
503 struct pci_dev *self; /* bridge device as seen by parent */
504 struct list_head slots; /* list of slots on this bus;
505 protected by pci_slot_mutex */
506 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
507 struct list_head resources; /* address space routed to this bus */
508 struct resource busn_res; /* bus numbers routed to this bus */
510 struct pci_ops *ops; /* configuration access functions */
511 struct msi_controller *msi; /* MSI controller */
512 void *sysdata; /* hook for sys-specific extension */
513 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
515 unsigned char number; /* bus number */
516 unsigned char primary; /* number of primary bridge */
517 unsigned char max_bus_speed; /* enum pci_bus_speed */
518 unsigned char cur_bus_speed; /* enum pci_bus_speed */
519 #ifdef CONFIG_PCI_DOMAINS_GENERIC
525 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
526 pci_bus_flags_t bus_flags; /* inherited by child buses */
527 struct device *bridge;
529 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
530 struct bin_attribute *legacy_mem; /* legacy mem */
531 unsigned int is_added:1;
534 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
537 * Returns true if the PCI bus is root (behind host-PCI bridge),
540 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
541 * This is incorrect because "virtual" buses added for SR-IOV (via
542 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
544 static inline bool pci_is_root_bus(struct pci_bus *pbus)
546 return !(pbus->parent);
550 * pci_is_bridge - check if the PCI device is a bridge
553 * Return true if the PCI device is bridge whether it has subordinate
556 static inline bool pci_is_bridge(struct pci_dev *dev)
558 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
559 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
562 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
564 dev = pci_physfn(dev);
565 if (pci_is_root_bus(dev->bus))
568 return dev->bus->self;
571 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
572 void pci_put_host_bridge_device(struct device *dev);
574 #ifdef CONFIG_PCI_MSI
575 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
577 return pci_dev->msi_enabled || pci_dev->msix_enabled;
580 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
584 * Error values that may be returned by PCI functions.
586 #define PCIBIOS_SUCCESSFUL 0x00
587 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
588 #define PCIBIOS_BAD_VENDOR_ID 0x83
589 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
590 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
591 #define PCIBIOS_SET_FAILED 0x88
592 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
595 * Translate above to generic errno for passing back through non-PCI code.
597 static inline int pcibios_err_to_errno(int err)
599 if (err <= PCIBIOS_SUCCESSFUL)
600 return err; /* Assume already errno */
603 case PCIBIOS_FUNC_NOT_SUPPORTED:
605 case PCIBIOS_BAD_VENDOR_ID:
607 case PCIBIOS_DEVICE_NOT_FOUND:
609 case PCIBIOS_BAD_REGISTER_NUMBER:
611 case PCIBIOS_SET_FAILED:
613 case PCIBIOS_BUFFER_TOO_SMALL:
620 /* Low-level architecture-dependent routines */
623 int (*add_bus)(struct pci_bus *bus);
624 void (*remove_bus)(struct pci_bus *bus);
625 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
626 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
627 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
631 * ACPI needs to be able to access PCI config space before we've done a
632 * PCI bus scan and created pci_bus structures.
634 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
635 int reg, int len, u32 *val);
636 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
637 int reg, int len, u32 val);
639 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
640 typedef u64 pci_bus_addr_t;
642 typedef u32 pci_bus_addr_t;
645 struct pci_bus_region {
646 pci_bus_addr_t start;
651 spinlock_t lock; /* protects list, index */
652 struct list_head list; /* for IDs added at runtime */
657 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
658 * a set of callbacks in struct pci_error_handlers, that device driver
659 * will be notified of PCI bus errors, and will be driven to recovery
660 * when an error occurs.
663 typedef unsigned int __bitwise pci_ers_result_t;
665 enum pci_ers_result {
666 /* no result/none/not supported in device driver */
667 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
669 /* Device driver can recover without slot reset */
670 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
672 /* Device driver wants slot to be reset. */
673 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
675 /* Device has completely failed, is unrecoverable */
676 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
678 /* Device driver is fully recovered and operational */
679 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
681 /* No AER capabilities registered for the driver */
682 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
685 /* PCI bus error event callbacks */
686 struct pci_error_handlers {
687 /* PCI bus error detected on this device */
688 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
689 enum pci_channel_state error);
691 /* MMIO has been re-enabled, but not DMA */
692 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
694 /* PCI slot has been reset */
695 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
697 /* PCI function reset prepare or completed */
698 void (*reset_notify)(struct pci_dev *dev, bool prepare);
700 /* Device driver may resume normal operations */
701 void (*resume)(struct pci_dev *dev);
707 struct list_head node;
709 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
710 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
711 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
712 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
713 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
714 int (*resume_early) (struct pci_dev *dev);
715 int (*resume) (struct pci_dev *dev); /* Device woken up */
716 void (*shutdown) (struct pci_dev *dev);
717 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
718 const struct pci_error_handlers *err_handler;
719 struct device_driver driver;
720 struct pci_dynids dynids;
723 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
726 * PCI_DEVICE - macro used to describe a specific pci device
727 * @vend: the 16 bit PCI Vendor ID
728 * @dev: the 16 bit PCI Device ID
730 * This macro is used to create a struct pci_device_id that matches a
731 * specific device. The subvendor and subdevice fields will be set to
734 #define PCI_DEVICE(vend,dev) \
735 .vendor = (vend), .device = (dev), \
736 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
739 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
740 * @vend: the 16 bit PCI Vendor ID
741 * @dev: the 16 bit PCI Device ID
742 * @subvend: the 16 bit PCI Subvendor ID
743 * @subdev: the 16 bit PCI Subdevice ID
745 * This macro is used to create a struct pci_device_id that matches a
746 * specific device with subsystem information.
748 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
749 .vendor = (vend), .device = (dev), \
750 .subvendor = (subvend), .subdevice = (subdev)
753 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
754 * @dev_class: the class, subclass, prog-if triple for this device
755 * @dev_class_mask: the class mask for this device
757 * This macro is used to create a struct pci_device_id that matches a
758 * specific PCI class. The vendor, device, subvendor, and subdevice
759 * fields will be set to PCI_ANY_ID.
761 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
762 .class = (dev_class), .class_mask = (dev_class_mask), \
763 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
764 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
767 * PCI_VDEVICE - macro used to describe a specific pci device in short form
768 * @vend: the vendor name
769 * @dev: the 16 bit PCI Device ID
771 * This macro is used to create a struct pci_device_id that matches a
772 * specific PCI device. The subvendor, and subdevice fields will be set
773 * to PCI_ANY_ID. The macro allows the next field to follow as the device
777 #define PCI_VDEVICE(vend, dev) \
778 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
779 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
782 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
783 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
784 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
785 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
786 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
787 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
788 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
791 /* these external functions are only available when PCI support is enabled */
794 extern unsigned int pci_flags;
796 static inline void pci_set_flags(int flags) { pci_flags = flags; }
797 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
798 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
799 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
801 void pcie_bus_configure_settings(struct pci_bus *bus);
803 enum pcie_bus_config_types {
804 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
805 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
806 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
807 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
808 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
811 extern enum pcie_bus_config_types pcie_bus_config;
813 extern struct bus_type pci_bus_type;
815 /* Do NOT directly access these two variables, unless you are arch-specific PCI
816 * code, or PCI core code. */
817 extern struct list_head pci_root_buses; /* list of all known PCI buses */
818 /* Some device drivers need know if PCI is initiated */
819 int no_pci_devices(void);
821 void pcibios_resource_survey_bus(struct pci_bus *bus);
822 void pcibios_bus_add_device(struct pci_dev *pdev);
823 void pcibios_add_bus(struct pci_bus *bus);
824 void pcibios_remove_bus(struct pci_bus *bus);
825 void pcibios_fixup_bus(struct pci_bus *);
826 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
827 /* Architecture-specific versions may override this (weak) */
828 char *pcibios_setup(char *str);
830 /* Used only when drivers/pci/setup.c is used */
831 resource_size_t pcibios_align_resource(void *, const struct resource *,
834 void pcibios_update_irq(struct pci_dev *, int irq);
836 /* Weak but can be overriden by arch */
837 void pci_fixup_cardbus(struct pci_bus *);
839 /* Generic PCI functions used internally */
841 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
842 struct resource *res);
843 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
844 struct pci_bus_region *region);
845 void pcibios_scan_specific_bus(int busn);
846 struct pci_bus *pci_find_bus(int domain, int busnr);
847 void pci_bus_add_devices(const struct pci_bus *bus);
848 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
849 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
850 struct pci_ops *ops, void *sysdata,
851 struct list_head *resources);
852 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
853 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
854 void pci_bus_release_busn_res(struct pci_bus *b);
855 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
856 struct pci_ops *ops, void *sysdata,
857 struct list_head *resources,
858 struct msi_controller *msi);
859 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
860 struct pci_ops *ops, void *sysdata,
861 struct list_head *resources);
862 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
864 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
865 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
867 struct hotplug_slot *hotplug);
868 void pci_destroy_slot(struct pci_slot *slot);
870 void pci_dev_assign_slot(struct pci_dev *dev);
872 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
874 int pci_scan_slot(struct pci_bus *bus, int devfn);
875 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
876 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
877 unsigned int pci_scan_child_bus(struct pci_bus *bus);
878 void pci_bus_add_device(struct pci_dev *dev);
879 void pci_read_bridge_bases(struct pci_bus *child);
880 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
881 struct resource *res);
882 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
883 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
884 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
885 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
886 struct pci_dev *pci_dev_get(struct pci_dev *dev);
887 void pci_dev_put(struct pci_dev *dev);
888 void pci_remove_bus(struct pci_bus *b);
889 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
890 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
891 void pci_stop_root_bus(struct pci_bus *bus);
892 void pci_remove_root_bus(struct pci_bus *bus);
893 void pci_setup_cardbus(struct pci_bus *bus);
894 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
895 void pci_sort_breadthfirst(void);
896 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
897 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
899 /* Generic PCI functions exported to card drivers */
901 enum pci_lost_interrupt_reason {
902 PCI_LOST_IRQ_NO_INFORMATION = 0,
903 PCI_LOST_IRQ_DISABLE_MSI,
904 PCI_LOST_IRQ_DISABLE_MSIX,
905 PCI_LOST_IRQ_DISABLE_ACPI,
907 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
908 int pci_find_capability(struct pci_dev *dev, int cap);
909 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
910 int pci_find_ext_capability(struct pci_dev *dev, int cap);
911 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
912 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
913 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
914 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
916 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
917 struct pci_dev *from);
918 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
919 unsigned int ss_vendor, unsigned int ss_device,
920 struct pci_dev *from);
921 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
922 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
924 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
927 return pci_get_domain_bus_and_slot(0, bus, devfn);
929 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
930 int pci_dev_present(const struct pci_device_id *ids);
932 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
934 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
935 int where, u16 *val);
936 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
937 int where, u32 *val);
938 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
940 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
942 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
945 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
946 int where, int size, u32 *val);
947 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
948 int where, int size, u32 val);
949 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
950 int where, int size, u32 *val);
951 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
952 int where, int size, u32 val);
954 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
956 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
957 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
958 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
959 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
960 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
961 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
963 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
964 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
965 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
966 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
967 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
969 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
972 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
975 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
978 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
981 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
984 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
987 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
990 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
993 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
996 /* user-space driven config access */
997 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
998 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
999 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1000 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1001 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1002 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1004 int __must_check pci_enable_device(struct pci_dev *dev);
1005 int __must_check pci_enable_device_io(struct pci_dev *dev);
1006 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1007 int __must_check pci_reenable_device(struct pci_dev *);
1008 int __must_check pcim_enable_device(struct pci_dev *pdev);
1009 void pcim_pin_device(struct pci_dev *pdev);
1011 static inline int pci_is_enabled(struct pci_dev *pdev)
1013 return (atomic_read(&pdev->enable_cnt) > 0);
1016 static inline int pci_is_managed(struct pci_dev *pdev)
1018 return pdev->is_managed;
1021 void pci_disable_device(struct pci_dev *dev);
1023 extern unsigned int pcibios_max_latency;
1024 void pci_set_master(struct pci_dev *dev);
1025 void pci_clear_master(struct pci_dev *dev);
1027 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1028 int pci_set_cacheline_size(struct pci_dev *dev);
1029 #define HAVE_PCI_SET_MWI
1030 int __must_check pci_set_mwi(struct pci_dev *dev);
1031 int pci_try_set_mwi(struct pci_dev *dev);
1032 void pci_clear_mwi(struct pci_dev *dev);
1033 void pci_intx(struct pci_dev *dev, int enable);
1034 bool pci_intx_mask_supported(struct pci_dev *dev);
1035 bool pci_check_and_mask_intx(struct pci_dev *dev);
1036 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1037 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1038 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1039 int pcix_get_max_mmrbc(struct pci_dev *dev);
1040 int pcix_get_mmrbc(struct pci_dev *dev);
1041 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1042 int pcie_get_readrq(struct pci_dev *dev);
1043 int pcie_set_readrq(struct pci_dev *dev, int rq);
1044 int pcie_get_mps(struct pci_dev *dev);
1045 int pcie_set_mps(struct pci_dev *dev, int mps);
1046 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1047 enum pcie_link_width *width);
1048 void pcie_flr(struct pci_dev *dev);
1049 int __pci_reset_function(struct pci_dev *dev);
1050 int __pci_reset_function_locked(struct pci_dev *dev);
1051 int pci_reset_function(struct pci_dev *dev);
1052 int pci_try_reset_function(struct pci_dev *dev);
1053 int pci_probe_reset_slot(struct pci_slot *slot);
1054 int pci_reset_slot(struct pci_slot *slot);
1055 int pci_try_reset_slot(struct pci_slot *slot);
1056 int pci_probe_reset_bus(struct pci_bus *bus);
1057 int pci_reset_bus(struct pci_bus *bus);
1058 int pci_try_reset_bus(struct pci_bus *bus);
1059 void pci_reset_secondary_bus(struct pci_dev *dev);
1060 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1061 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1062 void pci_update_resource(struct pci_dev *dev, int resno);
1063 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1064 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1065 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1066 bool pci_device_is_present(struct pci_dev *pdev);
1067 void pci_ignore_hotplug(struct pci_dev *dev);
1069 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1070 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1071 const char *fmt, ...);
1072 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1074 /* ROM control related routines */
1075 int pci_enable_rom(struct pci_dev *pdev);
1076 void pci_disable_rom(struct pci_dev *pdev);
1077 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1078 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1079 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1080 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1082 /* Power management related routines */
1083 int pci_save_state(struct pci_dev *dev);
1084 void pci_restore_state(struct pci_dev *dev);
1085 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1086 int pci_load_saved_state(struct pci_dev *dev,
1087 struct pci_saved_state *state);
1088 int pci_load_and_free_saved_state(struct pci_dev *dev,
1089 struct pci_saved_state **state);
1090 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1091 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1093 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1094 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1095 u16 cap, unsigned int size);
1096 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1097 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1098 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1099 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1100 void pci_pme_active(struct pci_dev *dev, bool enable);
1101 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1102 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1103 int pci_prepare_to_sleep(struct pci_dev *dev);
1104 int pci_back_from_sleep(struct pci_dev *dev);
1105 bool pci_dev_run_wake(struct pci_dev *dev);
1106 bool pci_check_pme_status(struct pci_dev *dev);
1107 void pci_pme_wakeup_bus(struct pci_bus *bus);
1108 void pci_d3cold_enable(struct pci_dev *dev);
1109 void pci_d3cold_disable(struct pci_dev *dev);
1111 /* PCI Virtual Channel */
1112 int pci_save_vc_state(struct pci_dev *dev);
1113 void pci_restore_vc_state(struct pci_dev *dev);
1114 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1116 /* For use by arch with custom probe code */
1117 void set_pcie_port_type(struct pci_dev *pdev);
1118 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1120 /* Functions for PCI Hotplug drivers to use */
1121 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1122 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1123 unsigned int pci_rescan_bus(struct pci_bus *bus);
1124 void pci_lock_rescan_remove(void);
1125 void pci_unlock_rescan_remove(void);
1127 /* Vital product data routines */
1128 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1129 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1130 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1132 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1133 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1134 void pci_bus_assign_resources(const struct pci_bus *bus);
1135 void pci_bus_claim_resources(struct pci_bus *bus);
1136 void pci_bus_size_bridges(struct pci_bus *bus);
1137 int pci_claim_resource(struct pci_dev *, int);
1138 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1139 void pci_assign_unassigned_resources(void);
1140 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1141 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1142 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1143 void pdev_enable_device(struct pci_dev *);
1144 int pci_enable_resources(struct pci_dev *, int mask);
1145 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1146 int (*)(const struct pci_dev *, u8, u8));
1147 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1148 #define HAVE_PCI_REQ_REGIONS 2
1149 int __must_check pci_request_regions(struct pci_dev *, const char *);
1150 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1151 void pci_release_regions(struct pci_dev *);
1152 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1153 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1154 void pci_release_region(struct pci_dev *, int);
1155 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1156 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1157 void pci_release_selected_regions(struct pci_dev *, int);
1159 /* drivers/pci/bus.c */
1160 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1161 void pci_bus_put(struct pci_bus *bus);
1162 void pci_add_resource(struct list_head *resources, struct resource *res);
1163 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1164 resource_size_t offset);
1165 void pci_free_resource_list(struct list_head *resources);
1166 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1167 unsigned int flags);
1168 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1169 void pci_bus_remove_resources(struct pci_bus *bus);
1170 int devm_request_pci_bus_resources(struct device *dev,
1171 struct list_head *resources);
1173 #define pci_bus_for_each_resource(bus, res, i) \
1175 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1178 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1179 struct resource *res, resource_size_t size,
1180 resource_size_t align, resource_size_t min,
1181 unsigned long type_mask,
1182 resource_size_t (*alignf)(void *,
1183 const struct resource *,
1189 int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1190 unsigned long pci_address_to_pio(phys_addr_t addr);
1191 phys_addr_t pci_pio_to_address(unsigned long pio);
1192 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1193 void pci_unmap_iospace(struct resource *res);
1194 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1195 resource_size_t offset,
1196 resource_size_t size);
1197 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1198 struct resource *res);
1200 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1202 struct pci_bus_region region;
1204 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1205 return region.start;
1208 /* Proper probing supporting hot-pluggable devices */
1209 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1210 const char *mod_name);
1213 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1215 #define pci_register_driver(driver) \
1216 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1218 void pci_unregister_driver(struct pci_driver *dev);
1221 * module_pci_driver() - Helper macro for registering a PCI driver
1222 * @__pci_driver: pci_driver struct
1224 * Helper macro for PCI drivers which do not do anything special in module
1225 * init/exit. This eliminates a lot of boilerplate. Each module may only
1226 * use this macro once, and calling it replaces module_init() and module_exit()
1228 #define module_pci_driver(__pci_driver) \
1229 module_driver(__pci_driver, pci_register_driver, \
1230 pci_unregister_driver)
1233 * builtin_pci_driver() - Helper macro for registering a PCI driver
1234 * @__pci_driver: pci_driver struct
1236 * Helper macro for PCI drivers which do not do anything special in their
1237 * init code. This eliminates a lot of boilerplate. Each driver may only
1238 * use this macro once, and calling it replaces device_initcall(...)
1240 #define builtin_pci_driver(__pci_driver) \
1241 builtin_driver(__pci_driver, pci_register_driver)
1243 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1244 int pci_add_dynid(struct pci_driver *drv,
1245 unsigned int vendor, unsigned int device,
1246 unsigned int subvendor, unsigned int subdevice,
1247 unsigned int class, unsigned int class_mask,
1248 unsigned long driver_data);
1249 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1250 struct pci_dev *dev);
1251 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1254 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1256 int pci_cfg_space_size(struct pci_dev *dev);
1257 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1258 void pci_setup_bridge(struct pci_bus *bus);
1259 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1260 unsigned long type);
1261 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1263 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1264 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1266 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1267 unsigned int command_bits, u32 flags);
1269 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */
1270 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */
1271 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */
1272 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */
1273 #define PCI_IRQ_ALL_TYPES \
1274 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1276 /* kmem_cache style wrapper around pci_alloc_consistent() */
1278 #include <linux/pci-dma.h>
1279 #include <linux/dmapool.h>
1281 #define pci_pool dma_pool
1282 #define pci_pool_create(name, pdev, size, align, allocation) \
1283 dma_pool_create(name, &pdev->dev, size, align, allocation)
1284 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1285 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1286 #define pci_pool_zalloc(pool, flags, handle) \
1287 dma_pool_zalloc(pool, flags, handle)
1288 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1291 u32 vector; /* kernel uses to write allocated vector */
1292 u16 entry; /* driver uses to specify entry, OS writes */
1295 #ifdef CONFIG_PCI_MSI
1296 int pci_msi_vec_count(struct pci_dev *dev);
1297 void pci_disable_msi(struct pci_dev *dev);
1298 int pci_msix_vec_count(struct pci_dev *dev);
1299 void pci_disable_msix(struct pci_dev *dev);
1300 void pci_restore_msi_state(struct pci_dev *dev);
1301 int pci_msi_enabled(void);
1302 int pci_enable_msi(struct pci_dev *dev);
1303 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1304 int minvec, int maxvec);
1305 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1306 struct msix_entry *entries, int nvec)
1308 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1313 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1314 unsigned int max_vecs, unsigned int flags,
1315 const struct irq_affinity *affd);
1317 void pci_free_irq_vectors(struct pci_dev *dev);
1318 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1319 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1320 int pci_irq_get_node(struct pci_dev *pdev, int vec);
1323 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1324 static inline void pci_disable_msi(struct pci_dev *dev) { }
1325 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1326 static inline void pci_disable_msix(struct pci_dev *dev) { }
1327 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1328 static inline int pci_msi_enabled(void) { return 0; }
1329 static inline int pci_enable_msi(struct pci_dev *dev)
1331 static inline int pci_enable_msix_range(struct pci_dev *dev,
1332 struct msix_entry *entries, int minvec, int maxvec)
1334 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1335 struct msix_entry *entries, int nvec)
1339 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1340 unsigned int max_vecs, unsigned int flags,
1341 const struct irq_affinity *aff_desc)
1343 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1348 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1352 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1354 if (WARN_ON_ONCE(nr > 0))
1358 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1361 return cpu_possible_mask;
1364 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1366 return first_online_node;
1371 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1372 unsigned int max_vecs, unsigned int flags)
1374 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1378 #ifdef CONFIG_PCIEPORTBUS
1379 extern bool pcie_ports_disabled;
1380 extern bool pcie_ports_auto;
1382 #define pcie_ports_disabled true
1383 #define pcie_ports_auto false
1386 #ifdef CONFIG_PCIEASPM
1387 bool pcie_aspm_support_enabled(void);
1389 static inline bool pcie_aspm_support_enabled(void) { return false; }
1392 #ifdef CONFIG_PCIEAER
1393 void pci_no_aer(void);
1394 bool pci_aer_available(void);
1395 int pci_aer_init(struct pci_dev *dev);
1397 static inline void pci_no_aer(void) { }
1398 static inline bool pci_aer_available(void) { return false; }
1399 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1402 #ifdef CONFIG_PCIE_ECRC
1403 void pcie_set_ecrc_checking(struct pci_dev *dev);
1404 void pcie_ecrc_get_policy(char *str);
1406 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1407 static inline void pcie_ecrc_get_policy(char *str) { }
1410 #ifdef CONFIG_HT_IRQ
1411 /* The functions a driver should call */
1412 int ht_create_irq(struct pci_dev *dev, int idx);
1413 void ht_destroy_irq(unsigned int irq);
1414 #endif /* CONFIG_HT_IRQ */
1416 #ifdef CONFIG_PCI_ATS
1417 /* Address Translation Service */
1418 void pci_ats_init(struct pci_dev *dev);
1419 int pci_enable_ats(struct pci_dev *dev, int ps);
1420 void pci_disable_ats(struct pci_dev *dev);
1421 int pci_ats_queue_depth(struct pci_dev *dev);
1423 static inline void pci_ats_init(struct pci_dev *d) { }
1424 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1425 static inline void pci_disable_ats(struct pci_dev *d) { }
1426 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1429 #ifdef CONFIG_PCIE_PTM
1430 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1432 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1436 void pci_cfg_access_lock(struct pci_dev *dev);
1437 bool pci_cfg_access_trylock(struct pci_dev *dev);
1438 void pci_cfg_access_unlock(struct pci_dev *dev);
1441 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1442 * a PCI domain is defined to be a set of PCI buses which share
1443 * configuration space.
1445 #ifdef CONFIG_PCI_DOMAINS
1446 extern int pci_domains_supported;
1447 int pci_get_new_domain_nr(void);
1449 enum { pci_domains_supported = 0 };
1450 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1451 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1452 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1453 #endif /* CONFIG_PCI_DOMAINS */
1456 * Generic implementation for PCI domain support. If your
1457 * architecture does not need custom management of PCI
1458 * domains then this implementation will be used
1460 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1461 static inline int pci_domain_nr(struct pci_bus *bus)
1463 return bus->domain_nr;
1466 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1468 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1471 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1474 /* some architectures require additional setup to direct VGA traffic */
1475 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1476 unsigned int command_bits, u32 flags);
1477 void pci_register_set_vga_state(arch_set_vga_state_t func);
1480 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1482 return pci_request_selected_regions(pdev,
1483 pci_select_bars(pdev, IORESOURCE_IO), name);
1487 pci_release_io_regions(struct pci_dev *pdev)
1489 return pci_release_selected_regions(pdev,
1490 pci_select_bars(pdev, IORESOURCE_IO));
1494 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1496 return pci_request_selected_regions(pdev,
1497 pci_select_bars(pdev, IORESOURCE_MEM), name);
1501 pci_release_mem_regions(struct pci_dev *pdev)
1503 return pci_release_selected_regions(pdev,
1504 pci_select_bars(pdev, IORESOURCE_MEM));
1507 #else /* CONFIG_PCI is not enabled */
1509 static inline void pci_set_flags(int flags) { }
1510 static inline void pci_add_flags(int flags) { }
1511 static inline void pci_clear_flags(int flags) { }
1512 static inline int pci_has_flag(int flag) { return 0; }
1515 * If the system does not have PCI, clearly these return errors. Define
1516 * these as simple inline functions to avoid hair in drivers.
1519 #define _PCI_NOP(o, s, t) \
1520 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1522 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1524 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1525 _PCI_NOP(o, word, u16 x) \
1526 _PCI_NOP(o, dword, u32 x)
1527 _PCI_NOP_ALL(read, *)
1528 _PCI_NOP_ALL(write,)
1530 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1531 unsigned int device,
1532 struct pci_dev *from)
1535 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1536 unsigned int device,
1537 unsigned int ss_vendor,
1538 unsigned int ss_device,
1539 struct pci_dev *from)
1542 static inline struct pci_dev *pci_get_class(unsigned int class,
1543 struct pci_dev *from)
1546 #define pci_dev_present(ids) (0)
1547 #define no_pci_devices() (1)
1548 #define pci_dev_put(dev) do { } while (0)
1550 static inline void pci_set_master(struct pci_dev *dev) { }
1551 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1552 static inline void pci_disable_device(struct pci_dev *dev) { }
1553 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1555 static inline int __pci_register_driver(struct pci_driver *drv,
1556 struct module *owner)
1558 static inline int pci_register_driver(struct pci_driver *drv)
1560 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1561 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1563 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1566 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1569 /* Power management related routines */
1570 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1571 static inline void pci_restore_state(struct pci_dev *dev) { }
1572 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1574 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1576 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1579 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1583 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1584 struct resource *res)
1586 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1588 static inline void pci_release_regions(struct pci_dev *dev) { }
1590 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1592 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1593 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1595 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1597 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1599 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1602 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1606 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1607 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1608 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1610 #define dev_is_pci(d) (false)
1611 #define dev_is_pf(d) (false)
1612 #endif /* CONFIG_PCI */
1614 /* Include architecture-dependent settings and functions */
1616 #include <asm/pci.h>
1618 /* These two functions provide almost identical functionality. Depennding
1619 * on the architecture, one will be implemented as a wrapper around the
1620 * other (in drivers/pci/mmap.c).
1622 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1623 * is expected to be an offset within that region.
1625 * pci_mmap_page_range() is the legacy architecture-specific interface,
1626 * which accepts a "user visible" resource address converted by
1627 * pci_resource_to_user(), as used in the legacy mmap() interface in
1630 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1631 struct vm_area_struct *vma,
1632 enum pci_mmap_state mmap_state, int write_combine);
1633 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1634 struct vm_area_struct *vma,
1635 enum pci_mmap_state mmap_state, int write_combine);
1637 #ifndef arch_can_pci_mmap_wc
1638 #define arch_can_pci_mmap_wc() 0
1641 #ifndef arch_can_pci_mmap_io
1642 #define arch_can_pci_mmap_io() 0
1643 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1645 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1648 #ifndef pci_root_bus_fwnode
1649 #define pci_root_bus_fwnode(bus) NULL
1652 /* these helpers provide future and backwards compatibility
1653 * for accessing popular PCI BAR info */
1654 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1655 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1656 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1657 #define pci_resource_len(dev,bar) \
1658 ((pci_resource_start((dev), (bar)) == 0 && \
1659 pci_resource_end((dev), (bar)) == \
1660 pci_resource_start((dev), (bar))) ? 0 : \
1662 (pci_resource_end((dev), (bar)) - \
1663 pci_resource_start((dev), (bar)) + 1))
1665 /* Similar to the helpers above, these manipulate per-pci_dev
1666 * driver-specific data. They are really just a wrapper around
1667 * the generic device structure functions of these calls.
1669 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1671 return dev_get_drvdata(&pdev->dev);
1674 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1676 dev_set_drvdata(&pdev->dev, data);
1679 /* If you want to know what to call your pci_dev, ask this function.
1680 * Again, it's a wrapper around the generic device.
1682 static inline const char *pci_name(const struct pci_dev *pdev)
1684 return dev_name(&pdev->dev);
1688 /* Some archs don't want to expose struct resource to userland as-is
1689 * in sysfs and /proc
1691 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1692 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1693 const struct resource *rsrc,
1694 resource_size_t *start, resource_size_t *end);
1696 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1697 const struct resource *rsrc, resource_size_t *start,
1698 resource_size_t *end)
1700 *start = rsrc->start;
1703 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1707 * The world is not perfect and supplies us with broken PCI devices.
1708 * For at least a part of these bugs we need a work-around, so both
1709 * generic (drivers/pci/quirks.c) and per-architecture code can define
1710 * fixup hooks to be called for particular buggy devices.
1714 u16 vendor; /* You can use PCI_ANY_ID here of course */
1715 u16 device; /* You can use PCI_ANY_ID here of course */
1716 u32 class; /* You can use PCI_ANY_ID here too */
1717 unsigned int class_shift; /* should be 0, 8, 16 */
1718 void (*hook)(struct pci_dev *dev);
1721 enum pci_fixup_pass {
1722 pci_fixup_early, /* Before probing BARs */
1723 pci_fixup_header, /* After reading configuration header */
1724 pci_fixup_final, /* Final phase of device fixups */
1725 pci_fixup_enable, /* pci_enable_device() time */
1726 pci_fixup_resume, /* pci_device_resume() */
1727 pci_fixup_suspend, /* pci_device_suspend() */
1728 pci_fixup_resume_early, /* pci_device_resume_early() */
1729 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1732 /* Anonymous variables would be nice... */
1733 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1734 class_shift, hook) \
1735 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1736 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1737 = { vendor, device, class, class_shift, hook };
1739 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1740 class_shift, hook) \
1741 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1742 hook, vendor, device, class, class_shift, hook)
1743 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1744 class_shift, hook) \
1745 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1746 hook, vendor, device, class, class_shift, hook)
1747 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1748 class_shift, hook) \
1749 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1750 hook, vendor, device, class, class_shift, hook)
1751 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1752 class_shift, hook) \
1753 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1754 hook, vendor, device, class, class_shift, hook)
1755 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1756 class_shift, hook) \
1757 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1758 resume##hook, vendor, device, class, \
1760 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1761 class_shift, hook) \
1762 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1763 resume_early##hook, vendor, device, \
1764 class, class_shift, hook)
1765 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1766 class_shift, hook) \
1767 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1768 suspend##hook, vendor, device, class, \
1770 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1771 class_shift, hook) \
1772 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1773 suspend_late##hook, vendor, device, \
1774 class, class_shift, hook)
1776 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1777 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1778 hook, vendor, device, PCI_ANY_ID, 0, hook)
1779 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1780 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1781 hook, vendor, device, PCI_ANY_ID, 0, hook)
1782 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1783 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1784 hook, vendor, device, PCI_ANY_ID, 0, hook)
1785 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1786 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1787 hook, vendor, device, PCI_ANY_ID, 0, hook)
1788 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1789 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1790 resume##hook, vendor, device, \
1791 PCI_ANY_ID, 0, hook)
1792 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1793 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1794 resume_early##hook, vendor, device, \
1795 PCI_ANY_ID, 0, hook)
1796 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1797 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1798 suspend##hook, vendor, device, \
1799 PCI_ANY_ID, 0, hook)
1800 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1801 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1802 suspend_late##hook, vendor, device, \
1803 PCI_ANY_ID, 0, hook)
1805 #ifdef CONFIG_PCI_QUIRKS
1806 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1807 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1808 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1810 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1811 struct pci_dev *dev) { }
1812 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1817 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1823 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1824 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1825 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1826 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1827 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1829 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1831 extern int pci_pci_problems;
1832 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1833 #define PCIPCI_TRITON 2
1834 #define PCIPCI_NATOMA 4
1835 #define PCIPCI_VIAETBF 8
1836 #define PCIPCI_VSFX 16
1837 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1838 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1840 extern unsigned long pci_cardbus_io_size;
1841 extern unsigned long pci_cardbus_mem_size;
1842 extern u8 pci_dfl_cache_line_size;
1843 extern u8 pci_cache_line_size;
1845 extern unsigned long pci_hotplug_io_size;
1846 extern unsigned long pci_hotplug_mem_size;
1847 extern unsigned long pci_hotplug_bus_size;
1849 /* Architecture-specific versions may override these (weak) */
1850 void pcibios_disable_device(struct pci_dev *dev);
1851 void pcibios_set_master(struct pci_dev *dev);
1852 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1853 enum pcie_reset_state state);
1854 int pcibios_add_device(struct pci_dev *dev);
1855 void pcibios_release_device(struct pci_dev *dev);
1856 void pcibios_penalize_isa_irq(int irq, int active);
1857 int pcibios_alloc_irq(struct pci_dev *dev);
1858 void pcibios_free_irq(struct pci_dev *dev);
1860 #ifdef CONFIG_HIBERNATE_CALLBACKS
1861 extern struct dev_pm_ops pcibios_pm_ops;
1864 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1865 void __init pci_mmcfg_early_init(void);
1866 void __init pci_mmcfg_late_init(void);
1868 static inline void pci_mmcfg_early_init(void) { }
1869 static inline void pci_mmcfg_late_init(void) { }
1872 int pci_ext_cfg_avail(void);
1874 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1875 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1877 #ifdef CONFIG_PCI_IOV
1878 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1879 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1881 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1882 void pci_disable_sriov(struct pci_dev *dev);
1883 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1884 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1885 int pci_num_vf(struct pci_dev *dev);
1886 int pci_vfs_assigned(struct pci_dev *dev);
1887 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1888 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1889 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1891 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1895 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1899 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1901 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1905 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1906 int id, int reset) { }
1907 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1908 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1909 static inline int pci_vfs_assigned(struct pci_dev *dev)
1911 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1913 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1915 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1919 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1920 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1921 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1925 * pci_pcie_cap - get the saved PCIe capability offset
1928 * PCIe capability offset is calculated at PCI device initialization
1929 * time and saved in the data structure. This function returns saved
1930 * PCIe capability offset. Using this instead of pci_find_capability()
1931 * reduces unnecessary search in the PCI configuration space. If you
1932 * need to calculate PCIe capability offset from raw device for some
1933 * reasons, please use pci_find_capability() instead.
1935 static inline int pci_pcie_cap(struct pci_dev *dev)
1937 return dev->pcie_cap;
1941 * pci_is_pcie - check if the PCI device is PCI Express capable
1944 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1946 static inline bool pci_is_pcie(struct pci_dev *dev)
1948 return pci_pcie_cap(dev);
1952 * pcie_caps_reg - get the PCIe Capabilities Register
1955 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1957 return dev->pcie_flags_reg;
1961 * pci_pcie_type - get the PCIe device/port type
1964 static inline int pci_pcie_type(const struct pci_dev *dev)
1966 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1969 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
1972 if (!pci_is_pcie(dev))
1974 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
1976 if (!dev->bus->self)
1978 dev = dev->bus->self;
1983 void pci_request_acs(void);
1984 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1985 bool pci_acs_path_enabled(struct pci_dev *start,
1986 struct pci_dev *end, u16 acs_flags);
1988 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1989 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1991 /* Large Resource Data Type Tag Item Names */
1992 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1993 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1994 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1996 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1997 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1998 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2000 /* Small Resource Data Type Tag Item Names */
2001 #define PCI_VPD_STIN_END 0x0f /* End */
2003 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2005 #define PCI_VPD_SRDT_TIN_MASK 0x78
2006 #define PCI_VPD_SRDT_LEN_MASK 0x07
2007 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2009 #define PCI_VPD_LRDT_TAG_SIZE 3
2010 #define PCI_VPD_SRDT_TAG_SIZE 1
2012 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2014 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2015 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2016 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2017 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2020 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2021 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2023 * Returns the extracted Large Resource Data Type length.
2025 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2027 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2031 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2032 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2034 * Returns the extracted Large Resource Data Type Tag item.
2036 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2038 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2042 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2043 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2045 * Returns the extracted Small Resource Data Type length.
2047 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2049 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2053 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2054 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2056 * Returns the extracted Small Resource Data Type Tag Item.
2058 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2060 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2064 * pci_vpd_info_field_size - Extracts the information field length
2065 * @lrdt: Pointer to the beginning of an information field header
2067 * Returns the extracted information field length.
2069 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2071 return info_field[2];
2075 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2076 * @buf: Pointer to buffered vpd data
2077 * @off: The offset into the buffer at which to begin the search
2078 * @len: The length of the vpd buffer
2079 * @rdt: The Resource Data Type to search for
2081 * Returns the index where the Resource Data Type was found or
2082 * -ENOENT otherwise.
2084 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2087 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2088 * @buf: Pointer to buffered vpd data
2089 * @off: The offset into the buffer at which to begin the search
2090 * @len: The length of the buffer area, relative to off, in which to search
2091 * @kw: The keyword to search for
2093 * Returns the index where the information field keyword was found or
2094 * -ENOENT otherwise.
2096 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2097 unsigned int len, const char *kw);
2099 /* PCI <-> OF binding helpers */
2103 void pci_set_of_node(struct pci_dev *dev);
2104 void pci_release_of_node(struct pci_dev *dev);
2105 void pci_set_bus_of_node(struct pci_bus *bus);
2106 void pci_release_bus_of_node(struct pci_bus *bus);
2107 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2109 /* Arch may override this (weak) */
2110 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2112 static inline struct device_node *
2113 pci_device_to_OF_node(const struct pci_dev *pdev)
2115 return pdev ? pdev->dev.of_node : NULL;
2118 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2120 return bus ? bus->dev.of_node : NULL;
2123 #else /* CONFIG_OF */
2124 static inline void pci_set_of_node(struct pci_dev *dev) { }
2125 static inline void pci_release_of_node(struct pci_dev *dev) { }
2126 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2127 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2128 static inline struct device_node *
2129 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2130 static inline struct irq_domain *
2131 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2132 #endif /* CONFIG_OF */
2135 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2138 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2140 static inline struct irq_domain *
2141 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2145 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2147 return pdev->dev.archdata.edev;
2151 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2152 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2153 int pci_for_each_dma_alias(struct pci_dev *pdev,
2154 int (*fn)(struct pci_dev *pdev,
2155 u16 alias, void *data), void *data);
2157 /* helper functions for operation of device flag */
2158 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2160 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2162 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2164 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2166 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2168 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2172 * pci_ari_enabled - query ARI forwarding status
2175 * Returns true if ARI forwarding is enabled.
2177 static inline bool pci_ari_enabled(struct pci_bus *bus)
2179 return bus->self && bus->self->ari_enabled;
2183 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2184 * @pdev: PCI device to check
2186 * Walk upwards from @pdev and check for each encountered bridge if it's part
2187 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2188 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2190 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2192 struct pci_dev *parent = pdev;
2194 if (pdev->is_thunderbolt)
2197 while ((parent = pci_upstream_bridge(parent)))
2198 if (parent->is_thunderbolt)
2204 /* provide the legacy pci_dma_* API */
2205 #include <linux/pci-dma-compat.h>
2207 #endif /* LINUX_PCI_H */