sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/cacheflush.h>
  57 #endif
  58 #include <sound/core.h>
  59 #include <sound/initval.h>
  60 #include <linux/vgaarb.h>
  61 #include <linux/vga_switcheroo.h>
  62 #include <linux/firmware.h>
  63 #include "hda_codec.h"
  64 #include "hda_controller.h"
  65 #include "hda_intel.h"
  66
  67 /* position fix mode */
  68 enum {
  69         POS_FIX_AUTO,
  70         POS_FIX_LPIB,
  71         POS_FIX_POSBUF,
  72         POS_FIX_VIACOMBO,
  73         POS_FIX_COMBO,
  74 };
  75
  76 /* Defines for ATI HD Audio support in SB450 south bridge */
  77 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  78 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  79
  80 /* Defines for Nvidia HDA support */
  81 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  82 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  83 #define NVIDIA_HDA_ISTRM_COH          0x4d
  84 #define NVIDIA_HDA_OSTRM_COH          0x4c
  85 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  86
  87 /* Defines for Intel SCH HDA snoop control */
  88 #define INTEL_SCH_HDA_DEVC      0x78
  89 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  90
  91 /* Define IN stream 0 FIFO size offset in VIA controller */
  92 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
  93 /* Define VIA HD Audio Device ID*/
  94 #define VIA_HDAC_DEVICE_ID              0x3288
  95
  96 /* max number of SDs */
  97 /* ICH, ATI and VIA have 4 playback and 4 capture */
  98 #define ICH6_NUM_CAPTURE        4
  99 #define ICH6_NUM_PLAYBACK       4
 100
 101 /* ULI has 6 playback and 5 capture */
 102 #define ULI_NUM_CAPTURE         5
 103 #define ULI_NUM_PLAYBACK        6
 104
 105 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 106 #define ATIHDMI_NUM_CAPTURE     0
 107 #define ATIHDMI_NUM_PLAYBACK    8
 108
 109 /* TERA has 4 playback and 3 capture */
 110 #define TERA_NUM_CAPTURE        3
 111 #define TERA_NUM_PLAYBACK       4
 112
 113
 114 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 115 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 116 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 117 static char *model[SNDRV_CARDS];
 118 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 119 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 120 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 121 static int probe_only[SNDRV_CARDS];
 122 static int jackpoll_ms[SNDRV_CARDS];
 123 static bool single_cmd;
 124 static int enable_msi = -1;
 125 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 126 static char *patch[SNDRV_CARDS];
 127 #endif
 128 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 129 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 130                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 131 #endif
 132
 133 module_param_array(index, int, NULL, 0444);
 134 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 135 module_param_array(id, charp, NULL, 0444);
 136 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 137 module_param_array(enable, bool, NULL, 0444);
 138 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 139 module_param_array(model, charp, NULL, 0444);
 140 MODULE_PARM_DESC(model, "Use the given board model.");
 141 module_param_array(position_fix, int, NULL, 0444);
 142 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 143                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
 144 module_param_array(bdl_pos_adj, int, NULL, 0644);
 145 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 146 module_param_array(probe_mask, int, NULL, 0444);
 147 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 148 module_param_array(probe_only, int, NULL, 0444);
 149 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 150 module_param_array(jackpoll_ms, int, NULL, 0444);
 151 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 152 module_param(single_cmd, bool, 0444);
 153 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 154                  "(for debugging only).");
 155 module_param(enable_msi, bint, 0444);
 156 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 157 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 158 module_param_array(patch, charp, NULL, 0444);
 159 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 160 #endif
 161 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 162 module_param_array(beep_mode, bool, NULL, 0444);
 163 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 164                             "(0=off, 1=on) (default=1).");
 165 #endif
 166
 167 #ifdef CONFIG_PM
 168 static int param_set_xint(const char *val, const struct kernel_param *kp);
 169 static struct kernel_param_ops param_ops_xint = {
 170         .set = param_set_xint,
 171         .get = param_get_int,
 172 };
 173 #define param_check_xint param_check_int
 174
 175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 176 module_param(power_save, xint, 0644);
 177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 178                  "(in second, 0 = disable).");
 179
 180 /* reset the HD-audio controller in power save mode.
 181  * this may give more power-saving, but will take longer time to
 182  * wake up.
 183  */
 184 static bool power_save_controller = 1;
 185 module_param(power_save_controller, bool, 0644);
 186 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 187 #else
 188 #define power_save      0
 189 #endif /* CONFIG_PM */
 190
 191 static int align_buffer_size = -1;
 192 module_param(align_buffer_size, bint, 0644);
 193 MODULE_PARM_DESC(align_buffer_size,
 194                 "Force buffer and period sizes to be multiple of 128 bytes.");
 195
 196 #ifdef CONFIG_X86
 197 static int hda_snoop = -1;
 198 module_param_named(snoop, hda_snoop, bint, 0444);
 199 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 200 #else
 201 #define hda_snoop               true
 202 #endif
 203
 204
 205 MODULE_LICENSE("GPL");
 206 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 207                          "{Intel, ICH6M},"
 208                          "{Intel, ICH7},"
 209                          "{Intel, ESB2},"
 210                          "{Intel, ICH8},"
 211                          "{Intel, ICH9},"
 212                          "{Intel, ICH10},"
 213                          "{Intel, PCH},"
 214                          "{Intel, CPT},"
 215                          "{Intel, PPT},"
 216                          "{Intel, LPT},"
 217                          "{Intel, LPT_LP},"
 218                          "{Intel, WPT_LP},"
 219                          "{Intel, SPT},"
 220                          "{Intel, SPT_LP},"
 221                          "{Intel, HPT},"
 222                          "{Intel, PBG},"
 223                          "{Intel, SCH},"
 224                          "{ATI, SB450},"
 225                          "{ATI, SB600},"
 226                          "{ATI, RS600},"
 227                          "{ATI, RS690},"
 228                          "{ATI, RS780},"
 229                          "{ATI, R600},"
 230                          "{ATI, RV630},"
 231                          "{ATI, RV610},"
 232                          "{ATI, RV670},"
 233                          "{ATI, RV635},"
 234                          "{ATI, RV620},"
 235                          "{ATI, RV770},"
 236                          "{VIA, VT8251},"
 237                          "{VIA, VT8237A},"
 238                          "{SiS, SIS966},"
 239                          "{ULI, M5461}}");
 240 MODULE_DESCRIPTION("Intel HDA driver");
 241
 242 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 243 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 244 #define SUPPORT_VGA_SWITCHEROO
 245 #endif
 246 #endif
 247
 248
 249 /*
 250  */
 251
 252 /* driver types */
 253 enum {
 254         AZX_DRIVER_ICH,
 255         AZX_DRIVER_PCH,
 256         AZX_DRIVER_SCH,
 257         AZX_DRIVER_HDMI,
 258         AZX_DRIVER_ATI,
 259         AZX_DRIVER_ATIHDMI,
 260         AZX_DRIVER_ATIHDMI_NS,
 261         AZX_DRIVER_VIA,
 262         AZX_DRIVER_SIS,
 263         AZX_DRIVER_ULI,
 264         AZX_DRIVER_NVIDIA,
 265         AZX_DRIVER_TERA,
 266         AZX_DRIVER_CTX,
 267         AZX_DRIVER_CTHDA,
 268         AZX_DRIVER_CMEDIA,
 269         AZX_DRIVER_GENERIC,
 270         AZX_NUM_DRIVERS, /* keep this as last entry */
 271 };
 272
 273 #define azx_get_snoop_type(chip) \
 274         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 275 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 276
 277 /* quirks for old Intel chipsets */
 278 #define AZX_DCAPS_INTEL_ICH \
 279         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 280
 281 /* quirks for Intel PCH */
 282 #define AZX_DCAPS_INTEL_PCH_NOPM \
 283         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 284          AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
 285
 286 #define AZX_DCAPS_INTEL_PCH \
 287         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
 288
 289 #define AZX_DCAPS_INTEL_HASWELL \
 290         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 291          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 292          AZX_DCAPS_SNOOP_TYPE(SCH))
 293
 294 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 295 #define AZX_DCAPS_INTEL_BROADWELL \
 296         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 297          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 298          AZX_DCAPS_SNOOP_TYPE(SCH))
 299
 300 #define AZX_DCAPS_INTEL_BAYTRAIL \
 301         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
 302
 303 #define AZX_DCAPS_INTEL_BRASWELL \
 304         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
 305
 306 #define AZX_DCAPS_INTEL_SKYLAKE \
 307         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 308          AZX_DCAPS_I915_POWERWELL)
 309
 310 /* quirks for ATI SB / AMD Hudson */
 311 #define AZX_DCAPS_PRESET_ATI_SB \
 312         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 313          AZX_DCAPS_SNOOP_TYPE(ATI))
 314
 315 /* quirks for ATI/AMD HDMI */
 316 #define AZX_DCAPS_PRESET_ATI_HDMI \
 317         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 318          AZX_DCAPS_NO_MSI64)
 319
 320 /* quirks for ATI HDMI with snoop off */
 321 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 322         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 323
 324 /* quirks for Nvidia */
 325 #define AZX_DCAPS_PRESET_NVIDIA \
 326         (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
 327          AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 328          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 329
 330 #define AZX_DCAPS_PRESET_CTHDA \
 331         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 332          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 333
 334 /*
 335  * VGA-switcher support
 336  */
 337 #ifdef SUPPORT_VGA_SWITCHEROO
 338 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 339 #else
 340 #define use_vga_switcheroo(chip)        0
 341 #endif
 342
 343 static char *driver_short_names[] = {
 344         [AZX_DRIVER_ICH] = "HDA Intel",
 345         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 346         [AZX_DRIVER_SCH] = "HDA Intel MID",
 347         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 348         [AZX_DRIVER_ATI] = "HDA ATI SB",
 349         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 350         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 351         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 352         [AZX_DRIVER_SIS] = "HDA SIS966",
 353         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 354         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 355         [AZX_DRIVER_TERA] = "HDA Teradici",
 356         [AZX_DRIVER_CTX] = "HDA Creative",
 357         [AZX_DRIVER_CTHDA] = "HDA Creative",
 358         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 359         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 360 };
 361
 362 #ifdef CONFIG_X86
 363 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 364 {
 365         int pages;
 366
 367         if (azx_snoop(chip))
 368                 return;
 369         if (!dmab || !dmab->area || !dmab->bytes)
 370                 return;
 371
 372 #ifdef CONFIG_SND_DMA_SGBUF
 373         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 374                 struct snd_sg_buf *sgbuf = dmab->private_data;
 375                 if (chip->driver_type == AZX_DRIVER_CMEDIA)
 376                         return; /* deal with only CORB/RIRB buffers */
 377                 if (on)
 378                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 379                 else
 380                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 381                 return;
 382         }
 383 #endif
 384
 385         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 386         if (on)
 387                 set_memory_wc((unsigned long)dmab->area, pages);
 388         else
 389                 set_memory_wb((unsigned long)dmab->area, pages);
 390 }
 391
 392 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 393                                  bool on)
 394 {
 395         __mark_pages_wc(chip, buf, on);
 396 }
 397 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 398                                    struct snd_pcm_substream *substream, bool on)
 399 {
 400         if (azx_dev->wc_marked != on) {
 401                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 402                 azx_dev->wc_marked = on;
 403         }
 404 }
 405 #else
 406 /* NOP for other archs */
 407 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 408                                  bool on)
 409 {
 410 }
 411 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 412                                    struct snd_pcm_substream *substream, bool on)
 413 {
 414 }
 415 #endif
 416
 417 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 418
 419 /*
 420  * initialize the PCI registers
 421  */
 422 /* update bits in a PCI register byte */
 423 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 424                             unsigned char mask, unsigned char val)
 425 {
 426         unsigned char data;
 427
 428         pci_read_config_byte(pci, reg, &data);
 429         data &= ~mask;
 430         data |= (val & mask);
 431         pci_write_config_byte(pci, reg, data);
 432 }
 433
 434 static void azx_init_pci(struct azx *chip)
 435 {
 436         int snoop_type = azx_get_snoop_type(chip);
 437
 438         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 439          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 440          * Ensuring these bits are 0 clears playback static on some HD Audio
 441          * codecs.
 442          * The PCI register TCSEL is defined in the Intel manuals.
 443          */
 444         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 445                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 446                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 447         }
 448
 449         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 450          * we need to enable snoop.
 451          */
 452         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 453                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 454                         azx_snoop(chip));
 455                 update_pci_byte(chip->pci,
 456                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 457                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 458         }
 459
 460         /* For NVIDIA HDA, enable snoop */
 461         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 462                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 463                         azx_snoop(chip));
 464                 update_pci_byte(chip->pci,
 465                                 NVIDIA_HDA_TRANSREG_ADDR,
 466                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 467                 update_pci_byte(chip->pci,
 468                                 NVIDIA_HDA_ISTRM_COH,
 469                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 470                 update_pci_byte(chip->pci,
 471                                 NVIDIA_HDA_OSTRM_COH,
 472                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 473         }
 474
 475         /* Enable SCH/PCH snoop if needed */
 476         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 477                 unsigned short snoop;
 478                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 479                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 480                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 481                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 482                         if (!azx_snoop(chip))
 483                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 484                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 485                         pci_read_config_word(chip->pci,
 486                                 INTEL_SCH_HDA_DEVC, &snoop);
 487                 }
 488                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 489                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 490                         "Disabled" : "Enabled");
 491         }
 492 }
 493
 494 /* calculate runtime delay from LPIB */
 495 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 496                                    unsigned int pos)
 497 {
 498         struct snd_pcm_substream *substream = azx_dev->substream;
 499         int stream = substream->stream;
 500         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 501         int delay;
 502
 503         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 504                 delay = pos - lpib_pos;
 505         else
 506                 delay = lpib_pos - pos;
 507         if (delay < 0) {
 508                 if (delay >= azx_dev->delay_negative_threshold)
 509                         delay = 0;
 510                 else
 511                         delay += azx_dev->bufsize;
 512         }
 513
 514         if (delay >= azx_dev->period_bytes) {
 515                 dev_info(chip->card->dev,
 516                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 517                          delay, azx_dev->period_bytes);
 518                 delay = 0;
 519                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 520                 chip->get_delay[stream] = NULL;
 521         }
 522
 523         return bytes_to_frames(substream->runtime, delay);
 524 }
 525
 526 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 527
 528 /* called from IRQ */
 529 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 530 {
 531         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 532         int ok;
 533
 534         ok = azx_position_ok(chip, azx_dev);
 535         if (ok == 1) {
 536                 azx_dev->irq_pending = 0;
 537                 return ok;
 538         } else if (ok == 0) {
 539                 /* bogus IRQ, process it later */
 540                 azx_dev->irq_pending = 1;
 541                 schedule_work(&hda->irq_pending_work);
 542         }
 543         return 0;
 544 }
 545
 546 /*
 547  * Check whether the current DMA position is acceptable for updating
 548  * periods.  Returns non-zero if it's OK.
 549  *
 550  * Many HD-audio controllers appear pretty inaccurate about
 551  * the update-IRQ timing.  The IRQ is issued before actually the
 552  * data is processed.  So, we need to process it afterwords in a
 553  * workqueue.
 554  */
 555 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 556 {
 557         struct snd_pcm_substream *substream = azx_dev->substream;
 558         int stream = substream->stream;
 559         u32 wallclk;
 560         unsigned int pos;
 561
 562         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
 563         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
 564                 return -1;      /* bogus (too early) interrupt */
 565
 566         if (chip->get_position[stream])
 567                 pos = chip->get_position[stream](chip, azx_dev);
 568         else { /* use the position buffer as default */
 569                 pos = azx_get_pos_posbuf(chip, azx_dev);
 570                 if (!pos || pos == (u32)-1) {
 571                         dev_info(chip->card->dev,
 572                                  "Invalid position buffer, using LPIB read method instead.\n");
 573                         chip->get_position[stream] = azx_get_pos_lpib;
 574                         pos = azx_get_pos_lpib(chip, azx_dev);
 575                         chip->get_delay[stream] = NULL;
 576                 } else {
 577                         chip->get_position[stream] = azx_get_pos_posbuf;
 578                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 579                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 580                 }
 581         }
 582
 583         if (pos >= azx_dev->bufsize)
 584                 pos = 0;
 585
 586         if (WARN_ONCE(!azx_dev->period_bytes,
 587                       "hda-intel: zero azx_dev->period_bytes"))
 588                 return -1; /* this shouldn't happen! */
 589         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
 590             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
 591                 /* NG - it's below the first next period boundary */
 592                 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
 593         azx_dev->start_wallclk += wallclk;
 594         return 1; /* OK, it's fine */
 595 }
 596
 597 /*
 598  * The work for pending PCM period updates.
 599  */
 600 static void azx_irq_pending_work(struct work_struct *work)
 601 {
 602         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 603         struct azx *chip = &hda->chip;
 604         int i, pending, ok;
 605
 606         if (!hda->irq_pending_warned) {
 607                 dev_info(chip->card->dev,
 608                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 609                          chip->card->number);
 610                 hda->irq_pending_warned = 1;
 611         }
 612
 613         for (;;) {
 614                 pending = 0;
 615                 spin_lock_irq(&chip->reg_lock);
 616                 for (i = 0; i < chip->num_streams; i++) {
 617                         struct azx_dev *azx_dev = &chip->azx_dev[i];
 618                         if (!azx_dev->irq_pending ||
 619                             !azx_dev->substream ||
 620                             !azx_dev->running)
 621                                 continue;
 622                         ok = azx_position_ok(chip, azx_dev);
 623                         if (ok > 0) {
 624                                 azx_dev->irq_pending = 0;
 625                                 spin_unlock(&chip->reg_lock);
 626                                 snd_pcm_period_elapsed(azx_dev->substream);
 627                                 spin_lock(&chip->reg_lock);
 628                         } else if (ok < 0) {
 629                                 pending = 0;    /* too early */
 630                         } else
 631                                 pending++;
 632                 }
 633                 spin_unlock_irq(&chip->reg_lock);
 634                 if (!pending)
 635                         return;
 636                 msleep(1);
 637         }
 638 }
 639
 640 /* clear irq_pending flags and assure no on-going workq */
 641 static void azx_clear_irq_pending(struct azx *chip)
 642 {
 643         int i;
 644
 645         spin_lock_irq(&chip->reg_lock);
 646         for (i = 0; i < chip->num_streams; i++)
 647                 chip->azx_dev[i].irq_pending = 0;
 648         spin_unlock_irq(&chip->reg_lock);
 649 }
 650
 651 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 652 {
 653         if (request_irq(chip->pci->irq, azx_interrupt,
 654                         chip->msi ? 0 : IRQF_SHARED,
 655                         KBUILD_MODNAME, chip)) {
 656                 dev_err(chip->card->dev,
 657                         "unable to grab IRQ %d, disabling device\n",
 658                         chip->pci->irq);
 659                 if (do_disconnect)
 660                         snd_card_disconnect(chip->card);
 661                 return -1;
 662         }
 663         chip->irq = chip->pci->irq;
 664         pci_intx(chip->pci, !chip->msi);
 665         return 0;
 666 }
 667
 668 /* get the current DMA position with correction on VIA chips */
 669 static unsigned int azx_via_get_position(struct azx *chip,
 670                                          struct azx_dev *azx_dev)
 671 {
 672         unsigned int link_pos, mini_pos, bound_pos;
 673         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 674         unsigned int fifo_size;
 675
 676         link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
 677         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 678                 /* Playback, no problem using link position */
 679                 return link_pos;
 680         }
 681
 682         /* Capture */
 683         /* For new chipset,
 684          * use mod to get the DMA position just like old chipset
 685          */
 686         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
 687         mod_dma_pos %= azx_dev->period_bytes;
 688
 689         /* azx_dev->fifo_size can't get FIFO size of in stream.
 690          * Get from base address + offset.
 691          */
 692         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 693
 694         if (azx_dev->insufficient) {
 695                 /* Link position never gather than FIFO size */
 696                 if (link_pos <= fifo_size)
 697                         return 0;
 698
 699                 azx_dev->insufficient = 0;
 700         }
 701
 702         if (link_pos <= fifo_size)
 703                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
 704         else
 705                 mini_pos = link_pos - fifo_size;
 706
 707         /* Find nearest previous boudary */
 708         mod_mini_pos = mini_pos % azx_dev->period_bytes;
 709         mod_link_pos = link_pos % azx_dev->period_bytes;
 710         if (mod_link_pos >= fifo_size)
 711                 bound_pos = link_pos - mod_link_pos;
 712         else if (mod_dma_pos >= mod_mini_pos)
 713                 bound_pos = mini_pos - mod_mini_pos;
 714         else {
 715                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
 716                 if (bound_pos >= azx_dev->bufsize)
 717                         bound_pos = 0;
 718         }
 719
 720         /* Calculate real DMA position we want */
 721         return bound_pos + mod_dma_pos;
 722 }
 723
 724 #ifdef CONFIG_PM
 725 static DEFINE_MUTEX(card_list_lock);
 726 static LIST_HEAD(card_list);
 727
 728 static void azx_add_card_list(struct azx *chip)
 729 {
 730         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 731         mutex_lock(&card_list_lock);
 732         list_add(&hda->list, &card_list);
 733         mutex_unlock(&card_list_lock);
 734 }
 735
 736 static void azx_del_card_list(struct azx *chip)
 737 {
 738         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 739         mutex_lock(&card_list_lock);
 740         list_del_init(&hda->list);
 741         mutex_unlock(&card_list_lock);
 742 }
 743
 744 /* trigger power-save check at writing parameter */
 745 static int param_set_xint(const char *val, const struct kernel_param *kp)
 746 {
 747         struct hda_intel *hda;
 748         struct azx *chip;
 749         int prev = power_save;
 750         int ret = param_set_int(val, kp);
 751
 752         if (ret || prev == power_save)
 753                 return ret;
 754
 755         mutex_lock(&card_list_lock);
 756         list_for_each_entry(hda, &card_list, list) {
 757                 chip = &hda->chip;
 758                 if (!chip->bus || chip->disabled)
 759                         continue;
 760                 snd_hda_set_power_save(chip->bus, power_save * 1000);
 761         }
 762         mutex_unlock(&card_list_lock);
 763         return 0;
 764 }
 765 #else
 766 #define azx_add_card_list(chip) /* NOP */
 767 #define azx_del_card_list(chip) /* NOP */
 768 #endif /* CONFIG_PM */
 769
 770 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
 771 /*
 772  * power management
 773  */
 774 static int azx_suspend(struct device *dev)
 775 {
 776         struct snd_card *card = dev_get_drvdata(dev);
 777         struct azx *chip;
 778         struct hda_intel *hda;
 779
 780         if (!card)
 781                 return 0;
 782
 783         chip = card->private_data;
 784         hda = container_of(chip, struct hda_intel, chip);
 785         if (chip->disabled || hda->init_failed)
 786                 return 0;
 787
 788         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 789         azx_clear_irq_pending(chip);
 790         azx_stop_chip(chip);
 791         azx_enter_link_reset(chip);
 792         if (chip->irq >= 0) {
 793                 free_irq(chip->irq, chip);
 794                 chip->irq = -1;
 795         }
 796
 797         if (chip->msi)
 798                 pci_disable_msi(chip->pci);
 799         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 800                 hda_display_power(hda, false);
 801         return 0;
 802 }
 803
 804 static int azx_resume(struct device *dev)
 805 {
 806         struct pci_dev *pci = to_pci_dev(dev);
 807         struct snd_card *card = dev_get_drvdata(dev);
 808         struct azx *chip;
 809         struct hda_intel *hda;
 810
 811         if (!card)
 812                 return 0;
 813
 814         chip = card->private_data;
 815         hda = container_of(chip, struct hda_intel, chip);
 816         if (chip->disabled || hda->init_failed)
 817                 return 0;
 818
 819         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
 820                 hda_display_power(hda, true);
 821                 haswell_set_bclk(hda);
 822         }
 823         if (chip->msi)
 824                 if (pci_enable_msi(pci) < 0)
 825                         chip->msi = 0;
 826         if (azx_acquire_irq(chip, 1) < 0)
 827                 return -EIO;
 828         azx_init_pci(chip);
 829
 830         azx_init_chip(chip, true);
 831
 832         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 833         return 0;
 834 }
 835 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
 836
 837 #ifdef CONFIG_PM
 838 static int azx_runtime_suspend(struct device *dev)
 839 {
 840         struct snd_card *card = dev_get_drvdata(dev);
 841         struct azx *chip;
 842         struct hda_intel *hda;
 843
 844         if (!card)
 845                 return 0;
 846
 847         chip = card->private_data;
 848         hda = container_of(chip, struct hda_intel, chip);
 849         if (chip->disabled || hda->init_failed)
 850                 return 0;
 851
 852         if (!azx_has_pm_runtime(chip))
 853                 return 0;
 854
 855         /* enable controller wake up event */
 856         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
 857                   STATESTS_INT_MASK);
 858
 859         azx_stop_chip(chip);
 860         azx_enter_link_reset(chip);
 861         azx_clear_irq_pending(chip);
 862         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 863                 hda_display_power(hda, false);
 864
 865         return 0;
 866 }
 867
 868 static int azx_runtime_resume(struct device *dev)
 869 {
 870         struct snd_card *card = dev_get_drvdata(dev);
 871         struct azx *chip;
 872         struct hda_intel *hda;
 873         struct hda_bus *bus;
 874         struct hda_codec *codec;
 875         int status;
 876
 877         if (!card)
 878                 return 0;
 879
 880         chip = card->private_data;
 881         hda = container_of(chip, struct hda_intel, chip);
 882         if (chip->disabled || hda->init_failed)
 883                 return 0;
 884
 885         if (!azx_has_pm_runtime(chip))
 886                 return 0;
 887
 888         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
 889                 hda_display_power(hda, true);
 890                 haswell_set_bclk(hda);
 891         }
 892
 893         /* Read STATESTS before controller reset */
 894         status = azx_readw(chip, STATESTS);
 895
 896         azx_init_pci(chip);
 897         azx_init_chip(chip, true);
 898
 899         bus = chip->bus;
 900         if (status && bus) {
 901                 list_for_each_codec(codec, bus)
 902                         if (status & (1 << codec->addr))
 903                                 schedule_delayed_work(&codec->jackpoll_work,
 904                                                       codec->jackpoll_interval);
 905         }
 906
 907         /* disable controller Wake Up event*/
 908         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
 909                         ~STATESTS_INT_MASK);
 910
 911         return 0;
 912 }
 913
 914 static int azx_runtime_idle(struct device *dev)
 915 {
 916         struct snd_card *card = dev_get_drvdata(dev);
 917         struct azx *chip;
 918         struct hda_intel *hda;
 919
 920         if (!card)
 921                 return 0;
 922
 923         chip = card->private_data;
 924         hda = container_of(chip, struct hda_intel, chip);
 925         if (chip->disabled || hda->init_failed)
 926                 return 0;
 927
 928         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
 929             chip->bus->core.codec_powered)
 930                 return -EBUSY;
 931
 932         return 0;
 933 }
 934
 935 static const struct dev_pm_ops azx_pm = {
 936         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
 937         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
 938 };
 939
 940 #define AZX_PM_OPS      &azx_pm
 941 #else
 942 #define AZX_PM_OPS      NULL
 943 #endif /* CONFIG_PM */
 944
 945
 946 static int azx_probe_continue(struct azx *chip);
 947
 948 #ifdef SUPPORT_VGA_SWITCHEROO
 949 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
 950
 951 static void azx_vs_set_state(struct pci_dev *pci,
 952                              enum vga_switcheroo_state state)
 953 {
 954         struct snd_card *card = pci_get_drvdata(pci);
 955         struct azx *chip = card->private_data;
 956         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 957         bool disabled;
 958
 959         wait_for_completion(&hda->probe_wait);
 960         if (hda->init_failed)
 961                 return;
 962
 963         disabled = (state == VGA_SWITCHEROO_OFF);
 964         if (chip->disabled == disabled)
 965                 return;
 966
 967         if (!chip->bus) {
 968                 chip->disabled = disabled;
 969                 if (!disabled) {
 970                         dev_info(chip->card->dev,
 971                                  "Start delayed initialization\n");
 972                         if (azx_probe_continue(chip) < 0) {
 973                                 dev_err(chip->card->dev, "initialization error\n");
 974                                 hda->init_failed = true;
 975                         }
 976                 }
 977         } else {
 978                 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
 979                          disabled ? "Disabling" : "Enabling");
 980                 if (disabled) {
 981                         pm_runtime_put_sync_suspend(card->dev);
 982                         azx_suspend(card->dev);
 983                         /* when we get suspended by vga switcheroo we end up in D3cold,
 984                          * however we have no ACPI handle, so pci/acpi can't put us there,
 985                          * put ourselves there */
 986                         pci->current_state = PCI_D3cold;
 987                         chip->disabled = true;
 988                         if (snd_hda_lock_devices(chip->bus))
 989                                 dev_warn(chip->card->dev,
 990                                          "Cannot lock devices!\n");
 991                 } else {
 992                         snd_hda_unlock_devices(chip->bus);
 993                         pm_runtime_get_noresume(card->dev);
 994                         chip->disabled = false;
 995                         azx_resume(card->dev);
 996                 }
 997         }
 998 }
 999
1000 static bool azx_vs_can_switch(struct pci_dev *pci)
1001 {
1002         struct snd_card *card = pci_get_drvdata(pci);
1003         struct azx *chip = card->private_data;
1004         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1005
1006         wait_for_completion(&hda->probe_wait);
1007         if (hda->init_failed)
1008                 return false;
1009         if (chip->disabled || !chip->bus)
1010                 return true;
1011         if (snd_hda_lock_devices(chip->bus))
1012                 return false;
1013         snd_hda_unlock_devices(chip->bus);
1014         return true;
1015 }
1016
1017 static void init_vga_switcheroo(struct azx *chip)
1018 {
1019         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1020         struct pci_dev *p = get_bound_vga(chip->pci);
1021         if (p) {
1022                 dev_info(chip->card->dev,
1023                          "Handle VGA-switcheroo audio client\n");
1024                 hda->use_vga_switcheroo = 1;
1025                 pci_dev_put(p);
1026         }
1027 }
1028
1029 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1030         .set_gpu_state = azx_vs_set_state,
1031         .can_switch = azx_vs_can_switch,
1032 };
1033
1034 static int register_vga_switcheroo(struct azx *chip)
1035 {
1036         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1037         int err;
1038
1039         if (!hda->use_vga_switcheroo)
1040                 return 0;
1041         /* FIXME: currently only handling DIS controller
1042          * is there any machine with two switchable HDMI audio controllers?
1043          */
1044         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1045                                                     VGA_SWITCHEROO_DIS,
1046                                                     chip->bus != NULL);
1047         if (err < 0)
1048                 return err;
1049         hda->vga_switcheroo_registered = 1;
1050
1051         /* register as an optimus hdmi audio power domain */
1052         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1053                                                          &hda->hdmi_pm_domain);
1054         return 0;
1055 }
1056 #else
1057 #define init_vga_switcheroo(chip)               /* NOP */
1058 #define register_vga_switcheroo(chip)           0
1059 #define check_hdmi_disabled(pci)        false
1060 #endif /* SUPPORT_VGA_SWITCHER */
1061
1062 /*
1063  * destructor
1064  */
1065 static int azx_free(struct azx *chip)
1066 {
1067         struct pci_dev *pci = chip->pci;
1068         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1069         int i;
1070
1071         if (azx_has_pm_runtime(chip) && chip->running)
1072                 pm_runtime_get_noresume(&pci->dev);
1073
1074         azx_del_card_list(chip);
1075
1076         hda->init_failed = 1; /* to be sure */
1077         complete_all(&hda->probe_wait);
1078
1079         if (use_vga_switcheroo(hda)) {
1080                 if (chip->disabled && chip->bus)
1081                         snd_hda_unlock_devices(chip->bus);
1082                 if (hda->vga_switcheroo_registered)
1083                         vga_switcheroo_unregister_client(chip->pci);
1084         }
1085
1086         if (chip->initialized) {
1087                 azx_clear_irq_pending(chip);
1088                 for (i = 0; i < chip->num_streams; i++)
1089                         azx_stream_stop(chip, &chip->azx_dev[i]);
1090                 azx_stop_chip(chip);
1091         }
1092
1093         if (chip->irq >= 0)
1094                 free_irq(chip->irq, (void*)chip);
1095         if (chip->msi)
1096                 pci_disable_msi(chip->pci);
1097         iounmap(chip->remap_addr);
1098
1099         azx_free_stream_pages(chip);
1100         if (chip->region_requested)
1101                 pci_release_regions(chip->pci);
1102         pci_disable_device(chip->pci);
1103         kfree(chip->azx_dev);
1104 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1105         release_firmware(chip->fw);
1106 #endif
1107         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1108                 hda_display_power(hda, false);
1109                 hda_i915_exit(hda);
1110         }
1111         kfree(hda);
1112
1113         return 0;
1114 }
1115
1116 static int azx_dev_free(struct snd_device *device)
1117 {
1118         return azx_free(device->device_data);
1119 }
1120
1121 #ifdef SUPPORT_VGA_SWITCHEROO
1122 /*
1123  * Check of disabled HDMI controller by vga-switcheroo
1124  */
1125 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1126 {
1127         struct pci_dev *p;
1128
1129         /* check only discrete GPU */
1130         switch (pci->vendor) {
1131         case PCI_VENDOR_ID_ATI:
1132         case PCI_VENDOR_ID_AMD:
1133         case PCI_VENDOR_ID_NVIDIA:
1134                 if (pci->devfn == 1) {
1135                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1136                                                         pci->bus->number, 0);
1137                         if (p) {
1138                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1139                                         return p;
1140                                 pci_dev_put(p);
1141                         }
1142                 }
1143                 break;
1144         }
1145         return NULL;
1146 }
1147
1148 static bool check_hdmi_disabled(struct pci_dev *pci)
1149 {
1150         bool vga_inactive = false;
1151         struct pci_dev *p = get_bound_vga(pci);
1152
1153         if (p) {
1154                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1155                         vga_inactive = true;
1156                 pci_dev_put(p);
1157         }
1158         return vga_inactive;
1159 }
1160 #endif /* SUPPORT_VGA_SWITCHEROO */
1161
1162 /*
1163  * white/black-listing for position_fix
1164  */
1165 static struct snd_pci_quirk position_fix_list[] = {
1166         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1167         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1168         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1169         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1170         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1171         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1172         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1173         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1174         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1175         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1176         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1177         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1178         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1179         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1180         {}
1181 };
1182
1183 static int check_position_fix(struct azx *chip, int fix)
1184 {
1185         const struct snd_pci_quirk *q;
1186
1187         switch (fix) {
1188         case POS_FIX_AUTO:
1189         case POS_FIX_LPIB:
1190         case POS_FIX_POSBUF:
1191         case POS_FIX_VIACOMBO:
1192         case POS_FIX_COMBO:
1193                 return fix;
1194         }
1195
1196         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1197         if (q) {
1198                 dev_info(chip->card->dev,
1199                          "position_fix set to %d for device %04x:%04x\n",
1200                          q->value, q->subvendor, q->subdevice);
1201                 return q->value;
1202         }
1203
1204         /* Check VIA/ATI HD Audio Controller exist */
1205         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1206                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1207                 return POS_FIX_VIACOMBO;
1208         }
1209         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1210                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1211                 return POS_FIX_LPIB;
1212         }
1213         return POS_FIX_AUTO;
1214 }
1215
1216 static void assign_position_fix(struct azx *chip, int fix)
1217 {
1218         static azx_get_pos_callback_t callbacks[] = {
1219                 [POS_FIX_AUTO] = NULL,
1220                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1221                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1222                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1223                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1224         };
1225
1226         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1227
1228         /* combo mode uses LPIB only for playback */
1229         if (fix == POS_FIX_COMBO)
1230                 chip->get_position[1] = NULL;
1231
1232         if (fix == POS_FIX_POSBUF &&
1233             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1234                 chip->get_delay[0] = chip->get_delay[1] =
1235                         azx_get_delay_from_lpib;
1236         }
1237
1238 }
1239
1240 /*
1241  * black-lists for probe_mask
1242  */
1243 static struct snd_pci_quirk probe_mask_list[] = {
1244         /* Thinkpad often breaks the controller communication when accessing
1245          * to the non-working (or non-existing) modem codec slot.
1246          */
1247         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1248         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1249         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1250         /* broken BIOS */
1251         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1252         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1253         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1254         /* forced codec slots */
1255         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1256         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1257         /* WinFast VP200 H (Teradici) user reported broken communication */
1258         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1259         {}
1260 };
1261
1262 #define AZX_FORCE_CODEC_MASK    0x100
1263
1264 static void check_probe_mask(struct azx *chip, int dev)
1265 {
1266         const struct snd_pci_quirk *q;
1267
1268         chip->codec_probe_mask = probe_mask[dev];
1269         if (chip->codec_probe_mask == -1) {
1270                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1271                 if (q) {
1272                         dev_info(chip->card->dev,
1273                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1274                                  q->value, q->subvendor, q->subdevice);
1275                         chip->codec_probe_mask = q->value;
1276                 }
1277         }
1278
1279         /* check forced option */
1280         if (chip->codec_probe_mask != -1 &&
1281             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1282                 chip->codec_mask = chip->codec_probe_mask & 0xff;
1283                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1284                          chip->codec_mask);
1285         }
1286 }
1287
1288 /*
1289  * white/black-list for enable_msi
1290  */
1291 static struct snd_pci_quirk msi_black_list[] = {
1292         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1293         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1294         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1295         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1296         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1297         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1298         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1299         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1300         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1301         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1302         {}
1303 };
1304
1305 static void check_msi(struct azx *chip)
1306 {
1307         const struct snd_pci_quirk *q;
1308
1309         if (enable_msi >= 0) {
1310                 chip->msi = !!enable_msi;
1311                 return;
1312         }
1313         chip->msi = 1;  /* enable MSI as default */
1314         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1315         if (q) {
1316                 dev_info(chip->card->dev,
1317                          "msi for device %04x:%04x set to %d\n",
1318                          q->subvendor, q->subdevice, q->value);
1319                 chip->msi = q->value;
1320                 return;
1321         }
1322
1323         /* NVidia chipsets seem to cause troubles with MSI */
1324         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1325                 dev_info(chip->card->dev, "Disabling MSI\n");
1326                 chip->msi = 0;
1327         }
1328 }
1329
1330 /* check the snoop mode availability */
1331 static void azx_check_snoop_available(struct azx *chip)
1332 {
1333         int snoop = hda_snoop;
1334
1335         if (snoop >= 0) {
1336                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1337                          snoop ? "snoop" : "non-snoop");
1338                 chip->snoop = snoop;
1339                 return;
1340         }
1341
1342         snoop = true;
1343         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1344             chip->driver_type == AZX_DRIVER_VIA) {
1345                 /* force to non-snoop mode for a new VIA controller
1346                  * when BIOS is set
1347                  */
1348                 u8 val;
1349                 pci_read_config_byte(chip->pci, 0x42, &val);
1350                 if (!(val & 0x80) && chip->pci->revision == 0x30)
1351                         snoop = false;
1352         }
1353
1354         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1355                 snoop = false;
1356
1357         chip->snoop = snoop;
1358         if (!snoop)
1359                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1360 }
1361
1362 static void azx_probe_work(struct work_struct *work)
1363 {
1364         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1365         azx_probe_continue(&hda->chip);
1366 }
1367
1368 /*
1369  * constructor
1370  */
1371 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1372                       int dev, unsigned int driver_caps,
1373                       const struct hda_controller_ops *hda_ops,
1374                       struct azx **rchip)
1375 {
1376         static struct snd_device_ops ops = {
1377                 .dev_free = azx_dev_free,
1378         };
1379         struct hda_intel *hda;
1380         struct azx *chip;
1381         int err;
1382
1383         *rchip = NULL;
1384
1385         err = pci_enable_device(pci);
1386         if (err < 0)
1387                 return err;
1388
1389         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1390         if (!hda) {
1391                 pci_disable_device(pci);
1392                 return -ENOMEM;
1393         }
1394
1395         chip = &hda->chip;
1396         spin_lock_init(&chip->reg_lock);
1397         mutex_init(&chip->open_mutex);
1398         chip->card = card;
1399         chip->pci = pci;
1400         chip->ops = hda_ops;
1401         chip->irq = -1;
1402         chip->driver_caps = driver_caps;
1403         chip->driver_type = driver_caps & 0xff;
1404         check_msi(chip);
1405         chip->dev_index = dev;
1406         chip->jackpoll_ms = jackpoll_ms;
1407         INIT_LIST_HEAD(&chip->pcm_list);
1408         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1409         INIT_LIST_HEAD(&hda->list);
1410         init_vga_switcheroo(chip);
1411         init_completion(&hda->probe_wait);
1412
1413         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1414
1415         check_probe_mask(chip, dev);
1416
1417         chip->single_cmd = single_cmd;
1418         azx_check_snoop_available(chip);
1419
1420         if (bdl_pos_adj[dev] < 0) {
1421                 switch (chip->driver_type) {
1422                 case AZX_DRIVER_ICH:
1423                 case AZX_DRIVER_PCH:
1424                         bdl_pos_adj[dev] = 1;
1425                         break;
1426                 default:
1427                         bdl_pos_adj[dev] = 32;
1428                         break;
1429                 }
1430         }
1431         chip->bdl_pos_adj = bdl_pos_adj;
1432
1433         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1434         if (err < 0) {
1435                 dev_err(card->dev, "Error creating device [card]!\n");
1436                 azx_free(chip);
1437                 return err;
1438         }
1439
1440         /* continue probing in work context as may trigger request module */
1441         INIT_WORK(&hda->probe_work, azx_probe_work);
1442
1443         *rchip = chip;
1444
1445         return 0;
1446 }
1447
1448 static int azx_first_init(struct azx *chip)
1449 {
1450         int dev = chip->dev_index;
1451         struct pci_dev *pci = chip->pci;
1452         struct snd_card *card = chip->card;
1453         int err;
1454         unsigned short gcap;
1455         unsigned int dma_bits = 64;
1456
1457 #if BITS_PER_LONG != 64
1458         /* Fix up base address on ULI M5461 */
1459         if (chip->driver_type == AZX_DRIVER_ULI) {
1460                 u16 tmp3;
1461                 pci_read_config_word(pci, 0x40, &tmp3);
1462                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1463                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1464         }
1465 #endif
1466
1467         err = pci_request_regions(pci, "ICH HD audio");
1468         if (err < 0)
1469                 return err;
1470         chip->region_requested = 1;
1471
1472         chip->addr = pci_resource_start(pci, 0);
1473         chip->remap_addr = pci_ioremap_bar(pci, 0);
1474         if (chip->remap_addr == NULL) {
1475                 dev_err(card->dev, "ioremap error\n");
1476                 return -ENXIO;
1477         }
1478
1479         if (chip->msi) {
1480                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1481                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1482                         pci->no_64bit_msi = true;
1483                 }
1484                 if (pci_enable_msi(pci) < 0)
1485                         chip->msi = 0;
1486         }
1487
1488         if (azx_acquire_irq(chip, 0) < 0)
1489                 return -EBUSY;
1490
1491         pci_set_master(pci);
1492         synchronize_irq(chip->irq);
1493
1494         gcap = azx_readw(chip, GCAP);
1495         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1496
1497         /* AMD devices support 40 or 48bit DMA, take the safe one */
1498         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1499                 dma_bits = 40;
1500
1501         /* disable SB600 64bit support for safety */
1502         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1503                 struct pci_dev *p_smbus;
1504                 dma_bits = 40;
1505                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1506                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1507                                          NULL);
1508                 if (p_smbus) {
1509                         if (p_smbus->revision < 0x30)
1510                                 gcap &= ~AZX_GCAP_64OK;
1511                         pci_dev_put(p_smbus);
1512                 }
1513         }
1514
1515         /* disable 64bit DMA address on some devices */
1516         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1517                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1518                 gcap &= ~AZX_GCAP_64OK;
1519         }
1520
1521         /* disable buffer size rounding to 128-byte multiples if supported */
1522         if (align_buffer_size >= 0)
1523                 chip->align_buffer_size = !!align_buffer_size;
1524         else {
1525                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1526                         chip->align_buffer_size = 0;
1527                 else
1528                         chip->align_buffer_size = 1;
1529         }
1530
1531         /* allow 64bit DMA address if supported by H/W */
1532         if (!(gcap & AZX_GCAP_64OK))
1533                 dma_bits = 32;
1534         if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) {
1535                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits));
1536         } else {
1537                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1538                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
1539         }
1540
1541         /* read number of streams from GCAP register instead of using
1542          * hardcoded value
1543          */
1544         chip->capture_streams = (gcap >> 8) & 0x0f;
1545         chip->playback_streams = (gcap >> 12) & 0x0f;
1546         if (!chip->playback_streams && !chip->capture_streams) {
1547                 /* gcap didn't give any info, switching to old method */
1548
1549                 switch (chip->driver_type) {
1550                 case AZX_DRIVER_ULI:
1551                         chip->playback_streams = ULI_NUM_PLAYBACK;
1552                         chip->capture_streams = ULI_NUM_CAPTURE;
1553                         break;
1554                 case AZX_DRIVER_ATIHDMI:
1555                 case AZX_DRIVER_ATIHDMI_NS:
1556                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1557                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1558                         break;
1559                 case AZX_DRIVER_GENERIC:
1560                 default:
1561                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1562                         chip->capture_streams = ICH6_NUM_CAPTURE;
1563                         break;
1564                 }
1565         }
1566         chip->capture_index_offset = 0;
1567         chip->playback_index_offset = chip->capture_streams;
1568         chip->num_streams = chip->playback_streams + chip->capture_streams;
1569         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1570                                 GFP_KERNEL);
1571         if (!chip->azx_dev)
1572                 return -ENOMEM;
1573
1574         err = azx_alloc_stream_pages(chip);
1575         if (err < 0)
1576                 return err;
1577
1578         /* initialize streams */
1579         azx_init_stream(chip);
1580
1581         /* initialize chip */
1582         azx_init_pci(chip);
1583
1584         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1585                 struct hda_intel *hda;
1586
1587                 hda = container_of(chip, struct hda_intel, chip);
1588                 haswell_set_bclk(hda);
1589         }
1590
1591         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1592
1593         /* codec detection */
1594         if (!chip->codec_mask) {
1595                 dev_err(card->dev, "no codecs found!\n");
1596                 return -ENODEV;
1597         }
1598
1599         strcpy(card->driver, "HDA-Intel");
1600         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1601                 sizeof(card->shortname));
1602         snprintf(card->longname, sizeof(card->longname),
1603                  "%s at 0x%lx irq %i",
1604                  card->shortname, chip->addr, chip->irq);
1605
1606         return 0;
1607 }
1608
1609 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1610 /* callback from request_firmware_nowait() */
1611 static void azx_firmware_cb(const struct firmware *fw, void *context)
1612 {
1613         struct snd_card *card = context;
1614         struct azx *chip = card->private_data;
1615         struct pci_dev *pci = chip->pci;
1616
1617         if (!fw) {
1618                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1619                 goto error;
1620         }
1621
1622         chip->fw = fw;
1623         if (!chip->disabled) {
1624                 /* continue probing */
1625                 if (azx_probe_continue(chip))
1626                         goto error;
1627         }
1628         return; /* OK */
1629
1630  error:
1631         snd_card_free(card);
1632         pci_set_drvdata(pci, NULL);
1633 }
1634 #endif
1635
1636 /*
1637  * HDA controller ops.
1638  */
1639
1640 /* PCI register access. */
1641 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1642 {
1643         writel(value, addr);
1644 }
1645
1646 static u32 pci_azx_readl(u32 __iomem *addr)
1647 {
1648         return readl(addr);
1649 }
1650
1651 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1652 {
1653         writew(value, addr);
1654 }
1655
1656 static u16 pci_azx_readw(u16 __iomem *addr)
1657 {
1658         return readw(addr);
1659 }
1660
1661 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1662 {
1663         writeb(value, addr);
1664 }
1665
1666 static u8 pci_azx_readb(u8 __iomem *addr)
1667 {
1668         return readb(addr);
1669 }
1670
1671 static int disable_msi_reset_irq(struct azx *chip)
1672 {
1673         int err;
1674
1675         free_irq(chip->irq, chip);
1676         chip->irq = -1;
1677         pci_disable_msi(chip->pci);
1678         chip->msi = 0;
1679         err = azx_acquire_irq(chip, 1);
1680         if (err < 0)
1681                 return err;
1682
1683         return 0;
1684 }
1685
1686 /* DMA page allocation helpers.  */
1687 static int dma_alloc_pages(struct azx *chip,
1688                            int type,
1689                            size_t size,
1690                            struct snd_dma_buffer *buf)
1691 {
1692         int err;
1693
1694         err = snd_dma_alloc_pages(type,
1695                                   chip->card->dev,
1696                                   size, buf);
1697         if (err < 0)
1698                 return err;
1699         mark_pages_wc(chip, buf, true);
1700         return 0;
1701 }
1702
1703 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1704 {
1705         mark_pages_wc(chip, buf, false);
1706         snd_dma_free_pages(buf);
1707 }
1708
1709 static int substream_alloc_pages(struct azx *chip,
1710                                  struct snd_pcm_substream *substream,
1711                                  size_t size)
1712 {
1713         struct azx_dev *azx_dev = get_azx_dev(substream);
1714         int ret;
1715
1716         mark_runtime_wc(chip, azx_dev, substream, false);
1717         azx_dev->bufsize = 0;
1718         azx_dev->period_bytes = 0;
1719         azx_dev->format_val = 0;
1720         ret = snd_pcm_lib_malloc_pages(substream, size);
1721         if (ret < 0)
1722                 return ret;
1723         mark_runtime_wc(chip, azx_dev, substream, true);
1724         return 0;
1725 }
1726
1727 static int substream_free_pages(struct azx *chip,
1728                                 struct snd_pcm_substream *substream)
1729 {
1730         struct azx_dev *azx_dev = get_azx_dev(substream);
1731         mark_runtime_wc(chip, azx_dev, substream, false);
1732         return snd_pcm_lib_free_pages(substream);
1733 }
1734
1735 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1736                              struct vm_area_struct *area)
1737 {
1738 #ifdef CONFIG_X86
1739         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1740         struct azx *chip = apcm->chip;
1741         if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1742                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1743 #endif
1744 }
1745
1746 static const struct hda_controller_ops pci_hda_ops = {
1747         .reg_writel = pci_azx_writel,
1748         .reg_readl = pci_azx_readl,
1749         .reg_writew = pci_azx_writew,
1750         .reg_readw = pci_azx_readw,
1751         .reg_writeb = pci_azx_writeb,
1752         .reg_readb = pci_azx_readb,
1753         .disable_msi_reset_irq = disable_msi_reset_irq,
1754         .dma_alloc_pages = dma_alloc_pages,
1755         .dma_free_pages = dma_free_pages,
1756         .substream_alloc_pages = substream_alloc_pages,
1757         .substream_free_pages = substream_free_pages,
1758         .pcm_mmap_prepare = pcm_mmap_prepare,
1759         .position_check = azx_position_check,
1760 };
1761
1762 static int azx_probe(struct pci_dev *pci,
1763                      const struct pci_device_id *pci_id)
1764 {
1765         static int dev;
1766         struct snd_card *card;
1767         struct hda_intel *hda;
1768         struct azx *chip;
1769         bool schedule_probe;
1770         int err;
1771
1772         if (dev >= SNDRV_CARDS)
1773                 return -ENODEV;
1774         if (!enable[dev]) {
1775                 dev++;
1776                 return -ENOENT;
1777         }
1778
1779         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1780                            0, &card);
1781         if (err < 0) {
1782                 dev_err(&pci->dev, "Error creating card!\n");
1783                 return err;
1784         }
1785
1786         err = azx_create(card, pci, dev, pci_id->driver_data,
1787                          &pci_hda_ops, &chip);
1788         if (err < 0)
1789                 goto out_free;
1790         card->private_data = chip;
1791         hda = container_of(chip, struct hda_intel, chip);
1792
1793         pci_set_drvdata(pci, card);
1794
1795         err = register_vga_switcheroo(chip);
1796         if (err < 0) {
1797                 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
1798                 goto out_free;
1799         }
1800
1801         if (check_hdmi_disabled(pci)) {
1802                 dev_info(card->dev, "VGA controller is disabled\n");
1803                 dev_info(card->dev, "Delaying initialization\n");
1804                 chip->disabled = true;
1805         }
1806
1807         schedule_probe = !chip->disabled;
1808
1809 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1810         if (patch[dev] && *patch[dev]) {
1811                 dev_info(card->dev, "Applying patch firmware '%s'\n",
1812                          patch[dev]);
1813                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1814                                               &pci->dev, GFP_KERNEL, card,
1815                                               azx_firmware_cb);
1816                 if (err < 0)
1817                         goto out_free;
1818                 schedule_probe = false; /* continued in azx_firmware_cb() */
1819         }
1820 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1821
1822 #ifndef CONFIG_SND_HDA_I915
1823         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1824                 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
1825 #endif
1826
1827         if (schedule_probe)
1828                 schedule_work(&hda->probe_work);
1829
1830         dev++;
1831         if (chip->disabled)
1832                 complete_all(&hda->probe_wait);
1833         return 0;
1834
1835 out_free:
1836         snd_card_free(card);
1837         return err;
1838 }
1839
1840 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1841 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1842         [AZX_DRIVER_NVIDIA] = 8,
1843         [AZX_DRIVER_TERA] = 1,
1844 };
1845
1846 static int azx_probe_continue(struct azx *chip)
1847 {
1848         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1849         struct pci_dev *pci = chip->pci;
1850         int dev = chip->dev_index;
1851         int err;
1852
1853         /* Request power well for Haswell HDA controller and codec */
1854         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1855 #ifdef CONFIG_SND_HDA_I915
1856                 err = hda_i915_init(hda);
1857                 if (err < 0)
1858                         goto out_free;
1859                 err = hda_display_power(hda, true);
1860                 if (err < 0) {
1861                         dev_err(chip->card->dev,
1862                                 "Cannot turn on display power on i915\n");
1863                         goto out_free;
1864                 }
1865 #endif
1866         }
1867
1868         err = azx_first_init(chip);
1869         if (err < 0)
1870                 goto out_free;
1871
1872 #ifdef CONFIG_SND_HDA_INPUT_BEEP
1873         chip->beep_mode = beep_mode[dev];
1874 #endif
1875
1876         /* create codec instances */
1877         err = azx_bus_create(chip, model[dev]);
1878         if (err < 0)
1879                 goto out_free;
1880
1881         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
1882         if (err < 0)
1883                 goto out_free;
1884
1885 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1886         if (chip->fw) {
1887                 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1888                                          chip->fw->data);
1889                 if (err < 0)
1890                         goto out_free;
1891 #ifndef CONFIG_PM
1892                 release_firmware(chip->fw); /* no longer needed */
1893                 chip->fw = NULL;
1894 #endif
1895         }
1896 #endif
1897         if ((probe_only[dev] & 1) == 0) {
1898                 err = azx_codec_configure(chip);
1899                 if (err < 0)
1900                         goto out_free;
1901         }
1902
1903         err = snd_card_register(chip->card);
1904         if (err < 0)
1905                 goto out_free;
1906
1907         chip->running = 1;
1908         azx_add_card_list(chip);
1909         snd_hda_set_power_save(chip->bus, power_save * 1000);
1910         if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
1911                 pm_runtime_put_noidle(&pci->dev);
1912
1913 out_free:
1914         if (err < 0)
1915                 hda->init_failed = 1;
1916         complete_all(&hda->probe_wait);
1917         return err;
1918 }
1919
1920 static void azx_remove(struct pci_dev *pci)
1921 {
1922         struct snd_card *card = pci_get_drvdata(pci);
1923
1924         if (card)
1925                 snd_card_free(card);
1926 }
1927
1928 static void azx_shutdown(struct pci_dev *pci)
1929 {
1930         struct snd_card *card = pci_get_drvdata(pci);
1931         struct azx *chip;
1932
1933         if (!card)
1934                 return;
1935         chip = card->private_data;
1936         if (chip && chip->running)
1937                 azx_stop_chip(chip);
1938 }
1939
1940 /* PCI IDs */
1941 static const struct pci_device_id azx_ids[] = {
1942         /* CPT */
1943         { PCI_DEVICE(0x8086, 0x1c20),
1944           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1945         /* PBG */
1946         { PCI_DEVICE(0x8086, 0x1d20),
1947           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1948         /* Panther Point */
1949         { PCI_DEVICE(0x8086, 0x1e20),
1950           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1951         /* Lynx Point */
1952         { PCI_DEVICE(0x8086, 0x8c20),
1953           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1954         /* 9 Series */
1955         { PCI_DEVICE(0x8086, 0x8ca0),
1956           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1957         /* Wellsburg */
1958         { PCI_DEVICE(0x8086, 0x8d20),
1959           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1960         { PCI_DEVICE(0x8086, 0x8d21),
1961           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1962         /* Lynx Point-LP */
1963         { PCI_DEVICE(0x8086, 0x9c20),
1964           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1965         /* Lynx Point-LP */
1966         { PCI_DEVICE(0x8086, 0x9c21),
1967           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1968         /* Wildcat Point-LP */
1969         { PCI_DEVICE(0x8086, 0x9ca0),
1970           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1971         /* Sunrise Point */
1972         { PCI_DEVICE(0x8086, 0xa170),
1973           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
1974         /* Sunrise Point-LP */
1975         { PCI_DEVICE(0x8086, 0x9d70),
1976           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
1977         /* Haswell */
1978         { PCI_DEVICE(0x8086, 0x0a0c),
1979           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
1980         { PCI_DEVICE(0x8086, 0x0c0c),
1981           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
1982         { PCI_DEVICE(0x8086, 0x0d0c),
1983           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
1984         /* Broadwell */
1985         { PCI_DEVICE(0x8086, 0x160c),
1986           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
1987         /* 5 Series/3400 */
1988         { PCI_DEVICE(0x8086, 0x3b56),
1989           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
1990         /* Poulsbo */
1991         { PCI_DEVICE(0x8086, 0x811b),
1992           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
1993         /* Oaktrail */
1994         { PCI_DEVICE(0x8086, 0x080a),
1995           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
1996         /* BayTrail */
1997         { PCI_DEVICE(0x8086, 0x0f04),
1998           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
1999         /* Braswell */
2000         { PCI_DEVICE(0x8086, 0x2284),
2001           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2002         /* ICH6 */
2003         { PCI_DEVICE(0x8086, 0x2668),
2004           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2005         /* ICH7 */
2006         { PCI_DEVICE(0x8086, 0x27d8),
2007           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2008         /* ESB2 */
2009         { PCI_DEVICE(0x8086, 0x269a),
2010           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2011         /* ICH8 */
2012         { PCI_DEVICE(0x8086, 0x284b),
2013           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2014         /* ICH9 */
2015         { PCI_DEVICE(0x8086, 0x293e),
2016           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2017         /* ICH9 */
2018         { PCI_DEVICE(0x8086, 0x293f),
2019           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2020         /* ICH10 */
2021         { PCI_DEVICE(0x8086, 0x3a3e),
2022           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2023         /* ICH10 */
2024         { PCI_DEVICE(0x8086, 0x3a6e),
2025           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2026         /* Generic Intel */
2027         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2028           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2029           .class_mask = 0xffffff,
2030           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2031         /* ATI SB 450/600/700/800/900 */
2032         { PCI_DEVICE(0x1002, 0x437b),
2033           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2034         { PCI_DEVICE(0x1002, 0x4383),
2035           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2036         /* AMD Hudson */
2037         { PCI_DEVICE(0x1022, 0x780d),
2038           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2039         /* ATI HDMI */
2040         { PCI_DEVICE(0x1002, 0x793b),
2041           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2042         { PCI_DEVICE(0x1002, 0x7919),
2043           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2044         { PCI_DEVICE(0x1002, 0x960f),
2045           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2046         { PCI_DEVICE(0x1002, 0x970f),
2047           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2048         { PCI_DEVICE(0x1002, 0xaa00),
2049           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2050         { PCI_DEVICE(0x1002, 0xaa08),
2051           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2052         { PCI_DEVICE(0x1002, 0xaa10),
2053           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2054         { PCI_DEVICE(0x1002, 0xaa18),
2055           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2056         { PCI_DEVICE(0x1002, 0xaa20),
2057           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2058         { PCI_DEVICE(0x1002, 0xaa28),
2059           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2060         { PCI_DEVICE(0x1002, 0xaa30),
2061           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2062         { PCI_DEVICE(0x1002, 0xaa38),
2063           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2064         { PCI_DEVICE(0x1002, 0xaa40),
2065           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2066         { PCI_DEVICE(0x1002, 0xaa48),
2067           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2068         { PCI_DEVICE(0x1002, 0xaa50),
2069           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2070         { PCI_DEVICE(0x1002, 0xaa58),
2071           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2072         { PCI_DEVICE(0x1002, 0xaa60),
2073           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2074         { PCI_DEVICE(0x1002, 0xaa68),
2075           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2076         { PCI_DEVICE(0x1002, 0xaa80),
2077           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2078         { PCI_DEVICE(0x1002, 0xaa88),
2079           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2080         { PCI_DEVICE(0x1002, 0xaa90),
2081           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2082         { PCI_DEVICE(0x1002, 0xaa98),
2083           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2084         { PCI_DEVICE(0x1002, 0x9902),
2085           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2086         { PCI_DEVICE(0x1002, 0xaaa0),
2087           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2088         { PCI_DEVICE(0x1002, 0xaaa8),
2089           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2090         { PCI_DEVICE(0x1002, 0xaab0),
2091           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2092         /* VIA VT8251/VT8237A */
2093         { PCI_DEVICE(0x1106, 0x3288),
2094           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2095         /* VIA GFX VT7122/VX900 */
2096         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2097         /* VIA GFX VT6122/VX11 */
2098         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2099         /* SIS966 */
2100         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2101         /* ULI M5461 */
2102         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2103         /* NVIDIA MCP */
2104         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2105           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2106           .class_mask = 0xffffff,
2107           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2108         /* Teradici */
2109         { PCI_DEVICE(0x6549, 0x1200),
2110           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2111         { PCI_DEVICE(0x6549, 0x2200),
2112           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2113         /* Creative X-Fi (CA0110-IBG) */
2114         /* CTHDA chips */
2115         { PCI_DEVICE(0x1102, 0x0010),
2116           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2117         { PCI_DEVICE(0x1102, 0x0012),
2118           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2119 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2120         /* the following entry conflicts with snd-ctxfi driver,
2121          * as ctxfi driver mutates from HD-audio to native mode with
2122          * a special command sequence.
2123          */
2124         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2125           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2126           .class_mask = 0xffffff,
2127           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2128           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2129 #else
2130         /* this entry seems still valid -- i.e. without emu20kx chip */
2131         { PCI_DEVICE(0x1102, 0x0009),
2132           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2133           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2134 #endif
2135         /* CM8888 */
2136         { PCI_DEVICE(0x13f6, 0x5011),
2137           .driver_data = AZX_DRIVER_CMEDIA |
2138           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2139         /* Vortex86MX */
2140         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2141         /* VMware HDAudio */
2142         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2143         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2144         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2145           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2146           .class_mask = 0xffffff,
2147           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2148         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2149           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2150           .class_mask = 0xffffff,
2151           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2152         { 0, }
2153 };
2154 MODULE_DEVICE_TABLE(pci, azx_ids);
2155
2156 /* pci_driver definition */
2157 static struct pci_driver azx_driver = {
2158         .name = KBUILD_MODNAME,
2159         .id_table = azx_ids,
2160         .probe = azx_probe,
2161         .remove = azx_remove,
2162         .shutdown = azx_shutdown,
2163         .driver = {
2164                 .pm = AZX_PM_OPS,
2165         },
2166 };
2167
2168 module_pci_driver(azx_driver);