]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
ARM: dts: armada-xp: Fixup pcie DT warnings
authorGregory CLEMENT <gregory.clement@free-electrons.com>
Sat, 5 Nov 2016 18:03:50 +0000 (19:03 +0100)
committerGregory CLEMENT <gregory.clement@free-electrons.com>
Sat, 19 Nov 2016 08:16:35 +0000 (09:16 +0100)
PCIe has a range property, so the unit name should contain an address.
Take the opportunity to use the node label instead of the full name.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
12 files changed:
arch/arm/boot/dts/armada-xp-axpwifiap.dts
arch/arm/boot/dts/armada-xp-db.dts
arch/arm/boot/dts/armada-xp-gp.dts
arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
arch/arm/boot/dts/armada-xp-linksys-mamba.dts
arch/arm/boot/dts/armada-xp-matrix.dts
arch/arm/boot/dts/armada-xp-mv78230.dtsi
arch/arm/boot/dts/armada-xp-mv78260.dtsi
arch/arm/boot/dts/armada-xp-mv78460.dtsi
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
arch/arm/boot/dts/armada-xp-synology-ds414.dts

index 7038c8625ac5b4149c759c1fc4a7a7197d615e4e..d12b06bf0d60abd6b21173049b10136d2a9c7c04 100644 (file)
                          MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
                          MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
 
-               pcie-controller {
-                       status = "okay";
-
-                       /* First mini-PCIe port */
-                       pcie@1,0 {
-                               /* Port 0, Lane 0 */
-                               status = "okay";
-                       };
-
-                       /* Second mini-PCIe port */
-                       pcie@2,0 {
-                               /* Port 0, Lane 1 */
-                               status = "okay";
-                       };
-
-                       /* Renesas uPD720202 USB 3.0 controller */
-                       pcie@3,0 {
-                               /* Port 0, Lane 3 */
-                               status = "okay";
-                       };
-               };
-
                internal-regs {
                        /* UART0 */
                        serial@12000 {
        };
 };
 
+&pciec {
+       status = "okay";
+
+       /* First mini-PCIe port */
+       pcie@1,0 {
+               /* Port 0, Lane 0 */
+               status = "okay";
+       };
+
+       /* Second mini-PCIe port */
+       pcie@2,0 {
+               /* Port 0, Lane 1 */
+               status = "okay";
+       };
+
+       /* Renesas uPD720202 USB 3.0 controller */
+       pcie@3,0 {
+               /* Port 0, Lane 3 */
+               status = "okay";
+       };
+};
+
 &pinctrl {
        pinctrl-0 = <&phy_int_pin>;
        pinctrl-names = "default";
index 665c81ff98dbc167b9c4d09bcb1e93717057128d..8b9c606bfbc6882024993253fe5afb8204d1615d 100644 (file)
                        };
                };
 
-               pcie-controller {
-                       status = "okay";
-
-                       /*
-                        * All 6 slots are physically present as
-                        * standard PCIe slots on the board.
-                        */
-                       pcie@1,0 {
-                               /* Port 0, Lane 0 */
-                               status = "okay";
-                       };
-                       pcie@2,0 {
-                               /* Port 0, Lane 1 */
-                               status = "okay";
-                       };
-                       pcie@3,0 {
-                               /* Port 0, Lane 2 */
-                               status = "okay";
-                       };
-                       pcie@4,0 {
-                               /* Port 0, Lane 3 */
-                               status = "okay";
-                       };
-                       pcie@9,0 {
-                               /* Port 2, Lane 0 */
-                               status = "okay";
-                       };
-                       pcie@10,0 {
-                               /* Port 3, Lane 0 */
-                               status = "okay";
-                       };
-               };
-
                internal-regs {
                        serial@12000 {
                                status = "okay";
        };
 };
 
+&pciec {
+       status = "okay";
+
+       /*
+        * All 6 slots are physically present as
+        * standard PCIe slots on the board.
+        */
+       pcie@1,0 {
+               /* Port 0, Lane 0 */
+               status = "okay";
+       };
+       pcie@2,0 {
+               /* Port 0, Lane 1 */
+               status = "okay";
+       };
+       pcie@3,0 {
+               /* Port 0, Lane 2 */
+               status = "okay";
+       };
+       pcie@4,0 {
+               /* Port 0, Lane 3 */
+               status = "okay";
+       };
+       pcie@9,0 {
+               /* Port 2, Lane 0 */
+               status = "okay";
+       };
+       pcie@10,0 {
+               /* Port 3, Lane 0 */
+               status = "okay";
+       };
+};
+
 &mdio {
        phy0: ethernet-phy@0 {
                reg = <0>;
index 09c9cabdf67a37ca03ff35d9e411caf58504141d..fca37e92b96a856089cb090223b268c8e9f17978 100644 (file)
                        };
                };
 
-               pcie-controller {
-                       status = "okay";
-
-                       /*
-                        * The 3 slots are physically present as
-                        * standard PCIe slots on the board.
-                        */
-                       pcie@1,0 {
-                               /* Port 0, Lane 0 */
-                               status = "okay";
-                       };
-                       pcie@9,0 {
-                               /* Port 2, Lane 0 */
-                               status = "okay";
-                       };
-                       pcie@10,0 {
-                               /* Port 3, Lane 0 */
-                               status = "okay";
-                       };
-               };
-
                internal-regs {
                        serial@12000 {
                                status = "okay";
        };
 };
 
+&pciec {
+       status = "okay";
+
+       /*
+        * The 3 slots are physically present as
+        * standard PCIe slots on the board.
+        */
+       pcie@1,0 {
+               /* Port 0, Lane 0 */
+               status = "okay";
+       };
+       pcie@9,0 {
+               /* Port 2, Lane 0 */
+               status = "okay";
+       };
+       pcie@10,0 {
+               /* Port 3, Lane 0 */
+               status = "okay";
+       };
+};
+
 &mdio {
        phy0: ethernet-phy@0 {
                reg = <16>;
index 0a6a43692620777afb6a59db603b1a9a13b2b666..1dce74d9b616268f125be7df41a5aec797b081b6 100644 (file)
                        MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
                        MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
 
-               pcie-controller {
-                       status = "okay";
-
-                       /* Quad port sata: Marvell 88SX7042 */
-                       pcie@1,0 {
-                               /* Port 0, Lane 0 */
-                               status = "okay";
-                       };
-
-                       /* USB 3.0 xHCI controller: NEC D720200F1 */
-                       pcie@5,0 {
-                               /* Port 1, Lane 0 */
-                               status = "okay";
-                       };
-               };
-
                internal-regs {
                        serial@12000 {
                                status = "okay";
                gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
        };
 };
+&pciec {
+       status = "okay";
+
+       /* Quad port sata: Marvell 88SX7042 */
+       pcie@1,0 {
+               /* Port 0, Lane 0 */
+               status = "okay";
+       };
+
+       /* USB 3.0 xHCI controller: NEC D720200F1 */
+       pcie@5,0 {
+               /* Port 1, Lane 0 */
+               status = "okay";
+       };
+};
 
 &mdio {
        phy0: ethernet-phy@0 { /* Marvell 88E1318 */
index 076f27f22c3bc151a539669a491ea2cf296a03f1..488a047481d4fd34142dcca0c8e80ecfde79d302 100644 (file)
                          MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
                          MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
 
-               pcie-controller {
-                       status = "okay";
-
-                       /* Etron EJ168 USB 3.0 controller */
-                       pcie@1,0 {
-                               /* Port 0, Lane 0 */
-                               status = "okay";
-                       };
-
-                       /* First mini-PCIe port */
-                       pcie@2,0 {
-                               /* Port 0, Lane 1 */
-                               status = "okay";
-                       };
-
-                       /* Second mini-PCIe port */
-                       pcie@3,0 {
-                               /* Port 0, Lane 3 */
-                               status = "okay";
-                       };
-               };
-
                internal-regs {
 
                        rtc@10300 {
        };
 };
 
+&pciec {
+       status = "okay";
+
+       /* Etron EJ168 USB 3.0 controller */
+       pcie@1,0 {
+               /* Port 0, Lane 0 */
+               status = "okay";
+       };
+
+       /* First mini-PCIe port */
+       pcie@2,0 {
+               /* Port 0, Lane 1 */
+               status = "okay";
+       };
+
+       /* Second mini-PCIe port */
+       pcie@3,0 {
+               /* Port 0, Lane 3 */
+               status = "okay";
+       };
+};
+
 &pinctrl {
 
        keys_pin: keys-pin {
index e1509f4c511425a031886c584c9705839b645e87..8b5a4e79d26b1a24cf7d30e5a437b1b9cd6896fe 100644 (file)
                          MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
                          MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
 
-               pcie-controller {
-                       status = "okay";
-
-                       pcie@1,0 {
-                               /* Port 0, Lane 0 */
-                               status = "okay";
-                       };
-               };
-
                internal-regs {
                        serial@12000 {
                                status = "okay";
                };
        };
 };
+
+&pciec {
+       status = "okay";
+
+       pcie@1,0 {
+               /* Port 0, Lane 0 */
+               status = "okay";
+       };
+};
index ebf79d6de1a11271610be53c3f4e8be657a8b0a5..05c164b5786d1983baf92490bc6f46cbdb93e629 100644 (file)
@@ -86,7 +86,7 @@
                 * configured as x4 or quad x1 lanes. One unit is
                 * x1 only.
                 */
-               pciec: pcie-controller {
+               pciec: pcie-controller@82000000 {
                        compatible = "marvell,armada-xp-pcie";
                        status = "disabled";
                        device_type = "pci";
index 34e78a568460457748f4e87110f0d3f05efcbed4..07894b0d3e59ceba584d1d4ef70c51228ecfbc11 100644 (file)
@@ -87,7 +87,7 @@
                 * configured as x4 or quad x1 lanes. One unit is
                 * x4 only.
                 */
-               pciec: pcie-controller {
+               pciec: pcie-controller@82000000 {
                        compatible = "marvell,armada-xp-pcie";
                        status = "disabled";
                        device_type = "pci";
index 5148827ed934f8d284d61dbb12b26d464403c036..775bee53ce8604598657d6abb65c37dd93311c6f 100644 (file)
                 * configured as x4 or quad x1 lanes. Two units are
                 * x4/x1.
                 */
-               pciec: pcie-controller {
+               pciec: pcie-controller@82000000 {
                        compatible = "marvell,armada-xp-pcie";
                        status = "disabled";
                        device_type = "pci";
index c4685cb86f0675e6b079d55df845e92c682d3ca5..5aaaf0fb2330c0433dd21f70cdda36264dddf40d 100644 (file)
                          MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
                          MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
 
-               pcie-controller {
-                       status = "okay";
-
-                       /* Connected to first Marvell 88SE9170 SATA controller */
-                       pcie@1,0 {
-                               /* Port 0, Lane 0 */
-                               status = "okay";
-                       };
-
-                       /* Connected to second Marvell 88SE9170 SATA controller */
-                       pcie@2,0 {
-                               /* Port 0, Lane 1 */
-                               status = "okay";
-                       };
-
-                       /* Connected to Fresco Logic FL1009 USB 3.0 controller */
-                       pcie@5,0 {
-                               /* Port 1, Lane 0 */
-                               status = "okay";
-                       };
-               };
-
                internal-regs {
 
                        /* RTC is provided by Intersil ISL12057 I2C RTC chip */
        };
 };
 
+&pciec {
+       status = "okay";
+
+       /* Connected to first Marvell 88SE9170 SATA controller */
+       pcie@1,0 {
+               /* Port 0, Lane 0 */
+               status = "okay";
+       };
+
+       /* Connected to second Marvell 88SE9170 SATA controller */
+       pcie@2,0 {
+               /* Port 0, Lane 1 */
+               status = "okay";
+       };
+
+       /* Connected to Fresco Logic FL1009 USB 3.0 controller */
+       pcie@5,0 {
+               /* Port 1, Lane 0 */
+               status = "okay";
+       };
+};
+
 &mdio {
        phy0: ethernet-phy@0 { /* Marvell 88E1318 */
                reg = <0>;
index 2e2cd935376171a1e2422ac37284e49351c8c5c0..a0e36e166b0221fad88a5e222d4758745a02daf2 100644 (file)
                        };
                };
 
-               pcie-controller {
-                       status = "okay";
-                       /* Internal mini-PCIe connector */
-                       pcie@1,0 {
-                               /* Port 0, Lane 0 */
-                               status = "okay";
-                       };
-               };
-
                internal-regs {
                        rtc@10300 {
                                /* No crystal connected to the internal RTC */
        };
 };
 
+&pciec {
+       status = "okay";
+       /* Internal mini-PCIe connector */
+       pcie@1,0 {
+               /* Port 0, Lane 0 */
+               status = "okay";
+       };
+};
+
 &mdio {
        phy0: ethernet-phy@0 {
                reg = <0>;
index 189ec7f4667cc16609a301f4ddf349bce4574204..d5630a7b4b1817c8305baf5b83dc06bd52fd0ed6 100644 (file)
                          MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
                          MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
 
-               pcie-controller {
-                       status = "okay";
-
-                       /*
-                        * Connected to Marvell 88SX7042 SATA-II controller
-                        * handling the four disks.
-                        */
-                       pcie@1,0 {
-                               /* Port 0, Lane 0 */
-                               status = "okay";
-                       };
-
-                       /*
-                        * Connected to EtronTech EJ168A XHCI controller
-                        * providing the two rear USB 3.0 ports.
-                        */
-                       pcie@5,0 {
-                               /* Port 1, Lane 0 */
-                               status = "okay";
-                       };
-               };
-
                internal-regs {
 
                        /* RTC is provided by Seiko S-35390A below */
        };
 };
 
+&pciec {
+       status = "okay";
+
+       /*
+        * Connected to Marvell 88SX7042 SATA-II controller
+        * handling the four disks.
+        */
+       pcie@1,0 {
+               /* Port 0, Lane 0 */
+               status = "okay";
+       };
+
+       /*
+        * Connected to EtronTech EJ168A XHCI controller
+        * providing the two rear USB 3.0 ports.
+        */
+       pcie@5,0 {
+               /* Port 1, Lane 0 */
+               status = "okay";
+       };
+};
+
+
 &mdio {
        phy0: ethernet-phy@0 { /* Marvell 88E1512 */
                reg = <0>;