ENGR00277382-1 [MX6SL] Ensure that PLL1 and PLL2 are always enabled.

Need to ensure that PLL1 and PLL2 have the enabled bit set even when
the PLL is powered down and disabled.

1. Modifications to the ARM_PODF bits in the CCM require PLL1 to be enabled.
2. PLL2 will be set to bypass and enabled state (can be powered down) in low
power IDLE mode.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 52317f1726389a4e8f003b600417d3b457854b4b..f90b62f12c07194cac218bc251a95a08a7d942eb 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -167,13 +167,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        };
 
        /*                   type                               name         parent_name  base     div_mask */
-       clk[pll1_sys]      = imx_clk_pllv3(IMX_PLLV3_SYS,       "pll1_sys",     "osc", base,        0x7f);
-       clk[pll2_bus]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,   "pll2_bus",     "osc", base + 0x30, 0x1);
-       clk[pll3_usb_otg]  = imx_clk_pllv3(IMX_PLLV3_USB,       "pll3_usb_otg", "osc", base + 0x10, 0x3);
-       clk[pll4_audio]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll4_audio",   "osc", base + 0x70, 0x7f);
-       clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x7f);
-       clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll6_enet",    "osc", base + 0xe0, 0x3);
-       clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x3);
+       clk[pll1_sys]      = imx_clk_pllv3(IMX_PLLV3_SYS,       "pll1_sys",     "osc", base,        0x7f, false);
+       clk[pll2_bus]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,   "pll2_bus",     "osc", base + 0x30, 0x1, false);
+       clk[pll3_usb_otg]  = imx_clk_pllv3(IMX_PLLV3_USB,       "pll3_usb_otg", "osc", base + 0x10, 0x3, false);
+       clk[pll4_audio]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll4_audio",   "osc", base + 0x70, 0x7f, false);
+       clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x7f, false);
+       clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll6_enet",    "osc", base + 0xe0, 0x3, false);
+       clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host",        "osc", base + 0x20, 0x3, false);
 
        /*
         * Bit 20 is the reserved and read-only bit, we do this only for:

diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 694c768e113f0bd05b7e2bed4c80b2aa16dc198c..22a8fefcd132ecc53a10512ff771d5440c9df28e 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -182,13 +182,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        anatop_base = base;
 
        /*                                             type               name            parent  base         div_mask */
-       clks[IMX6SL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1_sys",      "osc", base,        0x7f);
-       clks[IMX6SL_CLK_PLL2_BUS]      = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",      "osc", base + 0x30, 0x1);
-       clks[IMX6SL_CLK_PLL3_USB_OTG]  = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3_usb_otg",  "osc", base + 0x10, 0x3);
-       clks[IMX6SL_CLK_PLL4_AUDIO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4_audio",    "osc", base + 0x70, 0x7f);
-       clks[IMX6SL_CLK_PLL5_VIDEO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5_video",    "osc", base + 0xa0, 0x7f);
-       clks[IMX6SL_CLK_PLL6_ENET]     = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6_enet",     "osc", base + 0xe0, 0x3);
-       clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7_usb_host", "osc", base + 0x20, 0x3);
+       clks[IMX6SL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1_sys",      "osc", base,        0x7f, true);
+       clks[IMX6SL_CLK_PLL2_BUS]      = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",      "osc", base + 0x30, 0x1, true);
+       clks[IMX6SL_CLK_PLL3_USB_OTG]  = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3_usb_otg",  "osc", base + 0x10, 0x3, false);
+       clks[IMX6SL_CLK_PLL4_AUDIO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4_audio",    "osc", base + 0x70, 0x7f, false);
+       clks[IMX6SL_CLK_PLL5_VIDEO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5_video",    "osc", base + 0xa0, 0x7f, false);
+       clks[IMX6SL_CLK_PLL6_ENET]     = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6_enet",     "osc", base + 0xe0, 0x3, false);
+       clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7_usb_host", "osc", base + 0x20, 0x3, false);
 
        /*
         * usbphy1 and usbphy2 are implemented as dummy gates using reserve

diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index 61364050fccdce42b477f2a7a4aaafddf136f41a..633068bbc3c3c8bf4231d5e3dd8a7bd891a273ca 100644 (file)
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -32,6 +32,7 @@
  * @clk_hw:     clock source
  * @base:       base address of PLL registers
  * @powerup_set: set POWER bit to power up the PLL
+ * @always_on : Leave the PLL powered up all the time.
  * @div_mask:   mask of divider bits
  *
  * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
@@ -41,6 +42,7 @@ struct clk_pllv3 {
        struct clk_hw   hw;
        void __iomem    *base;
        bool            powerup_set;
+       bool            always_on;
        u32             div_mask;
 };
 
@@ -123,7 +125,8 @@ static void clk_pllv3_disable(struct clk_hw *hw)
        u32 val;
 
        val = readl_relaxed(pll->base);
-       val &= ~BM_PLL_ENABLE;
+       if (!pll->always_on)
+               val &= ~BM_PLL_ENABLE;
        writel_relaxed(val, pll->base);
 }
 
@@ -322,7 +325,7 @@ static const struct clk_ops clk_pllv3_enet_ops = {
 
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
                          const char *parent_name, void __iomem *base,
-                         u32 div_mask)
+                         u32 div_mask, bool always_on)
 {
        struct clk_pllv3 *pll;
        const struct clk_ops *ops;
@@ -352,6 +355,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
        }
        pll->base = base;
        pll->div_mask = div_mask;
+       pll->always_on = always_on;
 
        init.name = name;
        init.ops = ops;

diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index e29f6ebe9f39d0047abce6e010b9e577a1db14bc..c3b45c8387d17beefbba530942e076eb2c0f5ddb 100644 (file)
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -23,7 +23,8 @@ enum imx_pllv3_type {
 };
 
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
-               const char *parent_name, void __iomem *base, u32 div_mask);
+               const char *parent_name, void __iomem *base,
+               u32 div_mask, bool always_on);
 
 struct clk *clk_register_gate2(struct device *dev, const char *name,
                const char *parent_name, unsigned long flags,