ARM: dts: tx6: indentation cleanup

diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
index 8f817c06912f06f7e3c635cd356f5d8d47682bcb..352e2693fab4db664c5c76bb137b6a6423d9f507 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
@@ -323,9 +323,9 @@
                pinctrl_disp0_1: disp0grp-1 {
                        fsl,pins = <
                                MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
-                               MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
-                               MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
-                               MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
+                               MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
+                               MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
+                               MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
                                /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
                                MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
                                MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
@@ -356,9 +356,9 @@
                pinctrl_disp0_2: disp0grp-2 {
                        fsl,pins = <
                                MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
-                               MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
-                               MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
-                               MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
+                               MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
+                               MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
+                               MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
                                MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
                                MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
                                MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
@@ -400,8 +400,8 @@
                pinctrl_edt_ft5x06: edt-ft5x06grp {
                        fsl,pins = <
                                MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x1b0b0 /* Interrupt */
-                               MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x1b0b0 /* Reset */
-                               MX6QDL_PAD_EIM_A17__GPIO2_IO21          0x1b0b0 /* Wake */
+                               MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x1b0b0 /* Reset */
+                               MX6QDL_PAD_EIM_A17__GPIO2_IO21          0x1b0b0 /* Wake */
                        >;
                };
 
@@ -447,21 +447,21 @@
 
                pinctrl_gpmi_nand: gpminandgrp {
                        fsl,pins = <
-                               MX6QDL_PAD_NANDF_CLE__NAND_CLE          0x0b0b1
-                               MX6QDL_PAD_NANDF_ALE__NAND_ALE          0x0b0b1
-                               MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0x0b0b1
+                               MX6QDL_PAD_NANDF_CLE__NAND_CLE          0x0b0b1
+                               MX6QDL_PAD_NANDF_ALE__NAND_ALE          0x0b0b1
+                               MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0x0b0b1
                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0x0b000
-                               MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0x0b0b1
-                               MX6QDL_PAD_SD4_CMD__NAND_RE_B           0x0b0b1
-                               MX6QDL_PAD_SD4_CLK__NAND_WE_B           0x0b0b1
-                               MX6QDL_PAD_NANDF_D0__NAND_DATA00        0x0b0b1
-                               MX6QDL_PAD_NANDF_D1__NAND_DATA01        0x0b0b1
-                               MX6QDL_PAD_NANDF_D2__NAND_DATA02        0x0b0b1
-                               MX6QDL_PAD_NANDF_D3__NAND_DATA03        0x0b0b1
-                               MX6QDL_PAD_NANDF_D4__NAND_DATA04        0x0b0b1
-                               MX6QDL_PAD_NANDF_D5__NAND_DATA05        0x0b0b1
-                               MX6QDL_PAD_NANDF_D6__NAND_DATA06        0x0b0b1
-                               MX6QDL_PAD_NANDF_D7__NAND_DATA07        0x0b0b1
+                               MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0x0b0b1
+                               MX6QDL_PAD_SD4_CMD__NAND_RE_B           0x0b0b1
+                               MX6QDL_PAD_SD4_CLK__NAND_WE_B           0x0b0b1
+                               MX6QDL_PAD_NANDF_D0__NAND_DATA00        0x0b0b1
+                               MX6QDL_PAD_NANDF_D1__NAND_DATA01        0x0b0b1
+                               MX6QDL_PAD_NANDF_D2__NAND_DATA02        0x0b0b1
+                               MX6QDL_PAD_NANDF_D3__NAND_DATA03        0x0b0b1
+                               MX6QDL_PAD_NANDF_D4__NAND_DATA04        0x0b0b1
+                               MX6QDL_PAD_NANDF_D5__NAND_DATA05        0x0b0b1
+                               MX6QDL_PAD_NANDF_D6__NAND_DATA06        0x0b0b1
+                               MX6QDL_PAD_NANDF_D7__NAND_DATA07        0x0b0b1
                        >;
                };