powerpc/mm/radix: Synchronize updates to the process table

When writing to the process table, we need to ensure the store is
visible to a subsequent access by the MMU. We assume we never have
the PID active while doing the update, so a ptesync/isync pair
should hopefully be a big enough hammer for our purpose.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/mm/mmu_context_book3s64.c b/arch/powerpc/mm/mmu_context_book3s64.c
index ceff76262c7e8429f93719a3a3e7552c4e3e3c4e..abed1fe6992fa1bb365dfd30717bcfac3f402ee4 100644 (file)
--- a/arch/powerpc/mm/mmu_context_book3s64.c
+++ b/arch/powerpc/mm/mmu_context_book3s64.c
@@ -138,6 +138,14 @@ static int radix__init_new_context(struct mm_struct *mm)
        rts_field = radix__get_tree_size();
        process_tb[index].prtb0 = cpu_to_be64(rts_field | __pa(mm->pgd) | RADIX_PGD_INDEX_SIZE);
 
+       /*
+        * Order the above store with subsequent update of the PID
+        * register (at which point HW can start loading/caching
+        * the entry) and the corresponding load by the MMU from
+        * the L2 cache.
+        */
+       asm volatile("ptesync;isync" : : : "memory");
+
        mm->context.npu_context = NULL;
 
        return index;