]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
Merge remote-tracking branch 'pm/linux-next'
authorStephen Rothwell <sfr@canb.auug.org.au>
Sun, 1 Nov 2015 23:53:48 +0000 (10:53 +1100)
committerStephen Rothwell <sfr@canb.auug.org.au>
Sun, 1 Nov 2015 23:53:51 +0000 (10:53 +1100)
14 files changed:
1  2 
arch/arm/mach-mediatek/mediatek.c
arch/arm/mach-omap2/timer.c
arch/arm/mach-sunxi/sunxi.c
arch/arm64/include/asm/irq.h
drivers/acpi/nfit.c
drivers/acpi/osl.c
drivers/clocksource/Kconfig
drivers/clocksource/Makefile
drivers/cpufreq/Kconfig.arm
drivers/cpufreq/Makefile
drivers/pci/pci-driver.c
drivers/pci/pci.c
drivers/pci/pci.h
include/linux/acpi.h

index 19dc738c1abc5ab340d640c59a0ecccaa2f88aa5,a9549005097e035271ca34fae7a6a71caffdf956..d019a080a559a467acd503c94c0f70ec7c0050af
   */
  #include <linux/init.h>
  #include <asm/mach/arch.h>
-       clocksource_of_init();
 +#include <linux/of.h>
 +#include <linux/clk-provider.h>
 +#include <linux/clocksource.h>
 +
 +
 +#define GPT6_CON_MT65xx 0x10008060
 +#define GPT_ENABLE      0x31
 +
 +static void __init mediatek_timer_init(void)
 +{
 +      void __iomem *gpt_base;
 +
 +      if (of_machine_is_compatible("mediatek,mt6589") ||
 +          of_machine_is_compatible("mediatek,mt8135") ||
 +          of_machine_is_compatible("mediatek,mt8127")) {
 +              /* turn on GPT6 which ungates arch timer clocks */
 +              gpt_base = ioremap(GPT6_CON_MT65xx, 0x04);
 +
 +              /* enable clock and set to free-run */
 +              writel(GPT_ENABLE, gpt_base);
 +              iounmap(gpt_base);
 +      }
 +
 +      of_clk_init(NULL);
++      clocksource_probe();
 +};
  
  static const char * const mediatek_board_dt_compat[] = {
        "mediatek,mt6589",
index 05c17eb2f2d9374122bdecffcd163931f2ab251c,bef41837bf7fd7090eccf768c2881662ac42025a..b18ebbefae09577e20b19e53167aca5ef11b8d86
@@@ -469,64 -476,7 +469,64 @@@ static void __init omap2_gptimer_clocks
                        clocksource_gpt.name, clksrc.rate);
  }
  
 -#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 +static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
 +              const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
 +              const char *clksrc_prop, bool gptimer)
 +{
 +      omap_clk_init();
 +      omap_dmtimer_init();
 +      omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
 +
 +      /* Enable the use of clocksource="gp_timer" kernel parameter */
 +      if (use_gptimer_clksrc || gptimer)
 +              omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
 +                                              clksrc_prop);
 +      else
 +              omap2_sync32k_clocksource_init();
 +}
 +
 +void __init omap_init_time(void)
 +{
 +      __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
 +                      2, "timer_sys_ck", NULL, false);
 +
 +      if (of_have_populated_dt())
-               clocksource_of_init();
++              clocksource_probe();
 +}
 +
 +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
 +void __init omap3_secure_sync32k_timer_init(void)
 +{
 +      __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
 +                      2, "timer_sys_ck", NULL, false);
 +}
 +#endif /* CONFIG_ARCH_OMAP3 */
 +
 +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
 +void __init omap3_gptimer_timer_init(void)
 +{
 +      __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
 +                      1, "timer_sys_ck", "ti,timer-alwon", true);
 +}
 +#endif
 +
 +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) ||                \
 +      defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
 +static void __init omap4_sync32k_timer_init(void)
 +{
 +      __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
 +                      2, "sys_clkin_ck", NULL, false);
 +}
 +
 +void __init omap4_local_timer_init(void)
 +{
 +      omap4_sync32k_timer_init();
-       clocksource_of_init();
++      clocksource_probe();
 +}
 +#endif
 +
 +#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
 +
  /*
   * The realtime counter also called master counter, is a free-running
   * counter, which is related to real time. It produces the count used
Simple merge
index 09169296c3cc4c235d10a0b040c68938eb4a4c80,94c53674a31d24f45b6b392d90ac840c6bde7589..23eb450b820ba03ce83b737f308fcd3d6b33f9a8
@@@ -7,17 -5,7 +5,6 @@@
  
  struct pt_regs;
  
 -extern void migrate_irqs(void);
  extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
  
- static inline void acpi_irq_init(void)
- {
-       /*
-        * Hardcode ACPI IRQ chip initialization to GICv2 for now.
-        * Proper irqchip infrastructure will be implemented along with
-        * incoming  GICv2m|GICv3|ITS bits.
-        */
-       acpi_gic_init();
- }
- #define acpi_irq_init acpi_irq_init
  #endif
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge