]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
drivers/perf: arm_pmu: add ACPI framework
authorMark Rutland <mark.rutland@arm.com>
Tue, 11 Apr 2017 08:39:55 +0000 (09:39 +0100)
committerWill Deacon <will.deacon@arm.com>
Tue, 11 Apr 2017 15:29:54 +0000 (16:29 +0100)
This patch adds framework code to handle parsing PMU data out of the
MADT, sanity checking this, and managing the association of CPUs (and
their interrupts) with appropriate logical PMUs.

For the time being, we expect that only one PMU driver (PMUv3) will make
use of this, and we simply pass in a single probe function.

This is based on an earlier patch from Jeremy Linton.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
drivers/perf/Kconfig
drivers/perf/Makefile
drivers/perf/arm_pmu.c
drivers/perf/arm_pmu_acpi.c [new file with mode: 0644]
include/linux/cpuhotplug.h
include/linux/perf/arm_pmu.h

index c436e0d303e762eac99daa839bd47982ffb8832a..aa587edaf9eafae15d8e2824b9eb324548aa5f98 100644 (file)
@@ -12,6 +12,10 @@ config ARM_PMU
          Say y if you want to use CPU performance monitors on ARM-based
          systems.
 
+config ARM_PMU_ACPI
+       depends on ARM_PMU && ACPI
+       def_bool y
+
 config QCOM_L2_PMU
        bool "Qualcomm Technologies L2-cache PMU"
        depends on ARCH_QCOM && ARM64 && PERF_EVENTS && ACPI
index 925cd3903029e28dd93efb29d0d794733cd8ad39..6420bd4394d5e43f5e4ea9e5c327bc50b5582fd4 100644 (file)
@@ -1,4 +1,5 @@
 obj-$(CONFIG_ARM_PMU) += arm_pmu.o arm_pmu_platform.o
+obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o
 obj-$(CONFIG_QCOM_L2_PMU)      += qcom_l2_pmu.o
 obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o
 obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
index b3bedfa512ebc5fabbfd562a7fd25f87c8f39b98..dc459eb1246b16e9368dd0091d8b6bf50630eaba 100644 (file)
@@ -525,7 +525,7 @@ int perf_num_counters(void)
 }
 EXPORT_SYMBOL_GPL(perf_num_counters);
 
-static void armpmu_free_irq(struct arm_pmu *armpmu, int cpu)
+void armpmu_free_irq(struct arm_pmu *armpmu, int cpu)
 {
        struct pmu_hw_events __percpu *hw_events = armpmu->hw_events;
        int irq = per_cpu(hw_events->irq, cpu);
@@ -550,7 +550,7 @@ void armpmu_free_irqs(struct arm_pmu *armpmu)
                armpmu_free_irq(armpmu, cpu);
 }
 
-static int armpmu_request_irq(struct arm_pmu *armpmu, int cpu)
+int armpmu_request_irq(struct arm_pmu *armpmu, int cpu)
 {
        int err = 0;
        struct pmu_hw_events __percpu *hw_events = armpmu->hw_events;
diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c
new file mode 100644 (file)
index 0000000..34c862f
--- /dev/null
@@ -0,0 +1,256 @@
+/*
+ * ACPI probing code for ARM performance counters.
+ *
+ * Copyright (C) 2017 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/acpi.h>
+#include <linux/cpumask.h>
+#include <linux/init.h>
+#include <linux/percpu.h>
+#include <linux/perf/arm_pmu.h>
+
+#include <asm/cputype.h>
+
+static DEFINE_PER_CPU(struct arm_pmu *, probed_pmus);
+static DEFINE_PER_CPU(int, pmu_irqs);
+
+static int arm_pmu_acpi_register_irq(int cpu)
+{
+       struct acpi_madt_generic_interrupt *gicc;
+       int gsi, trigger;
+
+       gicc = acpi_cpu_get_madt_gicc(cpu);
+       if (WARN_ON(!gicc))
+               return -EINVAL;
+
+       gsi = gicc->performance_interrupt;
+       if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE)
+               trigger = ACPI_EDGE_SENSITIVE;
+       else
+               trigger = ACPI_LEVEL_SENSITIVE;
+
+       /*
+        * Helpfully, the MADT GICC doesn't have a polarity flag for the
+        * "performance interrupt". Luckily, on compliant GICs the polarity is
+        * a fixed value in HW (for both SPIs and PPIs) that we cannot change
+        * from SW.
+        *
+        * Here we pass in ACPI_ACTIVE_HIGH to keep the core code happy. This
+        * may not match the real polarity, but that should not matter.
+        *
+        * Other interrupt controllers are not supported with ACPI.
+        */
+       return acpi_register_gsi(NULL, gsi, trigger, ACPI_ACTIVE_HIGH);
+}
+
+static void arm_pmu_acpi_unregister_irq(int cpu)
+{
+       struct acpi_madt_generic_interrupt *gicc;
+       int gsi;
+
+       gicc = acpi_cpu_get_madt_gicc(cpu);
+       if (!gicc)
+               return;
+
+       gsi = gicc->performance_interrupt;
+       acpi_unregister_gsi(gsi);
+}
+
+static int arm_pmu_acpi_parse_irqs(void)
+{
+       int irq, cpu, irq_cpu, err;
+
+       for_each_possible_cpu(cpu) {
+               irq = arm_pmu_acpi_register_irq(cpu);
+               if (irq < 0) {
+                       err = irq;
+                       pr_warn("Unable to parse ACPI PMU IRQ for CPU%d: %d\n",
+                               cpu, err);
+                       goto out_err;
+               } else if (irq == 0) {
+                       pr_warn("No ACPI PMU IRQ for CPU%d\n", cpu);
+               }
+
+               per_cpu(pmu_irqs, cpu) = irq;
+       }
+
+       return 0;
+
+out_err:
+       for_each_possible_cpu(cpu) {
+               irq = per_cpu(pmu_irqs, cpu);
+               if (!irq)
+                       continue;
+
+               arm_pmu_acpi_unregister_irq(cpu);
+
+               /*
+                * Blat all copies of the IRQ so that we only unregister the
+                * corresponding GSI once (e.g. when we have PPIs).
+                */
+               for_each_possible_cpu(irq_cpu) {
+                       if (per_cpu(pmu_irqs, irq_cpu) == irq)
+                               per_cpu(pmu_irqs, irq_cpu) = 0;
+               }
+       }
+
+       return err;
+}
+
+static struct arm_pmu *arm_pmu_acpi_find_alloc_pmu(void)
+{
+       unsigned long cpuid = read_cpuid_id();
+       struct arm_pmu *pmu;
+       int cpu;
+
+       for_each_possible_cpu(cpu) {
+               pmu = per_cpu(probed_pmus, cpu);
+               if (!pmu || pmu->acpi_cpuid != cpuid)
+                       continue;
+
+               return pmu;
+       }
+
+       pmu = armpmu_alloc();
+       if (!pmu) {
+               pr_warn("Unable to allocate PMU for CPU%d\n",
+                       smp_processor_id());
+               return NULL;
+       }
+
+       pmu->acpi_cpuid = cpuid;
+
+       return pmu;
+}
+
+/*
+ * This must run before the common arm_pmu hotplug logic, so that we can
+ * associate a CPU and its interrupt before the common code tries to manage the
+ * affinity and so on.
+ *
+ * Note that hotplug events are serialized, so we cannot race with another CPU
+ * coming up. The perf core won't open events while a hotplug event is in
+ * progress.
+ */
+static int arm_pmu_acpi_cpu_starting(unsigned int cpu)
+{
+       struct arm_pmu *pmu;
+       struct pmu_hw_events __percpu *hw_events;
+       int irq;
+
+       /* If we've already probed this CPU, we have nothing to do */
+       if (per_cpu(probed_pmus, cpu))
+               return 0;
+
+       irq = per_cpu(pmu_irqs, cpu);
+
+       pmu = arm_pmu_acpi_find_alloc_pmu();
+       if (!pmu)
+               return -ENOMEM;
+
+       cpumask_set_cpu(cpu, &pmu->supported_cpus);
+
+       per_cpu(probed_pmus, cpu) = pmu;
+
+       /*
+        * Log and request the IRQ so the core arm_pmu code can manage it.  In
+        * some situations (e.g. mismatched PPIs), we may fail to request the
+        * IRQ. However, it may be too late for us to do anything about it.
+        * The common ARM PMU code will log a warning in this case.
+        */
+       hw_events = pmu->hw_events;
+       per_cpu(hw_events->irq, cpu) = irq;
+       armpmu_request_irq(pmu, cpu);
+
+       /*
+        * Ideally, we'd probe the PMU here when we find the first matching
+        * CPU. We can't do that for several reasons; see the comment in
+        * arm_pmu_acpi_init().
+        *
+        * So for the time being, we're done.
+        */
+       return 0;
+}
+
+int arm_pmu_acpi_probe(armpmu_init_fn init_fn)
+{
+       int pmu_idx = 0;
+       int cpu, ret;
+
+       if (acpi_disabled)
+               return 0;
+
+       /*
+        * Initialise and register the set of PMUs which we know about right
+        * now. Ideally we'd do this in arm_pmu_acpi_cpu_starting() so that we
+        * could handle late hotplug, but this may lead to deadlock since we
+        * might try to register a hotplug notifier instance from within a
+        * hotplug notifier.
+        *
+        * There's also the problem of having access to the right init_fn,
+        * without tying this too deeply into the "real" PMU driver.
+        *
+        * For the moment, as with the platform/DT case, we need at least one
+        * of a PMU's CPUs to be online at probe time.
+        */
+       for_each_possible_cpu(cpu) {
+               struct arm_pmu *pmu = per_cpu(probed_pmus, cpu);
+               char *base_name;
+
+               if (!pmu || pmu->name)
+                       continue;
+
+               ret = init_fn(pmu);
+               if (ret == -ENODEV) {
+                       /* PMU not handled by this driver, or not present */
+                       continue;
+               } else if (ret) {
+                       pr_warn("Unable to initialise PMU for CPU%d\n", cpu);
+                       return ret;
+               }
+
+               base_name = pmu->name;
+               pmu->name = kasprintf(GFP_KERNEL, "%s_%d", base_name, pmu_idx++);
+               if (!pmu->name) {
+                       pr_warn("Unable to allocate PMU name for CPU%d\n", cpu);
+                       return -ENOMEM;
+               }
+
+               ret = armpmu_register(pmu);
+               if (ret) {
+                       pr_warn("Failed to register PMU for CPU%d\n", cpu);
+                       return ret;
+               }
+       }
+
+       return 0;
+}
+
+static int arm_pmu_acpi_init(void)
+{
+       int ret;
+
+       if (acpi_disabled)
+               return 0;
+
+       /*
+        * We can't request IRQs yet, since we don't know the cookie value
+        * until we know which CPUs share the same logical PMU. We'll handle
+        * that in arm_pmu_acpi_cpu_starting().
+        */
+       ret = arm_pmu_acpi_parse_irqs();
+       if (ret)
+               return ret;
+
+       ret = cpuhp_setup_state(CPUHP_AP_PERF_ARM_ACPI_STARTING,
+                               "perf/arm/pmu_acpi:starting",
+                               arm_pmu_acpi_cpu_starting, NULL);
+
+       return ret;
+}
+subsys_initcall(arm_pmu_acpi_init)
index cfcfab37d9c4f9c1f686c31a9eda64a200fbe83b..0f2a80377520ec1d12299c78775d7162c63ac8c2 100644 (file)
@@ -94,6 +94,7 @@ enum cpuhp_state {
        CPUHP_AP_ARM_VFP_STARTING,
        CPUHP_AP_ARM64_DEBUG_MONITORS_STARTING,
        CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING,
+       CPUHP_AP_PERF_ARM_ACPI_STARTING,
        CPUHP_AP_PERF_ARM_STARTING,
        CPUHP_AP_ARM_L2X0_STARTING,
        CPUHP_AP_ARM_ARCH_TIMER_STARTING,
index 25556ebb1c7bf680cc04d924b9600599e49e6bd3..1360dd6d5e617a0fee746a0d530129e66530a0fb 100644 (file)
@@ -117,6 +117,9 @@ struct arm_pmu {
        struct notifier_block   cpu_pm_nb;
        /* the attr_groups array must be NULL-terminated */
        const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1];
+
+       /* Only to be used by ACPI probing code */
+       unsigned long acpi_cpuid;
 };
 
 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
@@ -159,12 +162,20 @@ int arm_pmu_device_probe(struct platform_device *pdev,
                         const struct of_device_id *of_table,
                         const struct pmu_probe_info *probe_table);
 
+#ifdef CONFIG_ACPI
+int arm_pmu_acpi_probe(armpmu_init_fn init_fn);
+#else
+static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
+#endif
+
 /* Internal functions only for core arm_pmu code */
 struct arm_pmu *armpmu_alloc(void);
 void armpmu_free(struct arm_pmu *pmu);
 int armpmu_register(struct arm_pmu *pmu);
 int armpmu_request_irqs(struct arm_pmu *armpmu);
 void armpmu_free_irqs(struct arm_pmu *armpmu);
+int armpmu_request_irq(struct arm_pmu *armpmu, int cpu);
+void armpmu_free_irq(struct arm_pmu *armpmu, int cpu);
 
 #define ARMV8_PMU_PDEV_NAME "armv8-pmu"