ARM: imx: fix vf610 enet module clock selection

The fec/enet driver calculates MDC rate with the formula below.

  ref_freq / ((MII_SPEED + 1) x 2)

The ref_freq here is the fec internal module clock, which is missing
from clk-vf610 clock driver right now.  And clk-vf610 driver mistakenly
supplies RMII clock (50 MHz) as the source to fec.  This results in the
situation that fec driver gets ref_freq as 50 MHz, while physically it
runs at 66 MHz (fec module clock physically sources from ipg which runs
at 66 MHz).  That's why software expects MDC runs at 2.5 MHz, while the
measurement tells it runs at 3.3 MHz.  And this causes the PHY KSZ8041
keeps swithing between Full and Half mode as below.

  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half
  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half
  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half

Add the missing module clock for ENET0 and ENET1, and correct the clock
supplying in device tree to fix above issue.

Thanks to Alison Wang <b18965@freescale.com> for debugging the issue.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index e1eb7dadda80a56255c63d1a646885f41115d6e0..67d929cf98045235a1a39eeeb7c884c2b2bccddc 100644 (file)
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -442,8 +442,8 @@
                                compatible = "fsl,mvf600-fec";
                                reg = <0x400d0000 0x1000>;
                                interrupts = <0 78 0x04>;
-                               clocks = <&clks VF610_CLK_ENET>,
-                                       <&clks VF610_CLK_ENET>,
+                               clocks = <&clks VF610_CLK_ENET0>,
+                                       <&clks VF610_CLK_ENET0>,
                                        <&clks VF610_CLK_ENET>;
                                clock-names = "ipg", "ahb", "ptp";
                                status = "disabled";
@@ -453,8 +453,8 @@
                                compatible = "fsl,mvf600-fec";
                                reg = <0x400d1000 0x1000>;
                                interrupts = <0 79 0x04>;
-                               clocks = <&clks VF610_CLK_ENET>,
-                                       <&clks VF610_CLK_ENET>,
+                               clocks = <&clks VF610_CLK_ENET1>,
+                                       <&clks VF610_CLK_ENET1>,
                                        <&clks VF610_CLK_ENET>;
                                clock-names = "ipg", "ahb", "ptp";
                                status = "disabled";

diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index d617c0b7c8095f23c3273c86aadd5421ad0d29d0..b169a396d93bfcf193c83d7329a6fdc290101425 100644 (file)
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -183,6 +183,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
        clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
        clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
        clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
+       clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));
+       clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));
 
        clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
 

diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 15e997fa78f24d9822defea3d2eb097b088580e7..4aa2b48cd15183e457a3eb96288dca81039cef37 100644 (file)
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -158,6 +158,8 @@
 #define VF610_CLK_GPU_SEL              145
 #define VF610_CLK_GPU_EN               146
 #define VF610_CLK_GPU2D                        147
-#define VF610_CLK_END                  148
+#define VF610_CLK_ENET0                        148
+#define VF610_CLK_ENET1                        149
+#define VF610_CLK_END                  150
 
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */