drm/i915: Extract i9xx_plane_ctl() and ironlake_plane_ctl()

Pull the code to calculate the pre-SKL primary plane control register
value into separate functions. Allows us to pre-compute it in the
future.

v2: Split the pre-ilk vs. ilk+ unification to a separate patch (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170323192712.30682-2-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9a28a8917dc10400523a3855aead84ab03e44e8b..aa2c85b2bf78c78fc14f32672e28ed84c66bbc6b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2962,28 +2962,23 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
        return 0;
 }
 
-static void i9xx_update_primary_plane(struct drm_plane *primary,
-                                     const struct intel_crtc_state *crtc_state,
-                                     const struct intel_plane_state *plane_state)
+static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
+                         const struct intel_plane_state *plane_state)
 {
-       struct drm_i915_private *dev_priv = to_i915(primary->dev);
-       struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
-       struct drm_framebuffer *fb = plane_state->base.fb;
-       int plane = intel_crtc->plane;
-       u32 linear_offset;
-       u32 dspcntr;
-       i915_reg_t reg = DSPCNTR(plane);
+       struct drm_i915_private *dev_priv =
+               to_i915(plane_state->base.plane->dev);
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+       const struct drm_framebuffer *fb = plane_state->base.fb;
        unsigned int rotation = plane_state->base.rotation;
-       int x = plane_state->base.src.x1 >> 16;
-       int y = plane_state->base.src.y1 >> 16;
-       unsigned long irqflags;
+       u32 dspcntr;
 
-       dspcntr = DISPPLANE_GAMMA_ENABLE;
+       dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
 
-       dspcntr |= DISPLAY_PLANE_ENABLE;
+       if (IS_G4X(dev_priv))
+               dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
        if (INTEL_GEN(dev_priv) < 4) {
-               if (intel_crtc->pipe == PIPE_B)
+               if (crtc->pipe == PIPE_B)
                        dspcntr |= DISPPLANE_SEL_PIPE_B;
        }
 
@@ -3010,7 +3005,8 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
                dspcntr |= DISPPLANE_RGBX101010;
                break;
        default:
-               BUG();
+               MISSING_CASE(fb->format->format);
+               return 0;
        }
 
        if (INTEL_GEN(dev_priv) >= 4 &&
@@ -3023,8 +3019,26 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
        if (rotation & DRM_REFLECT_X)
                dspcntr |= DISPPLANE_MIRROR;
 
-       if (IS_G4X(dev_priv))
-               dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
+       return dspcntr;
+}
+
+static void i9xx_update_primary_plane(struct drm_plane *primary,
+                                     const struct intel_crtc_state *crtc_state,
+                                     const struct intel_plane_state *plane_state)
+{
+       struct drm_i915_private *dev_priv = to_i915(primary->dev);
+       struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+       struct drm_framebuffer *fb = plane_state->base.fb;
+       int plane = intel_crtc->plane;
+       u32 linear_offset;
+       u32 dspcntr;
+       i915_reg_t reg = DSPCNTR(plane);
+       unsigned int rotation = plane_state->base.rotation;
+       int x = plane_state->base.src.x1 >> 16;
+       int y = plane_state->base.src.y1 >> 16;
+       unsigned long irqflags;
+
+       dspcntr = i9xx_plane_ctl(crtc_state, plane_state);
 
        intel_add_fb_offsets(&x, &y, plane_state, 0);
 
@@ -3105,25 +3119,19 @@ static void i9xx_disable_primary_plane(struct drm_plane *primary,
        spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
-static void ironlake_update_primary_plane(struct drm_plane *primary,
-                                         const struct intel_crtc_state *crtc_state,
-                                         const struct intel_plane_state *plane_state)
+static u32 ironlake_plane_ctl(const struct intel_crtc_state *crtc_state,
+                             const struct intel_plane_state *plane_state)
 {
-       struct drm_device *dev = primary->dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
-       struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
-       struct drm_framebuffer *fb = plane_state->base.fb;
-       int plane = intel_crtc->plane;
-       u32 linear_offset;
-       u32 dspcntr;
-       i915_reg_t reg = DSPCNTR(plane);
+       struct drm_i915_private *dev_priv =
+               to_i915(plane_state->base.plane->dev);
+       const struct drm_framebuffer *fb = plane_state->base.fb;
        unsigned int rotation = plane_state->base.rotation;
-       int x = plane_state->base.src.x1 >> 16;
-       int y = plane_state->base.src.y1 >> 16;
-       unsigned long irqflags;
+       u32 dspcntr;
 
-       dspcntr = DISPPLANE_GAMMA_ENABLE;
-       dspcntr |= DISPLAY_PLANE_ENABLE;
+       dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
+
+       if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
+               dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
        if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
                dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
@@ -3148,7 +3156,8 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
                dspcntr |= DISPPLANE_RGBX101010;
                break;
        default:
-               BUG();
+               MISSING_CASE(fb->format->format);
+               return 0;
        }
 
        if (fb->modifier == I915_FORMAT_MOD_X_TILED)
@@ -3157,8 +3166,27 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
        if (rotation & DRM_ROTATE_180)
                dspcntr |= DISPPLANE_ROTATE_180;
 
-       if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
-               dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
+       return dspcntr;
+}
+
+static void ironlake_update_primary_plane(struct drm_plane *primary,
+                                         const struct intel_crtc_state *crtc_state,
+                                         const struct intel_plane_state *plane_state)
+{
+       struct drm_device *dev = primary->dev;
+       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+       struct drm_framebuffer *fb = plane_state->base.fb;
+       int plane = intel_crtc->plane;
+       u32 linear_offset;
+       u32 dspcntr;
+       i915_reg_t reg = DSPCNTR(plane);
+       unsigned int rotation = plane_state->base.rotation;
+       int x = plane_state->base.src.x1 >> 16;
+       int y = plane_state->base.src.y1 >> 16;
+       unsigned long irqflags;
+
+       dspcntr = ironlake_plane_ctl(crtc_state, plane_state);
 
        intel_add_fb_offsets(&x, &y, plane_state, 0);