Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette...

Pull clk framework changes from Mike Turquette:
 "The first half of the clk framework pull request is made up almost
  entirely of new platform/driver support.  There are some conversions
  of existing drivers to the common-clock Device Tree binding, and a few
  non-critical fixes to the framework.

  Due to an entirely unnecessary cyclical dependency with the arm-soc
  tree this pull request is broken into two pieces.  The second piece
  will be sent out after arm-soc sends you the pull request that merged
  in core support for the HiSilicon 3620 platform.  That same pull
  request from arm-soc depends on this pull request to merge in those
  HiSilicon bits without causing build failures"

[ Just did the ARM SoC merges, so getting ready for the second clk tree
  pull request   - Linus ]

* tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits)
  devicetree: bindings: Document qcom,mmcc
  devicetree: bindings: Document qcom,gcc
  clk: qcom: Add support for MSM8660's global clock controller (GCC)
  clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)
  clk: qcom: Add support for MSM8974's global clock controller (GCC)
  clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)
  clk: qcom: Add support for MSM8960's global clock controller (GCC)
  clk: qcom: Add reset controller support
  clk: qcom: Add support for branches/gate clocks
  clk: qcom: Add support for root clock generators (RCGs)
  clk: qcom: Add support for phase locked loops (PLLs)
  clk: qcom: Add a regmap type clock struct
  clk: Add set_rate_and_parent() op
  reset: Silence warning in reset-controller.h
  clk: sirf: re-arch to make the codes support both prima2 and atlas6
  clk: composite: pass mux_hw into determine_rate
  clk: shmobile: Fix MSTP clock array initialization
  clk: shmobile: Fix MSTP clock index
  ARM: dts: Add clock provider specific properties to max77686 node
  clk: max77686: Register OF clock provider
  ...

diff --cc Documentation/devicetree/bindings/clock/exynos5250-clock.txt
Simple merge

diff --cc MAINTAINERS
Simple merge

diff --cc arch/arm/boot/dts/exynos4412-odroidx.dts
Simple merge

diff --cc arch/arm/boot/dts/exynos4412-trats2.dts
Simple merge

diff --cc arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 9a61494f45f514e1399a05b316f853489d9a9061,c33a01eda52aa518eb419ffa46955d8300509812..2c1560d52f1aea24bec737694ba680ea8caa63f8
--- 1/arch/arm/boot/dts/exynos5250-cros-common.dtsi
--- 2/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@@ -43,12 -35,8 +43,13 @@@
  
                max77686@09 {
                        compatible = "maxim,max77686";
 +                      interrupt-parent = <&gpx3>;
 +                      interrupts = <2 0>;
 +                      pinctrl-names = "default";
 +                      pinctrl-0 = <&max77686_irq>;
 +                      wakeup-source;
                        reg = <0x09>;
+                       #clock-cells = <1>;
  
                        voltage-regulators {
                                ldo1_reg: LDO1 {

diff --cc arch/arm/boot/dts/exynos5250.dtsi
Simple merge

diff --cc arch/arm/boot/dts/exynos5420.dtsi
Simple merge

diff --cc drivers/clk/Makefile
Simple merge

diff --cc drivers/clk/samsung/clk-exynos4.c
index 3852e44db0f83e75c6d87676118ba82e2071a777,2f7e440aebf88c56c630eec41e73ef227f832291..010f071af88321b288c0d9d0d5f17e5ed352fc01
--- 1/drivers/clk/samsung/clk-exynos4.c
--- 2/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@@ -498,64 -437,63 +437,64 @@@ static struct samsung_mux_clock exynos4
  
  /* list of divider clocks supported in all exynos4 soc's */
  static struct samsung_div_clock exynos4_div_clks[] __initdata = {
-       DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3),
-       DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3),
-       DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
-       DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
-       DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
-       DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
-       DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
-       DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
-       DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
-       DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
-       DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
-       DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
+       DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
+       DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
+       DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
+       DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
+       DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
+       DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
+       DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
+       DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
+       DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
+       DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
+       DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
+       DIV_F(0, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
                        CLK_SET_RATE_PARENT, 0),
-       DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
-       DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
-       DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
-       DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
-       DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
-       DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
-       DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
-       DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
-       DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
-       DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
-       DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
-       DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
-       DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
-       DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
-       DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
-       DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
-       DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
-       DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
-       DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
-       DIV_F(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
+       DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
+       DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
+       DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
+       DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
+       DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+       DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+       DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+       DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
+       DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
+       DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
+       DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
+       DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
+       DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
+       DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
+       DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
+       DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
+       DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
+       DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
+       DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
 -      DIV(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
++      DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
 +                      CLK_SET_RATE_PARENT, 0),
-       DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
-       DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
-       DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
-       DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
-       DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
-       DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
-       DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
-       DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
-       DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
-       DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
-       DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
-       DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
-       DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
-       DIV(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3),
-       DIV(sclk_apll, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
-       DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
+       DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
+       DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
+       DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
+       DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
+       DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
+       DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
+       DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
+       DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
+       DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
+       DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
+       DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
+       DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
+       DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
+       DIV(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3),
+       DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
+       DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
                        CLK_SET_RATE_PARENT, 0),
-       DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
+       DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
                        CLK_SET_RATE_PARENT, 0),
-       DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
+       DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
                        CLK_SET_RATE_PARENT, 0),
-       DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
+       DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
                        CLK_SET_RATE_PARENT, 0),
-       DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
+       DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
                        CLK_SET_RATE_PARENT, 0),
  };
  

diff --cc drivers/clk/tegra/clk-periph.c
Simple merge

diff --cc drivers/media/platform/omap3isp/isp.c
Simple merge