#define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
(_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1_50MHZ_40OHM \
+ (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
(_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
#define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \
(_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2_50MHZ_40OHM \
+ (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \
(_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
#define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \
(_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0_50MHZ_40OHM \
+ (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \
(_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
#define MX6Q_PAD_SD2_CLK__USDHC2_CLK \
(_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__USDHC2_CLK_50MHZ_40OHM \
+ (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \
(_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_SD2_CLK__KPP_COL_5 \
#define MX6Q_PAD_SD2_CMD__USDHC2_CMD \
(_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_CMD__USDHC2_CMD_50MHZ_40OHM \
+ (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \
(_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_SD2_CMD__KPP_ROW_5 \
#define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \
(_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3_50MHZ_40OHM \
+ (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \
(_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_SD2_DAT3__KPP_COL_6 \