num-lanes = <4>;
status = "disabled";
};
-
- pcie@290000 {
- compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x290000 0x1000
- 0x270000 0x1000
- 0x271000 0x40>;
- interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
- clocks = <&clock 28>, <&clock 27>;
- clock-names = "pcie", "pcie_bus";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
- 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0x0 0 &gic 53>;
- };
-
- pcie@2a0000 {
- compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x2a0000 0x1000
- 0x272000 0x1000
- 0x271040 0x40>;
- interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
- clocks = <&clock 29>, <&clock 27>;
- clock-names = "pcie", "pcie_bus";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
- 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0x0 0 &gic 56>;
- };
};
compatible = "fsl,imx23-lcdif";
reg = <0x80030000 2000>;
interrupts = <46 45>;
- clocks = <&clks 38>, <&clks 38>;
- clock-names = "pix", "axi";
+ clocks = <&clks 38>;
status = "disabled";
};
lcdif: lcdif@80030000 {
compatible = "fsl,imx28-lcdif";
reg = <0x80030000 0x2000>;
- interrupts = <38 86>;
- clocks = <&clks 55>, <&clks 55>;
- clock-names = "pix", "axi";
+ interrupts = <38>;
+ clocks = <&clks 55>;
dmas = <&dma_apbh 13>;
dma-names = "rx";
status = "disabled";
reg = <0xf8000000 0x20000>;
clocks = <&clks IMX5_CLK_OCRAM>;
};
-
- ocram: sram@f8000000 {
- compatible = "mmio-sram";
- reg = <0xf8000000 0x20000>;
- };
};
};
model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
};
-
-&ldb {
- ipu_id = <0>;
- sec_ipu_id = <0>;
-};
-
-&mxcfb1 {
- status = "okay";
-};
-
-&mxcfb2 {
- status = "okay";
-};
model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
};
-
-&ldb {
- ipu_id = <0>;
- sec_ipu_id = <0>;
-};
-
-&pxp {
- status = "okay";
-};
-
-&mxcfb1 {
- status = "okay";
-};
-
-&mxcfb2 {
- status = "okay";
-};
};
soc {
- gpu@00130000 {
- compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
- reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
- <0x0 0x0>;
- reg-names = "iobase_3d", "iobase_2d",
- "phys_baseaddr";
- interrupts = <0 9 0x04>, <0 10 0x04>;
- interrupt-names = "irq_3d", "irq_2d";
- clocks = <&clks 143>, <&clks 27>,
- <&clks 121>, <&clks 122>,
- <&clks 0>;
- clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
- "gpu2d_clk", "gpu3d_clk",
- "gpu3d_shader_clk";
- resets = <&src 0>, <&src 3>;
- reset-names = "gpu3d", "gpu2d";
- };
-
ocram: sram@00900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
};
aips1: aips-bus@02000000 {
- vpu@02040000 {
- iramsize = <0>;
- status = "okay";
- };
-
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
pxp: pxp@020f0000 {
- compatible = "fsl,imx6dl-pxp-dma";
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks 133>;
- clock-names = "pxp-axi";
- status = "disabled";
};
epdc: epdc@020f4000 {
compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
};
-&mxcfb1 {
- status = "okay";
-};
-
-&mxcfb2 {
- status = "okay";
-};
-
-&mxcfb3 {
- status = "okay";
-};
-
-&mxcfb4 {
- status = "okay";
-};
-
&sata {
status = "okay";
};
};
soc {
- gpu@00130000 {
- compatible = "fsl,imx6q-gpu";
- reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
- <0x02204000 0x4000>, <0x0 0x0>;
- reg-names = "iobase_3d", "iobase_2d",
- "iobase_vg", "phys_baseaddr";
- interrupts = <0 9 0x04>, <0 10 0x04>,<0 11 0x04>;
- interrupt-names = "irq_3d", "irq_2d", "irq_vg";
- clocks = <&clks 26>, <&clks 143>,
- <&clks 27>, <&clks 121>,
- <&clks 122>, <&clks 74>;
- clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
- "gpu3d_axi_clk", "gpu2d_clk",
- "gpu3d_clk", "gpu3d_shader_clk";
- resets = <&src 0>, <&src 3>, <&src 3>;
- reset-names = "gpu3d", "gpu2d", "gpuvg";
- };
-
ocram: sram@00900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x40000>;
};
};
- vpu@02040000 {
- status = "okay";
- };
-
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6q-iomuxc";
+
+ ipu2 {
+ pinctrl_ipu2_1: ipu2grp-1 {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
+ MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
+ MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
+ MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
+ MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
+ MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
+ MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
+ MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
+ MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
+ MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
+ MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
+ MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
+ MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
+ MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
+ MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
+ MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
+ MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
+ MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
+ MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
+ MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
+ MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
+ MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
+ MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
+ MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
+ MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
+ MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
+ MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
+ MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
+ MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
+ >;
+ };
+ };
};
};
};
};
};
-
-&iomuxc {
- ipu2 {
- pinctrl_ipu2_1: ipu2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
- MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
- MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
- MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
- MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
- MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
- MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
- MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
- MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
- MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
- MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
- MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
- MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
- MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
- MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
- MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
- MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
- MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
- MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
- MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
- MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
- MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
- MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
- MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
- MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
- MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
- MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
- MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
- MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
- >;
- };
- };
-};
#include <dt-bindings/gpio/gpio.h>
/ {
- aliases {
- mxcfb0 = &mxcfb1;
- mxcfb1 = &mxcfb2;
- mxcfb2 = &mxcfb3;
- mxcfb3 = &mxcfb4;
- };
-
memory {
reg = <0x10000000 0x80000000>;
};
default-brightness-level = <7>;
status = "okay";
};
-
- mxcfb1: fb@0 {
- compatible = "fsl,mxc_sdc_fb";
- disp_dev = "ldb";
- interface_pix_fmt = "RGB666";
- mode_str ="LDB-XGA";
- default_bpp = <16>;
- int_clk = <0>;
- late_init = <0>;
- status = "disabled";
- };
-
- mxcfb2: fb@1 {
- compatible = "fsl,mxc_sdc_fb";
- disp_dev = "ldb";
- interface_pix_fmt = "RGB666";
- mode_str ="LDB-XGA";
- default_bpp = <16>;
- int_clk = <0>;
- late_init = <0>;
- status = "disabled";
- };
-
- mxcfb3: fb@2 {
- compatible = "fsl,mxc_sdc_fb";
- disp_dev = "lcd";
- interface_pix_fmt = "RGB565";
- mode_str ="CLAA-WVGA";
- default_bpp = <16>;
- int_clk = <0>;
- late_init = <0>;
- status = "disabled";
- };
-
- mxcfb4: fb@3 {
- compatible = "fsl,mxc_sdc_fb";
- disp_dev = "ldb";
- interface_pix_fmt = "RGB666";
- mode_str ="LDB-XGA";
- default_bpp = <16>;
- int_clk = <0>;
- late_init = <0>;
- status = "disabled";
- };
-
- lcd@0 {
- compatible = "fsl,lcd";
- ipu_id = <0>;
- disp_id = <0>;
- default_ifmt = "RGB565";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu1_1>;
- status = "okay";
- };
-
- v4l2_cap_0 {
- compatible = "fsl,imx6q-v4l2-capture";
- ipu_id = <0>;
- csi_id = <0>;
- mclk_source = <0>;
- status = "okay";
- };
-
- v4l2_out {
- compatible = "fsl,mxc_v4l2_output";
- status = "okay";
- };
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1_1>;
+ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
status = "disabled"; /* pin conflict with WEIM NOR */
flash: m25p80@0 {
};
};
-&flexcan1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1_1>;
- pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */
- trx-en-gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>;
- trx-stby-gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
- status = "disabled"; /* pin conflict with fec */
-};
-
-&flexcan2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2_1>;
- trx-en-gpio = <&max7310_c 6 GPIO_ACTIVE_HIGH>;
- trx-stby-gpio = <&max7310_c 5 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
&ldb {
status = "okay";
status = "okay";
};
-&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand_1>;
- status = "okay";
-};
-
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
0x0000c000 0x1404a38e 0x00000000>;
};
};
-
-&ldb {
- ipu_id = <1>;
- disp_id = <1>;
- ext_ref = <1>;
- mode = "sep0";
- sec_ipu_id = <1>;
- sec_disp_id = <0>;
- status = "okay";
-};
-
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm3_1>;
- status = "okay";
-};
default-state = "on";
};
};
-
- sound {
- compatible = "fsl,imx6q-sabresd-wm8962",
- "fsl,imx-audio-wm8962";
- model = "wm8962-audio";
- ssi-controller = <&ssi2>;
- audio-codec = <&codec>;
- audio-routing =
- "Headphone Jack", "HPOUTL",
- "Headphone Jack", "HPOUTR",
- "Ext Spk", "SPKOUTL",
- "Ext Spk", "SPKOUTR",
- "MICBIAS", "AMIC",
- "IN3R", "MICBIAS",
- "DMIC", "MICBIAS",
- "DMICDAT", "DMIC";
- mux-int-port = <2>;
- mux-ext-port = <3>;
- };
-
- v4l2_cap_0 {
- compatible = "fsl,imx6q-v4l2-capture";
- ipu_id = <0>;
- csi_id = <0>;
- mclk_source = <0>;
- status = "okay";
- };
-
- v4l2_cap_1 {
- compatible = "fsl,imx6q-v4l2-capture";
- ipu_id = <0>;
- csi_id = <1>;
- mclk_source = <0>;
- status = "okay";
- };
-
- v4l2_out {
- compatible = "fsl,mxc_v4l2_output";
- status = "okay";
- };
-
- lvds_cabc_ctrl {
- lvds0-gpios = <&gpio6 15 0>;
- lvds1-gpios = <&gpio6 16 0>;
- };
};
&audmux {
};
};
};
-
- ov5640_mipi: ov5640_mipi@3c { /* i2c2 driver */
- compatible = "ovti,ov5640_mipi";
- reg = <0x3c>;
- clocks = <&clks 201>;
- clock-names = "csi_mclk";
- DOVDD-supply = <&vgen4_reg>; /* 1.8v */
- AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
- rev B board is VGEN5 */
- DVDD-supply = <&vgen2_reg>; /* 1.5v*/
- pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */
- rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */
- csi_id = <1>;
- mclk = <24000000>;
- mclk_source = <0>;
- };
-
- pmic: pfuze100@08 {
- compatible = "fsl,pfuze100";
- reg = <0x08>;
-
- regulators {
- sw1a_reg: sw1ab {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <6250>;
- };
-
- sw1c_reg: sw1c {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw2_reg: sw2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw3a_reg: sw3a {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw3b_reg: sw3b {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw4_reg: sw4 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- swbst_reg: swbst {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5150000>;
- };
-
- snvs_reg: vsnvs {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vref_reg: vrefddr {
- regulator-boot-on;
- regulator-always-on;
- };
-
- vgen1_reg: vgen1 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- };
-
- vgen2_reg: vgen2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- };
-
- vgen3_reg: vgen3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vgen4_reg: vgen4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vgen5_reg: vgen5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vgen6_reg: vgen6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
- };
-
- egalax_ts@04 {
- compatible = "eeti,egalax_ts";
- reg = <0x04>;
- interrupt-parent = <&gpio6>;
- interrupts = <8 2>;
- wakeup-gpios = <&gpio6 8 0>;
- };
-};
-
-&i2c3 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3_2>;
- status = "okay";
-
- egalax_ts@04 {
- compatible = "eeti,egalax_ts";
- reg = <0x04>;
- interrupt-parent = <&gpio6>;
- interrupts = <7 2>;
- wakeup-gpios = <&gpio6 7 0>;
- };
};
&i2c3 {
};
};
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_2>;
- status = "okay";
-
- codec: wm8962@1a {
- compatible = "wlf,wm8962";
- reg = <0x1a>;
- clocks = <&clks 169>;
- DCVDD-supply = <®_audio>;
- DBVDD-supply = <®_audio>;
- AVDD-supply = <®_audio>;
- CPVDD-supply = <®_audio>;
- MICVDD-supply = <®_audio>;
- PLLVDD-supply = <®_audio>;
- SPKVDD1-supply = <®_audio>;
- SPKVDD2-supply = <®_audio>;
- gpio-cfg = <
- 0x0000 /* 0:Default */
- 0x0000 /* 1:Default */
- 0x0013 /* 2:FN_DMICCLK */
- 0x0000 /* 3:Default */
- 0x8014 /* 4:FN_DMICCDAT */
- 0x0000 /* 5:Default */
- >;
- };
-};
-
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
- MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000
- MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
status = "okay";
};
-&pwm1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1_1>;
- status = "okay";
-};
-
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
bus-width = <8>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
- no-1-8-v;
status = "okay";
};
bus-width = <8>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
- no-1-8-v;
status = "okay";
};
};
asrc: asrc@02034000 {
- compatible = "fsl,imx6q-asrc";
reg = <0x02034000 0x4000>;
interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks 107>;
- clock-names = "core";
- dmas = <&sdma 17 20 0>, <&sdma 18 20 0>, <&sdma 19 20 0>,
- <&sdma 20 20 0>, <&sdma 21 20 0>, <&sdma 22 20 0>;
- dma-names = "rxa", "rxb", "rxc",
- "txa", "txb", "txc";
- fsl,clk-map-version = <2>;
- fsl,clk-channel-bits = <4>;
- status = "okay";
};
spba@0203c000 {
};
vpu: vpu@02040000 {
- compatible = "fsl,imx6-vpu";
reg = <0x02040000 0x3c000>;
- reg-names = "vpu_regs";
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
<0 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks 168>, <&clks 140>, <&clks 142>;
- clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
- iramsize = <0x21000>;
- iram = <&ocram>;
- resets = <&src 1>;
- pu-supply = <®_pu>;
- status = "disabled";
};
aipstz@0207c000 { /* AIPSTZ1 */
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
+ regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
};
};
};
-
-
-&iomuxc {
- audmux {
- pinctrl_audmux_1: audmux-1 {
- fsl,pins = <
- MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
- MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
- MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
- MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
- >;
- };
-
- pinctrl_audmux_2: audmux-2 {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
- >;
- };
-
- pinctrl_audmux_3: audmux-3 {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
- MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
- MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
- >;
- };
- };
-
- ecspi1 {
- pinctrl_ecspi1_1: ecspi1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
- >;
- };
-
- pinctrl_ecspi1_2: ecspi1grp-2 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
- >;
- };
- };
-
- ecspi3 {
- pinctrl_ecspi3_1: ecspi3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
- >;
- };
- };
-
- enet {
- pinctrl_enet_1: enetgrp-1 {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
- >;
- };
-
- pinctrl_enet_2: enetgrp-2 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
- >;
- };
-
- pinctrl_enet_3: enetgrp-3 {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- >;
- };
- };
-
- esai {
- pinctrl_esai_1: esaigrp-1 {
- fsl,pins = <
- MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
- MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
- MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
- MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
- MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
- MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
- MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
- MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
- MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
- >;
- };
-
- pinctrl_esai_2: esaigrp-2 {
- fsl,pins = <
- MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
- MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
- MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
- MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
- MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
- MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
- MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
- MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
- MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
- MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
- >;
- };
- };
-
- flexcan1 {
- pinctrl_flexcan1_1: flexcan1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
- >;
- };
-
- pinctrl_flexcan1_2: flexcan1grp-2 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
- >;
- };
- };
-
- flexcan2 {
- pinctrl_flexcan2_1: flexcan2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
- >;
- };
- };
-
- gpmi-nand {
- pinctrl_gpmi_nand_1: gpmi-nand-1 {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
- >;
- };
- };
-
- hdmi_hdcp {
- pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
- fsl,pins = <
- MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
- fsl,pins = <
- MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
- >;
- };
- };
-
- hdmi_cec {
- pinctrl_hdmi_cec_1: hdmicecgrp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
- >;
- };
-
- pinctrl_hdmi_cec_2: hdmicecgrp-2 {
- fsl,pins = <
- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
- >;
- };
- };
-
- i2c1 {
- pinctrl_i2c1_1: i2c1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c1_2: i2c1grp-2 {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
- >;
- };
- };
-
- i2c2 {
- pinctrl_i2c2_1: i2c2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c2_2: i2c2grp-2 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c2_3: i2c2grp-3 {
- fsl,pins = <
- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
- >;
- };
- };
-
- i2c3 {
- pinctrl_i2c3_1: i2c3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c3_2: i2c3grp-2 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c3_3: i2c3grp-3 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c3_4: i2c3grp-4 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
- >;
- };
- };
-
- ipu1 {
- pinctrl_ipu1_1: ipu1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
- MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
- >;
- };
-
- pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
- MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
- >;
- };
-
- pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
- MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
- MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
- MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
- MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
- MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
- MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
- MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
- >;
- };
- };
-
- mlb {
- pinctrl_mlb_1: mlbgrp-1 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
- MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
- MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
- >;
- };
-
- pinctrl_mlb_2: mlbgrp-2 {
- fsl,pins = <
- MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
- MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
- MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
- >;
- };
- };
-
- pwm1 {
- pinctrl_pwm1_1: pwm1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
- >;
- };
- };
-
- pwm3 {
- pinctrl_pwm3_1: pwm3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
- >;
- };
- };
-
- spdif {
- pinctrl_spdif_1: spdifgrp-1 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
- >;
- };
-
- pinctrl_spdif_2: spdifgrp-2 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
- MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
- >;
- };
- };
-
- uart1 {
- pinctrl_uart1_1: uart1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
- >;
- };
- };
-
- uart2 {
- pinctrl_uart2_1: uart2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
- fsl,pins = <
- MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
- MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
- >;
- };
- };
-
- uart3 {
- pinctrl_uart3_1: uart3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
- MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
- MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
- >;
- };
- };
-
- uart4 {
- pinctrl_uart4_1: uart4grp-1 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
- >;
- };
- };
-
- usbotg {
- pinctrl_usbotg_1: usbotggrp-1 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
- >;
- };
-
- pinctrl_usbotg_2: usbotggrp-2 {
- fsl,pins = <
- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
- >;
- };
- };
-
- usbh2 {
- pinctrl_usbh2_1: usbh2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
- MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
- >;
- };
-
- pinctrl_usbh2_2: usbh2grp-2 {
- fsl,pins = <
- MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
- >;
- };
- };
-
- usbh3 {
- pinctrl_usbh3_1: usbh3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
- MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
- >;
- };
-
- pinctrl_usbh3_2: usbh3grp-2 {
- fsl,pins = <
- MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
- >;
- };
- };
-
- usdhc2 {
- pinctrl_usdhc2_1: usdhc2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
- MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
- MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
- MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc2_2: usdhc2grp-2 {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- >;
- };
- };
-
- usdhc3 {
- pinctrl_usdhc3_1: usdhc3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc3_2: usdhc3grp-2 {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- >;
- };
- };
-
- usdhc4 {
- pinctrl_usdhc4_1: usdhc4grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc4_2: usdhc4grp-2 {
- fsl,pins = <
- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
- >;
- };
- };
-
- weim {
- pinctrl_weim_cs0_1: weim_cs0grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
- >;
- };
-
- pinctrl_weim_nor_1: weim_norgrp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
- MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
- MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
- /* data */
- MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
- MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
- MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
- MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
- MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
- MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
- MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
- MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
- MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
- MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
- MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
- MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
- MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
- MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
- MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
- MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
- /* address */
- MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
- MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
- MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
- MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
- MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
- MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
- MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
- MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
- MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
- MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
- MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
- MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
- MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
- MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
- MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
- MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
- MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
- MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
- MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
- MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
- MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
- MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
- MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
- MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
- >;
- };
- };
-};
mux-int-port = <2>;
mux-ext-port = <3>;
};
-
- pxp_v4l2_out {
- compatible = "fsl,imx6sl-pxp-v4l2";
- status = "okay";
- };
};
&audmux {
status = "okay";
};
-&lcdif {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcdif_dat_0
- &pinctrl_lcdif_ctrl_0>;
- lcd-supply = <®_lcd_3v3>;
- display = <&display>;
- status = "okay";
-
- display: display {
- bits-per-pixel = <16>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <33500000>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <89>;
- hfront-porch = <164>;
- vback-porch = <23>;
- vfront-porch = <10>;
- hsync-len = <10>;
- vsync-len = <10>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
- };
- };
-};
-
-&pwm1 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pinctrl_pwm1_0>;
- pinctrl-1 = <&pinctrl_pwm1_0_sleep>;
- status = "okay";
-};
-
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
cd-gpios = <&gpio3 22 0>;
status = "okay";
};
-
-&pxp {
- status = "okay";
-};
};
};
- tempmon: tempmon {
- compatible = "fsl,imx6sl-tempmon", "fsl,imx6q-tempmon";
- interrupts = <0 49 0x04>;
- fsl,tempmon = <&anatop>;
- fsl,tempmon-data = <&ocotp>;
- clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
- };
-
usbphy1: usbphy@020c9000 {
compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
<&clks IMX6SL_CLK_SDMA>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
- iram = <&ocram>;
/* imx6sl reuses imx6q sdma firmware */
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
};
pxp: pxp@020f0000 {
- compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks 111>;
- clock-names = "pxp-axi";
- status = "disabled";
};
epdc: epdc@020f4000 {
};
lcdif: lcdif@020f8000 {
- compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
reg = <0x020f8000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
- <&clks IMX6SL_CLK_LCDIF_AXI>;
- clock-names = "pix", "axi";
- status = "disabled";
};
dcp: dcp@020fc000 {
};
ocotp: ocotp@021bc000 {
- compatible = "fsl,imx6sl-ocotp", "syscon";
+ compatible = "fsl,imx6sl-ocotp";
reg = <0x021bc000 0x4000>;
};
reg = <0x021d8000 0x4000>;
status = "disabled";
};
-
- gpu@02200000 {
- compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu";
- reg = <0x02200000 0x4000>, <0x02204000 0x4000>,
- <0x80000000 0x0>;
- reg-names = "iobase_2d", "iobase_vg",
- "phys_baseaddr";
- interrupts = <0 10 0x04>, <0 11 0x04>;
- interrupt-names = "irq_2d", "irq_vg";
- clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
- <&clks IMX6SL_CLK_MMDC_ROOT>,
- <&clks IMX6SL_CLK_GPU2D_OVG>;
- clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
- "gpu2d_clk";
- resets = <&src 3>, <&src 3>;
- reset-names = "gpu2d", "gpuvg";
- };
-
- };
- };
-};
-
-&iomuxc {
- fec {
- pinctrl_fec_1: fecgrp-1 {
- fsl,pins = <
- MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
- MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
- MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
- MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
- MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
- MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
- MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
- MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
- MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
- >;
- };
- };
-
- i2c1 {
- pinctrl_i2c1_1: i2c1grp-1 {
- fsl,pins = <
- MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
- MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
- >;
- };
- };
-
- i2c2 {
- pinctrl_i2c2_1: i2c2grp-1 {
- fsl,pins = <
- MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
- MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
- >;
- };
- };
-
- i2c3 {
- pinctrl_i2c3_1: i2c3grp-1 {
- fsl,pins = <
- MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1
- MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1
- >;
- };
- };
-
- lcdif {
- pinctrl_lcdif_dat_0: lcdifdatgrp-0 {
- fsl,pins = <
- MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
- MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
- MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
- MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
- MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
- MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
- MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
- MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
- MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
- MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
- MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
- MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
- MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
- MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
- MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
- MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
- MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
- MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
- MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
- MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
- MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
- MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
- MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
- MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
- >;
- };
-
- pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 {
- fsl,pins = <
- MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
- MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
- MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
- MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
- MX6SL_PAD_LCD_RESET__LCD_RESET 0x1b0b0
- >;
- };
- };
-
- pwm1 {
- pinctrl_pwm1_0: pwm1grp-0 {
- fsl,pins = <
- MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
- >;
- };
-
- pinctrl_pwm1_0_sleep: pwm1grp-0-sleep {
- fsl,pins = <
- MX6SL_PAD_PWM1__GPIO3_IO23 0x3080
- >;
- };
- };
-
- uart1 {
- pinctrl_uart1_1: uart1grp-1 {
- fsl,pins = <
- MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
- MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
- >;
- };
- };
-
- usdhc1 {
- pinctrl_usdhc1_1: usdhc1grp-1 {
- fsl,pins = <
- MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
- >;
- };
- };
-
- usdhc2 {
- pinctrl_usdhc2_1: usdhc2grp-1 {
- fsl,pins = <
- MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- >;
- };
- };
-
- usdhc3 {
- pinctrl_usdhc3_1: usdhc3grp-1 {
- fsl,pins = <
- MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- >;
};
};
};
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/export.h>
-#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
-#include <linux/of_gpio.h>
#include <linux/of_platform.h>
#include <linux/pm_opp.h>
#include <linux/pci.h>
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
-static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
-{
- phy_write(dev, 0x0d, device);
- phy_write(dev, 0x0e, reg);
- phy_write(dev, 0x0d, (1 << 14) | device);
- phy_write(dev, 0x0e, val);
-}
-
-static int ksz9031rn_phy_fixup(struct phy_device *dev)
-{
- /*
- * min rx data delay, max rx/tx clock delay,
- * min rx/tx control delay
- */
- mmd_write_reg(dev, 2, 4, 0);
- mmd_write_reg(dev, 2, 5, 0);
- mmd_write_reg(dev, 2, 8, 0x003ff);
-
- return 0;
-}
-
static int ar8031_phy_fixup(struct phy_device *dev)
{
u16 val;
- /* disable phy AR8031 SmartEEE function. */
- phy_write(dev, 0xd, 0x3);
- phy_write(dev, 0xe, 0x805d);
- phy_write(dev, 0xd, 0x4003);
- val = phy_read(dev, 0xe);
- val &= ~(0x1 << 8);
- phy_write(dev, 0xe, val);
-
/* To enable AR8031 output a 125MHz clk from CLK_25M */
phy_write(dev, 0xd, 0x7);
phy_write(dev, 0xe, 0x8016);
}
}
-/*
- * Disable Hannstar LVDS panel CABC function.
- * This function turns the panel's backlight density automatically
- * according to the content shown on the panel which may cause
- * annoying unstable backlight issue.
- */
-static void __init imx6q_lvds_cabc_init(void)
-{
- struct device_node *np = NULL;
- int ret, lvds0_gpio, lvds1_gpio;
-
- np = of_find_node_by_name(NULL, "lvds_cabc_ctrl");
- if (!np)
- return;
-
- lvds0_gpio = of_get_named_gpio(np, "lvds0-gpios", 0);
- if (gpio_is_valid(lvds0_gpio)) {
- ret = gpio_request_one(lvds0_gpio, GPIOF_OUT_INIT_LOW,
- "LVDS0 CABC enable");
- if (ret)
- pr_warn("failed to request LVDS0 CABC gpio\n");
- }
-
- lvds1_gpio = of_get_named_gpio(np, "lvds1-gpios", 0);
- if (gpio_is_valid(lvds1_gpio)) {
- ret = gpio_request_one(lvds1_gpio, GPIOF_OUT_INIT_LOW,
- "LVDS1 CABC enable");
- if (ret)
- pr_warn("failed to request LVDS1 CABC gpio\n");
- }
-}
-
static void __init imx6q_init_machine(void)
{
struct device *parent;
cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();
imx6q_1588_init();
imx6q_axi_init();
- imx6q_lvds_cabc_init();
}
#define OCOTP_CFG3 0x440
{
debug_ll_io_init();
imx_scu_map_io();
- imx6_pm_map_io();
}
static void __init imx6q_init_irq(void)
};
DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
- /*
- * i.MX6Q/DL maps system memory at 0x10000000 (offset 256MiB), and
- * GPU has a limit on physical address that it accesses, which must
- * be below 2GiB.
- */
- .dma_zone_size = (SZ_2G - SZ_256M),
.smp = smp_ops(imx_smp_ops),
.map_io = imx6q_map_io,
.init_irq = imx6q_init_irq,
txstate->used = chan->cookie;
txstate->residue = 0;
}
- return DMA_SUCCESS;
+ return DMA_COMPLETE;
}
static int pxp_hw_init(struct pxps *pxp)
.unlocked_ioctl = drm_ioctl,
.mmap = drm_mmap,
.poll = drm_poll,
- .fasync = drm_fasync,
.llseek = noop_llseek,
};
static struct drm_driver driver = {
- .driver_features = DRIVER_USE_MTRR,
.fops = &viv_driver_fops,
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
static void __exit vivante_exit(void)
{
if (pplatformdev) {
- drm_platform_exit(&driver, pplatformdev);
+ drm_put_dev(platform_get_drvdata(pplatformdev));
platform_device_unregister(pplatformdev);
pplatformdev = NULL;
}
#define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
#define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
-/* dll control register */
-#define ESDHC_DLL_CTRL 0x60
-#define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
-#define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
-
/* tune control register */
#define ESDHC_TUNE_CTRL_STATUS 0x68
#define ESDHC_TUNE_CTRL_STEP 1
#define ESDHC_FLAG_STD_TUNING BIT(5)
/* The IP has SDHCI_CAPABILITIES_1 register */
#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
-/* The IP has errata ERR004536 */
-#define ESDHC_FLAG_ERR004536 BIT(7)
struct esdhc_soc_data {
u32 flags;
static struct esdhc_soc_data usdhc_imx6sl_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
- | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536,
+ | ESDHC_FLAG_HAVE_CAP1,
};
struct pltfm_imx_data {
return ret;
}
- if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
- if (esdhc_is_usdhc(imx_data)) {
- u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
- ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
- /* Swap AC23 bit */
- if (m & ESDHC_MIX_CTRL_AC23EN) {
- ret &= ~ESDHC_MIX_CTRL_AC23EN;
- ret |= SDHCI_TRNS_AUTO_CMD23;
- }
- } else {
- ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
- }
-
- return ret;
- }
-
return readw(host->ioaddr + reg);
}
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
}
-static unsigned int esdhc_get_max_timeout_counter(struct sdhci_host *host)
-{
- return 1 << 28;
-}
-
static struct sdhci_ops sdhci_esdhc_ops = {
.read_l = esdhc_readl_le,
.read_w = esdhc_readw_le,
struct esdhc_platform_data *boarddata)
{
struct device_node *np = pdev->dev.of_node;
- struct sdhci_host *host = platform_get_drvdata(pdev);
if (!np)
return -ENODEV;
if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
boarddata->delay_line = 0;
- if (of_find_property(np, "keep-power-in-suspend", NULL))
- host->mmc->pm_caps |= MMC_PM_KEEP_POWER;
-
- if (of_find_property(np, "enable-sdio-wakeup", NULL))
- host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
-
return 0;
}
#else
*/
if (esdhc_is_usdhc(imx_data)) {
writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
- host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
- SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER;
+ host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
host->mmc->caps |= MMC_CAP_1_8V_DDR;
-
- /*
- * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
- * TO1.1, it's harmless for MX6SL
- */
- writel(readl(host->ioaddr + 0x6c) | BIT(7), host->ioaddr + 0x6c);
- sdhci_esdhc_ops.get_max_timeout_counter =
- esdhc_get_max_timeout_counter;
}
if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
host->ioaddr + ESDHC_TUNING_CTRL);
- if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
- host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
-
boarddata = &imx_data->boarddata;
if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
if (!host->mmc->parent->platform_data) {
host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
}
- if (host->mmc->pm_caps & MMC_PM_KEEP_POWER &&
- host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)
- device_init_wakeup(&pdev->dev, 1);
-
err = sdhci_add_host(host);
if (err)
goto disable_clk;
else
{
/* Set the event to an unsignaled state. */
- INIT_COMPLETION(signal->obj);
+ reinit_completion(&signal->obj);
}
gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
* Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
* Copyright (c) 2004-2006 Macq Electronique SA.
*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
*/
#include <linux/module.h>
#include "fec.h"
static void set_multicast_list(struct net_device *ndev);
-static void fec_reset_phy(struct platform_device *pdev);
-static void fec_free_reset_gpio(struct platform_device *pdev);
#if defined(CONFIG_ARM)
#define FEC_ALIGNMENT 0xf
#define FEC_QUIRK_HAS_CSUM (1 << 5)
/* Controller has hardware vlan support */
#define FEC_QUIRK_HAS_VLAN (1 << 6)
-/* Controller is FEC-MAC */
-#define FEC_QUIRK_FEC_MAC (1 << 7)
/* ENET IP errata ERR006358
*
* If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
.driver_data = 0,
}, {
.name = "imx25-fec",
- .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_FEC_MAC,
+ .driver_data = FEC_QUIRK_USE_GASKET,
}, {
.name = "imx27-fec",
.driver_data = 0,
* enet-mac reset will reset mac address registers too,
* so need to reconfigure it.
*/
- if (id_entry->driver_data & FEC_QUIRK_ENET_MAC ||
- id_entry->driver_data & FEC_QUIRK_FEC_MAC) {
+ if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
* include that when passing upstream as it messes up
* bridging applications.
*/
- skb = __netdev_alloc_skb_ip_align(ndev, pkt_len - 4,
- GFP_ATOMIC | __GFP_NOWARN);
+ skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
if (unlikely(!skb)) {
ndev->stats.rx_dropped++;
} else {
int payload_offset = (2 * ETH_ALEN);
+ skb_reserve(skb, NET_IP_ALIGN);
skb_put(skb, pkt_len - 4); /* Make room */
/* Extract the frame data without the VLAN header. */
phy_start(fep->phy_dev);
netif_start_queue(ndev);
fep->opened = 1;
-
return 0;
}
fec_enet_clk_enable(ndev, false);
pinctrl_pm_select_sleep_state(&fep->pdev->dev);
fec_enet_free_buffers(ndev);
- fec_free_reset_gpio(fep->pdev);
return 0;
}
#ifdef CONFIG_OF
static void fec_reset_phy(struct platform_device *pdev)
{
- int err;
+ int err, phy_reset;
int msec = 1;
struct device_node *np = pdev->dev.of_node;
- struct net_device *ndev = platform_get_drvdata(pdev);
- struct fec_enet_private *fep = netdev_priv(ndev);
if (!np)
return;
if (msec > 1000)
msec = 1;
- fep->phy_reset_gpio = of_get_named_gpio(np, "phy-reset-gpios", 0);
- if (!gpio_is_valid(fep->phy_reset_gpio))
+ phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
+ if (!gpio_is_valid(phy_reset))
return;
- err = devm_gpio_request_one(&pdev->dev, fep->phy_reset_gpio,
- GPIOF_OUT_INIT_HIGH, "phy-reset");
+ err = devm_gpio_request_one(&pdev->dev, phy_reset,
+ GPIOF_OUT_INIT_LOW, "phy-reset");
if (err) {
dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
return;
}
msleep(msec);
- gpio_set_value(fep->phy_reset_gpio, 1);
-}
-
-static void fec_free_reset_gpio(struct platform_device *pdev)
-{
- struct net_device *ndev = platform_get_drvdata(pdev);
- struct fec_enet_private *fep = netdev_priv(ndev);
- struct device_node *np = pdev->dev.of_node;
- if (!np)
- return;
-
- fep->phy_reset_gpio = of_get_named_gpio(np, "phy-reset-gpios", 0);
- if (!gpio_is_valid(fep->phy_reset_gpio))
- return;
-
- devm_gpio_free(&pdev->dev, fep->phy_reset_gpio);
+ gpio_set_value(phy_reset, 1);
}
#else /* CONFIG_OF */
static void fec_reset_phy(struct platform_device *pdev)
* by machine code.
*/
}
-
-static void fec_free_reset_gpio(struct platform_device *pdev)
-{
- /*
- * make pair as api "fec_reset_phy()"
- */
-}
#endif /* CONFIG_OF */
static int
#define IMX_TEMP_PASSIVE 85000
#define IMX_TEMP_PASSIVE_COOL_DELTA 10000
+/*
+ * The maximum die temperature on imx parts is 105C, let's give some cushion
+ * for noise and possible temperature rise between measurements.
+ */
+#define IMX_TEMP_CRITICAL 100000
+
#define IMX_POLLING_DELAY 2000 /* millisecond */
#define IMX_PASSIVE_DELAY 1000
return ret;
}
- data->trip_temp[IMX_TRIP_PASSIVE] = IMX_TEMP_PASSIVE;
- data->trip_temp[IMX_TRIP_CRITICAL] = IMX_TEMP_CRITICAL;
+ data->temp_passive = IMX_TEMP_PASSIVE;
+ data->temp_critical = IMX_TEMP_CRITICAL;
data->tz = thermal_zone_device_register("imx_thermal_zone",
IMX_TRIP_NUM,
BIT(IMX_TRIP_PASSIVE), data,
writel(temp, sport->port.membase + UCR1);
spin_unlock_irqrestore(&sport->port.lock, flags);
- if (!uart_console(&sport->port)) {
- clk_disable_unprepare(sport->clk_per);
- clk_disable_unprepare(sport->clk_ipg);
- }
-}
-
-static void imx_flush_buffer(struct uart_port *port)
-{
- struct imx_port *sport = (struct imx_port *)port;
-
- if (sport->dma_is_enabled) {
- sport->tx_bytes = 0;
- dmaengine_terminate_all(sport->dma_chan_tx);
- }
+ clk_disable_unprepare(sport->clk_per);
+ clk_disable_unprepare(sport->clk_ipg);
}
static void imx_flush_buffer(struct uart_port *port)
#define PORTSC_HSP BIT(9)
#define PORTSC_PP BIT(12)
#define PORTSC_PTC (0x0FUL << 16)
+#define PORTSC_PHCD(d) ((d) ? BIT(22) : BIT(23))
/* PTS and PTW for non lpm version only */
#define PORTSC_PFSC BIT(24)
#define PORTSC_PTS(d) \
/*
- * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ * Copyright 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
* on behalf of DENX Software Engineering GmbH
*
#include "ci.h"
#include "ci_hdrc_imx.h"
-#define CI_HDRC_IMX_IMX28_WRITE_FIX BIT(0)
-#define CI_HDRC_IMX_SUPPORT_RUNTIME_PM BIT(1)
-#define CI_HDRC_IMX_MXS_PHY_EHCI_QUIRK BIT(2)
+#define CI_HDRC_IMX_IMX28_WRITE_FIX BIT(0)
struct ci_hdrc_imx_platform_flag {
unsigned int flags;
static const struct ci_hdrc_imx_platform_flag imx27_usb_data = {
};
-static const struct ci_hdrc_imx_platform_flag imx23_usb_data = {
- .flags = CI_HDRC_IMX_MXS_PHY_EHCI_QUIRK,
-};
-
static const struct ci_hdrc_imx_platform_flag imx28_usb_data = {
- .flags = CI_HDRC_IMX_IMX28_WRITE_FIX |
- CI_HDRC_IMX_MXS_PHY_EHCI_QUIRK,
-};
-
-static const struct ci_hdrc_imx_platform_flag imx6q_usb_data = {
- .flags = CI_HDRC_IMX_SUPPORT_RUNTIME_PM |
- CI_HDRC_IMX_MXS_PHY_EHCI_QUIRK,
-};
-
-static const struct ci_hdrc_imx_platform_flag imx6sl_usb_data = {
- .flags = CI_HDRC_IMX_SUPPORT_RUNTIME_PM,
+ .flags = CI_HDRC_IMX_IMX28_WRITE_FIX,
};
static const struct of_device_id ci_hdrc_imx_dt_ids[] = {
- { .compatible = "fsl,imx6sl-usb", .data = &imx6sl_usb_data},
- { .compatible = "fsl,imx6q-usb", .data = &imx6q_usb_data},
{ .compatible = "fsl,imx28-usb", .data = &imx28_usb_data},
- { .compatible = "fsl,imx23-usb", .data = &imx23_usb_data},
{ .compatible = "fsl,imx27-usb", .data = &imx27_usb_data},
{ /* sentinel */ }
};
if (ret)
goto err_clk;
- if (imx_platform_flag->flags & CI_HDRC_IMX_IMX28_WRITE_FIX)
- pdata.flags |= CI_HDRC_IMX28_WRITE_FIX;
-
- if (imx_platform_flag->flags & CI_HDRC_IMX_SUPPORT_RUNTIME_PM) {
- pdata.flags |= CI_HDRC_SUPPORTS_RUNTIME_PM;
- data->supports_runtime_pm = true;
- }
-
- if (imx_platform_flag->flags & CI_HDRC_IMX_MXS_PHY_EHCI_QUIRK)
- pdata.flags |= CI_HDRC_IMX_EHCI_QUIRK;
-
if (data->usbmisc_data) {
ret = imx_usbmisc_init(data->usbmisc_data);
if (ret) {
#define MSM_USB_BASE (ci->hw_bank.abs)
-static int ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
+static void ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
{
struct device *dev = ci->gadget.dev.parent;
int val;
dev_dbg(dev, "unknown ci_hdrc event\n");
break;
}
-
- return 0;
}
static struct ci_hdrc_platform_data ci_hdrc_msm_platdata = {
}
EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
-/**
- * ci_hdrc_query_available_role: get runtime available operation mode
- *
- * The glue layer can get current operation mode (host/peripheral/otg)
- * This function should be called after ci core device has created.
- *
- * @pdev: the platform device of ci core.
- *
- * Return USB_DR_MODE_XXX.
- */
-enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev)
-{
- struct ci_hdrc *ci = platform_get_drvdata(pdev);
-
- if (!ci)
- return USB_DR_MODE_UNKNOWN;
- if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])
- return USB_DR_MODE_OTG;
- else if (ci->roles[CI_ROLE_HOST])
- return USB_DR_MODE_HOST;
- else if (ci->roles[CI_ROLE_GADGET])
- return USB_DR_MODE_PERIPHERAL;
- else
- return USB_DR_MODE_UNKNOWN;
-}
-EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role);
-
static inline void ci_role_destroy(struct ci_hdrc *ci)
{
ci_hdrc_gadget_destroy(ci);
#include "host.h"
static struct hc_driver __read_mostly ci_ehci_hc_driver;
-static int (*orig_bus_suspend)(struct usb_hcd *hcd);
-
-static int ci_ehci_bus_suspend(struct usb_hcd *hcd)
-{
- struct ehci_hcd *ehci = hcd_to_ehci(hcd);
- int port;
- u32 tmp;
-
- int ret = orig_bus_suspend(hcd);
-
- if (ret)
- return ret;
-
- port = HCS_N_PORTS(ehci->hcs_params);
- while (port--) {
- u32 __iomem *reg = &ehci->regs->port_status[port];
- u32 portsc = ehci_readl(ehci, reg);
-
- if (portsc & PORT_CONNECT) {
- /*
- * For chipidea, the resume signal will be ended
- * automatically, so for remote wakeup case, the
- * usbcmd.rs may not be set before the resume has
- * ended if other resume path consumes too much
- * time (~23ms-24ms), in that case, the SOF will not
- * send out within 3ms after resume ends, then the
- * device will enter suspend again.
- */
- if (hcd->self.root_hub->do_remote_wakeup) {
- ehci_dbg(ehci,
- "Remote wakeup is enabled, "
- "and device is on the port\n");
-
- tmp = ehci_readl(ehci, &ehci->regs->command);
- tmp |= CMD_RUN;
- ehci_writel(ehci, tmp, &ehci->regs->command);
- /*
- * It needs a short delay between set RUNSTOP
- * and set PHCD.
- */
- udelay(125);
- }
- }
- }
-
- return 0;
-}
static irqreturn_t host_irq(struct ci_hdrc *ci)
{
ehci = hcd_to_ehci(hcd);
ehci->caps = ci->hw_bank.cap;
ehci->has_hostpc = ci->hw_bank.lpm;
+ ehci->has_tdi_phy_lpm = ci->hw_bank.lpm;
ehci->imx28_write_fix = ci->imx28_write_fix;
/*
ehci_init_driver(&ci_ehci_hc_driver, NULL);
- orig_bus_suspend = ci_ehci_hc_driver.bus_suspend;
-
- ci_ehci_hc_driver.bus_suspend = ci_ehci_bus_suspend;
-
return 0;
}
ci->b_sess_valid_event = false;
ci_handle_vbus_change(ci);
} else
- dev_dbg(ci->dev, "it should be quit event\n");
+ dev_err(ci->dev, "unexpected event occurs at %s\n", __func__);
enable_irq(ci->irq);
}
struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
unsigned long flags;
+ spin_lock_irqsave(&ci->lock, flags);
+ ci->gadget.speed = USB_SPEED_UNKNOWN;
+ ci->remote_wakeup = 0;
+ ci->suspended = 0;
+ spin_unlock_irqrestore(&ci->lock, flags);
+
/* flush all endpoints */
gadget_for_each_ep(ep, gadget) {
usb_ep_fifo_flush(ep);
ci->status = NULL;
}
- spin_lock_irqsave(&ci->lock, flags);
- ci->gadget.speed = USB_SPEED_UNKNOWN;
- ci->remote_wakeup = 0;
- ci->suspended = 0;
- spin_unlock_irqrestore(&ci->lock, flags);
-
return 0;
}
{
int retval;
- if (ci->gadget.speed != USB_SPEED_UNKNOWN) {
- if (ci->driver)
- ci->driver->disconnect(&ci->gadget);
- }
-
spin_unlock(&ci->lock);
if (ci->gadget.speed != USB_SPEED_UNKNOWN) {
if (ci->driver)
return -EBUSY;
spin_lock_irqsave(hwep->lock, flags);
- if (hwep->ci->gadget.speed == USB_SPEED_UNKNOWN) {
- spin_unlock_irqrestore(hwep->lock, flags);
- return 0;
- }
/* only internal SW should disable ctrl endpts */
return -EINVAL;
spin_lock_irqsave(hwep->lock, flags);
- if (hwep->ci->gadget.speed == USB_SPEED_UNKNOWN) {
- spin_unlock_irqrestore(hwep->lock, flags);
- return 0;
- }
retval = _ep_queue(ep, req, gfp_flags);
spin_unlock_irqrestore(hwep->lock, flags);
return retval;
return -EINVAL;
spin_lock_irqsave(hwep->lock, flags);
- if (hwep->ci->gadget.speed != USB_SPEED_UNKNOWN)
- hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
+
+ hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
dma_pool_free(hwep->td_pool, node->ptr, node->dma);
spin_lock_irqsave(hwep->lock, flags);
- if (hwep->ci->gadget.speed == USB_SPEED_UNKNOWN) {
- spin_unlock_irqrestore(hwep->lock, flags);
- return 0;
- }
#ifndef STALL_IN
/* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
if (value && hwep->type == USB_ENDPOINT_XFER_BULK && hwep->dir == TX &&
}
spin_lock_irqsave(hwep->lock, flags);
- if (hwep->ci->gadget.speed == USB_SPEED_UNKNOWN) {
- spin_unlock_irqrestore(hwep->lock, flags);
- return;
- }
hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
int ret = 0;
spin_lock_irqsave(&ci->lock, flags);
- if (ci->gadget.speed == USB_SPEED_UNKNOWN) {
- spin_unlock_irqrestore(&ci->lock, flags);
- return 0;
- }
if (!ci->remote_wakeup) {
ret = -EOPNOTSUPP;
goto out;
/*
- * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ * Copyright 2012 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
#include <linux/module.h>
#include <linux/of_platform.h>
+#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/delay.h>
struct imx_usbmisc {
void __iomem *base;
spinlock_t lock;
+ struct clk *clk;
const struct usbmisc_ops *ops;
};
{
struct resource *res;
struct imx_usbmisc *data;
+ int ret;
struct of_device_id *tmp_dev;
if (usbmisc)
if (IS_ERR(data->base))
return PTR_ERR(data->base);
+ data->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(data->clk)) {
+ dev_err(&pdev->dev,
+ "failed to get clock, err=%ld\n", PTR_ERR(data->clk));
+ return PTR_ERR(data->clk);
+ }
+
+ ret = clk_prepare_enable(data->clk);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "clk_prepare_enable failed, err=%d\n", ret);
+ return ret;
+ }
+
tmp_dev = (struct of_device_id *)
of_match_device(usbmisc_imx_dt_ids, &pdev->dev);
data->ops = (const struct usbmisc_ops *)tmp_dev->data;
static int usbmisc_imx_remove(struct platform_device *pdev)
{
+ clk_disable_unprepare(usbmisc->clk);
usbmisc = NULL;
return 0;
}
static int nop_set_suspend(struct usb_phy *x, int suspend)
{
- struct nop_usb_xceiv *nop = dev_get_drvdata(x->dev);
-
- if (IS_ERR(nop->clk))
- return 0;
-
- if (suspend)
- clk_disable_unprepare(nop->clk);
- else
- clk_prepare_enable(nop->clk);
-
return 0;
}
#define ANADIG_USB2_LOOPBACK_SET 0x244
#define ANADIG_USB2_LOOPBACK_CLR 0x248
-#define ANADIG_USB1_MISC 0x1f0
-#define ANADIG_USB2_MISC 0x250
-
#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12)
#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11)
#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2)
#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5)
-#define BM_ANADIG_USB1_MISC_RX_VPIN_FS BIT(29)
-#define BM_ANADIG_USB1_MISC_RX_VMIN_FS BIT(28)
-#define BM_ANADIG_USB2_MISC_RX_VPIN_FS BIT(29)
-#define BM_ANADIG_USB2_MISC_RX_VMIN_FS BIT(28)
-
#define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
/* Do disconnection between PHY and controller without vbus */
clk_disable_unprepare(mxs_phy->clk);
}
-static bool mxs_phy_is_low_speed_connection(struct mxs_phy *mxs_phy)
-{
- unsigned int line_state;
- /* bit definition is the same for all controllers */
- unsigned int dp_bit = BM_ANADIG_USB1_MISC_RX_VPIN_FS,
- dm_bit = BM_ANADIG_USB1_MISC_RX_VMIN_FS;
- unsigned int reg = ANADIG_USB1_MISC;
-
- /* If the SoCs don't have anatop, quit */
- if (!mxs_phy->regmap_anatop)
- return false;
-
- if (mxs_phy->port_id == 0)
- reg = ANADIG_USB1_MISC;
- else if (mxs_phy->port_id == 1)
- reg = ANADIG_USB2_MISC;
-
- regmap_read(mxs_phy->regmap_anatop, reg, &line_state);
-
- if ((line_state & (dp_bit | dm_bit)) == dm_bit)
- return true;
- else
- return false;
-}
-
static int mxs_phy_suspend(struct usb_phy *x, int suspend)
{
int ret;
struct mxs_phy *mxs_phy = to_mxs_phy(x);
- bool low_speed_connection, vbus_is_on;
-
- low_speed_connection = mxs_phy_is_low_speed_connection(mxs_phy);
- vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
if (suspend) {
- /*
- * FIXME: Do not power down RXPWD1PT1 bit for low speed
- * connect. The low speed connection will have problem at
- * very rare cases during usb suspend and resume process.
- */
- if (low_speed_connection & vbus_is_on) {
- /*
- * If value to be set as pwd value is not 0xffffffff,
- * several 32Khz cycles are needed.
- */
- mxs_phy_clock_switch();
- writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD);
- } else {
- writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
- }
+ writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
writel(BM_USBPHY_CTRL_CLKGATE,
x->io_priv + HW_USBPHY_CTRL_SET);
clk_disable_unprepare(mxs_phy->clk);
/*
- * Copyright (C) 2012-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
#define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK BIT(13)
#define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER 0x0
#define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1 BIT(13)
-#define IMX6Q_GPR1_GINT_MASK BIT(12)
-#define IMX6Q_GPR1_GINT_CLEAR 0x0
-#define IMX6Q_GPR1_GINT_ASSERT BIT(12)
+#define IMX6Q_GPR1_GINT BIT(12)
#define IMX6Q_GPR1_ADDRS3_MASK (0x3 << 10)
#define IMX6Q_GPR1_ADDRS3_32MB (0x0 << 10)
#define IMX6Q_GPR1_ADDRS3_64MB (0x1 << 10)
int nvec, int type);
};
-struct msi_chip {
- struct module *owner;
- struct device *dev;
- struct device_node *of_node;
- struct list_head list;
-
- int (*setup_irq)(struct msi_chip *chip, struct pci_dev *dev,
- struct msi_desc *desc);
- void (*teardown_irq)(struct msi_chip *chip, unsigned int irq);
- int (*check_device)(struct msi_chip *chip, struct pci_dev *dev,
- int nvec, int type);
-};
-
#endif /* LINUX_MSI_H */
of_pci_find_msi_chip_by_node(struct device_node *of_node) { return NULL; }
#endif
-#if defined(CONFIG_OF) && defined(CONFIG_PCI_MSI)
-int of_pci_msi_chip_add(struct msi_chip *chip);
-void of_pci_msi_chip_remove(struct msi_chip *chip);
-struct msi_chip *of_pci_find_msi_chip_by_node(struct device_node *of_node);
-#else
-static inline int of_pci_msi_chip_add(struct msi_chip *chip) { return -EINVAL; }
-static inline void of_pci_msi_chip_remove(struct msi_chip *chip) { }
-static inline struct msi_chip *
-of_pci_find_msi_chip_by_node(struct device_node *of_node) { return NULL; }
-#endif
-
#endif
projects / karo-tx-linux.git / commitdiff