xtensa: rename MISC SR definition to avoid name clashes

There are other special register that cause build warnings and may as
well need renaming as well.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>

diff --git a/arch/xtensa/include/asm/regs.h b/arch/xtensa/include/asm/regs.h
index d4baed246928085507a76a5acff71156537bdb69..a3075b12aff112c4f3ed7176fccb8125b9336db8 100644 (file)
--- a/arch/xtensa/include/asm/regs.h
+++ b/arch/xtensa/include/asm/regs.h
@@ -66,7 +66,7 @@
 #define ICOUNTLEVEL    237
 #define EXCVADDR       238
 #define CCOMPARE       240
-#define MISC           244
+#define MISC_SR                244
 
 /*  Special names for read-only and write-only interrupt registers.  */