x86: Look for IA32_ENERGY_PERF_BIAS support

[ upstream commit 23016bf0 ]

The new IA32_ENERGY_PERF_BIAS MSR allows system software to give
hardware a hint whether OS policy favors more power saving,
or more performance.  This allows the OS to have some influence
on internal hardware power/performance tradeoffs where the OS
has previously had no influence.

The support for this feature is indicated by CPUID.06H.ECX.bit3,
as documented in the Intel Architectures Software Developer's Manual.

This patch discovers support of this feature and displays it
as "epb" in /proc/cpuinfo.

Signed-off-by: Venkatesh Pallipadi <venki@google.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
LKML-Reference: <alpine.LFD.2.00.1006032310160.6669@localhost.localdomain>
Signed-off-by: Len Brown <len.brown@intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 14e0ee1b53f660a3d937150fe9abb2b9d82cf6eb..429e4f4857465acce907f89baeefa87b85084da3 100644 (file)
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -162,6 +162,7 @@
 #define X86_FEATURE_IDA                (7*32+ 0) /* Intel Dynamic Acceleration */
 #define X86_FEATURE_ARAT       (7*32+ 1) /* Always Running APIC Timer */
 #define X86_FEATURE_CPB                (7*32+ 2) /* AMD Core Performance Boost */
+#define X86_FEATURE_EPB                (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 0639d9f2df678c6c2873ab1647cda225c0e1b32b..7322e874430530e700e5b25a7ac8a36cbe407c5f 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -243,6 +243,8 @@
 
 #define MSR_IA32_TEMPERATURE_TARGET    0x000001a2
 
+#define MSR_IA32_ENERGY_PERF_BIAS      0x000001b0
+
 /* MISC_ENABLE bits: architectural */
 #define MSR_IA32_MISC_ENABLE_FAST_STRING       (1ULL << 0)
 #define MSR_IA32_MISC_ENABLE_TCC               (1ULL << 1)

diff --git a/arch/x86/kernel/cpu/addon_cpuid_features.c b/arch/x86/kernel/cpu/addon_cpuid_features.c
index 10fa5684a6628e5e095a698d8bc8065748bc4534..7369b4c2c55a2f877e4fb621186ca9e3e9c1f4a0 100644 (file)
--- a/arch/x86/kernel/cpu/addon_cpuid_features.c
+++ b/arch/x86/kernel/cpu/addon_cpuid_features.c
@@ -33,6 +33,7 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
                { X86_FEATURE_IDA,              CR_EAX, 1, 0x00000006 },
                { X86_FEATURE_ARAT,             CR_EAX, 2, 0x00000006 },
                { X86_FEATURE_APERFMPERF,       CR_ECX, 0, 0x00000006 },
+               { X86_FEATURE_EPB,              CR_ECX, 3, 0x00000006 },
                { X86_FEATURE_CPB,              CR_EDX, 9, 0x80000007 },
                { X86_FEATURE_NPT,              CR_EDX, 0, 0x8000000a },
                { X86_FEATURE_LBRV,             CR_EDX, 1, 0x8000000a },