arm64: dts: mt8173: Add clock controller device nodes

This adds the device nodes providing clocks on the Mediatek MT8173.
These are: topckgen, infracfg, pericfg and apmixedsys. These are
fed by two oscillators also added by this patch.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 27237a1c1a87030b41825777e9ce0750892870b3..30b2fdfc82101f20adadcc1fb6314f2442381365 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -11,6 +11,7 @@
  * GNU General Public License for more details.
  */
 
+#include <dt-bindings/clock/mt8173-clk.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "mt8173-pinfunc.h"
@@ -87,6 +88,20 @@
                #clock-cells = <0>;
        };
 
+       clk26m: oscillator@0 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <26000000>;
+               clock-output-names = "clk26m";
+       };
+
+       clk32k: oscillator@1 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <32000>;
+               clock-output-names = "clk32k";
+       };
+
        timer {
                compatible = "arm,armv8-timer";
                interrupt-parent = <&gic>;
@@ -106,11 +121,32 @@
                compatible = "simple-bus";
                ranges;
 
-               /*
-                * Pinctrl access register at 0x10005000 through regmap.
-                * Register 0x1000b000 is used by EINT.
-                */
-               pio: pinctrl@10005000 {
+               topckgen: clock-controller@10000000 {
+                       compatible = "mediatek,mt8173-topckgen";
+                       reg = <0 0x10000000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               infracfg: power-controller@10001000 {
+                       compatible = "mediatek,mt8173-infracfg", "syscon";
+                       reg = <0 0x10001000 0 0x1000>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               pericfg: power-controller@10003000 {
+                       compatible = "mediatek,mt8173-pericfg", "syscon";
+                       reg = <0 0x10003000 0 0x1000>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               syscfg_pctl_a: syscfg_pctl_a@10005000 {
+                       compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
+                       reg = <0 0x10005000 0 0x1000>;
+               };
+
+               pio: pinctrl@0x10005000 {
                        compatible = "mediatek,mt8173-pinctrl";
                        reg = <0 0x1000b000 0 0x1000>;
                        mediatek,pctl-regmap = <&syscfg_pctl_a>;
@@ -138,6 +174,12 @@
                        reg = <0 0x10200620 0 0x20>;
                };
 
+               apmixedsys: clock-controller@10209000 {
+                       compatible = "mediatek,mt8173-apmixedsys";
+                       reg = <0 0x10209000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
                gic: interrupt-controller@10220000 {
                        compatible = "arm,gic-400";
                        #interrupt-cells = <3>;