]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
ARM: 8083/1: exynos: activate the CCI on boot CPU/cluster using the MCPM loopback
authorNicolas Pitre <nicolas.pitre@linaro.org>
Tue, 24 Jun 2014 17:36:32 +0000 (18:36 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Fri, 18 Jul 2014 10:58:04 +0000 (11:58 +0100)
The Chromebook firmware doesn't enable the CCI for the boot cpu, and
arguably it shouldn't have to either. Let's have the kernel handle the

CCI on its own for the boot CPU the same way it does it for secondary CPUs
by using the MCPM loopback.

This allows to boot all 8 cores on exynos5420-peach-pit,
exynos5800-peach-pi and ARM Chromebook 2.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Tushar Behera <tushar.b@samsung.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mach-exynos/mcpm-exynos.c

index ace0ed617476ec113ab431145fc11fa2dfa425af..0d95bc8e49d88f5251e1d864c4bb331bac3cdc52 100644 (file)
@@ -289,6 +289,19 @@ static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
        "b      cci_enable_port_for_self");
 }
 
+static void __init exynos_cache_off(void)
+{
+       if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
+               /* disable L2 prefetching on the Cortex-A15 */
+               asm volatile(
+               "mcr    p15, 1, %0, c15, c0, 3\n\t"
+               "isb\n\t"
+               "dsb"
+               : : "r" (0x400));
+       }
+       exynos_v7_exit_coherency_flush(all);
+}
+
 static const struct of_device_id exynos_dt_mcpm_match[] = {
        { .compatible = "samsung,exynos5420" },
        { .compatible = "samsung,exynos5800" },
@@ -332,6 +345,8 @@ static int __init exynos_mcpm_init(void)
        ret = mcpm_platform_register(&exynos_power_ops);
        if (!ret)
                ret = mcpm_sync_init(exynos_pm_power_up_setup);
+       if (!ret)
+               ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI */
        if (ret) {
                iounmap(ns_sram_base_addr);
                return ret;