packages/devs/flash/arm/mxc/v2_0/src/mxc_nfc.c

   1 //==========================================================================
   2 //
   3 //              mxc_nfc.c
   4 //
   5 //              Flash programming to support NAND flash on Freescale MXC platforms
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //==========================================================================
  41 //#####DESCRIPTIONBEGIN####
  42 //
  43 // Author(s):    Kevin Zhang <k.zhang@freescale.com>
  44 // Contributors: Kevin Zhang <k.zhang@freescale.com>
  45 // Date:                 2006-01-23 Initial version
  46 // Date:                 2007-12-20 Update to support 4K page and bbt management.
  47 // Purpose:
  48 // Description:
  49 //       -- Add bad block management according to Linux NAND MTD implementation.
  50 //              Reference linux/drivers/mtd/nand/nand_bbt.c by Thomas Gleixner
  51 //              Summary:
  52 //                 1. Last 4 blocks are reserved for one main BBT and one
  53 //                        mirror BBT (2 spare ones just in case a block turns bad.)
  54 //                 2. The main BBT block's spare area starts with "Bbt0" followed
  55 //                        by a version number starting from 1.
  56 //                 3. The mirror BBT block's spare area starts with "1tbB" followed
  57 //                        by a version number also starting from 1.
  58 //                 4. The actual main area, starting from first page in the BBT block,
  59 //                        is used to indicate if a block is bad or not through 2bit/block:
  60 //                              * The table uses 2 bits per block
  61 //                              * 11b:  block is good
  62 //                              * 00b:  block is factory marked bad
  63 //                              * 01b:  block is marked bad due to wear
  64 //                              * 10b:  block is marked reserved (for BBT)
  65 //              Redboot operations: During boot, it searches for the marker for
  66 //                                                      either main BBT or mirror BBT based on the marker:
  67 //                 case 1: Neither table is found:
  68 //                                 Do the bad block scan of the whole flash with ECC off. Use
  69 //                                 manufactor marked BI field to decide if a block is bad and
  70 //                                 then build the BBT in RAM. Then write this table to both
  71 //                                 main BBT block and mirror BBT block.
  72 //                 case 2: Only one table is found:
  73 //                                 Load the BBT from the flash and stored in the RAM.
  74 //                                 Then build the 2nd BBT in the flash.
  75 //                 case 3: If both tables found, load the one with higher version in the
  76 //                                 RAM and then update the block with older BBT info with the
  77 //                                 newer one. If same version, just then read out the table in
  78 //                                 RAM.
  79 //
  80 //####DESCRIPTIONEND####
  81 //
  82 //==========================================================================
  83
  84 #include <pkgconf/hal.h>
  85 #include <cyg/hal/hal_arch.h>
  86 #include <cyg/hal/hal_cache.h>
  87 #include <cyg/io/nand_bbt.h>
  88 #include <redboot.h>
  89 #include <stdlib.h>
  90
  91 #include CYGHWR_MEMORY_LAYOUT_H
  92
  93 #include <cyg/hal/hal_io.h>
  94 #define  _FLASH_PRIVATE_
  95 #include <cyg/io/flash.h>
  96
  97 #include CYGHWR_FLASH_NAND_BBT_HEADER
  98
  99 #include <cyg/io/imx_nfc.h>
 100
 101 #define ECC_FORCE_ON    1
 102 #define ECC_FORCE_OFF   2
 103
 104 typedef u64 flash_addr_t;
 105
 106 enum blk_bad_type
 107 {
 108         BLK_GOOD = 0,
 109         BLK_BAD_RUNTIME = 1,
 110         BLK_RESERVED = 2,
 111         BLK_BAD_FACTORY = 3,
 112 };
 113
 114 #define diag_printf1(fmt...) CYG_MACRO_START                                            \
 115                 if (g_nfc_debug_level >= NFC_DEBUG_MIN) diag_printf(fmt);       \
 116 CYG_MACRO_END
 117
 118 #define MXC_UNLOCK_BLK_END              0xFFFF
 119
 120 extern unsigned int hal_timer_count(void);
 121 int nfc_program_region(flash_addr_t addr, u8 *buf, u32 len);
 122 int nfc_erase_region(flash_addr_t addr, u32 len, bool skip_bad, bool verbose);
 123
 124 static int nfc_write_pg_random(u32 pg_no, u32 pg_off, u8 *buf, u32 ecc_force);
 125 static int nfc_read_pg_random(u32 pg_no, u32 pg_off, u32 ecc_force, u32 cs_line,
 126                                                           u32 num_of_nand_chips);
 127 static int nfc_erase_blk(u32 ra);
 128 static void print_page(u32 addr, bool spare_only);
 129 static int nfc_read_page(u32 cs_line, u32 pg_no, u32 pg_off);
 130 static int mxc_nfc_scan(bool lowlevel);
 131 static void read_nflash_id(u32 *id, u32 cs_line);
 132 static int nfc_program_blk(u32 ra, u8 *buf, u32 len);
 133
 134 static void print_pkt_16(u16 *pkt, u32 len);
 135
 136 // globals
 137 static int nand_flash_index = -1;
 138 static int g_ecc_enable = true;
 139 static int g_spare_only_read_ok = true;
 140 static int g_nfc_debug_level = NFC_DEBUG_NONE;
 141 static bool g_nfc_debug_measure = false;
 142 static bool g_is_2k_page = false;
 143 static unsigned int g_block_offset;
 144 static bool g_is_4k_page = false;
 145 static unsigned int g_nfc_version = MXC_NFC_V1; // default to version 1.0
 146 static int      num_of_nand_chips = 1;
 147 static int num_of_nand_chips_for_nandsize = 1;
 148 static int scale_block_cnt = 1;
 149
 150 #define nfc_printf(level, args...) CYG_MACRO_START      \
 151                 if (g_nfc_debug_level >= level)                         \
 152                         diag_printf(args);                                              \
 153 CYG_MACRO_END
 154
 155 #if defined(NFC_V2_0) || defined(NFC_V2_1)
 156 #include <cyg/io/mxc_nfc_v2.h>
 157 #elif defined(NFC_V3_0)
 158 #include <cyg/io/mxc_nfc_v3.h>
 159 #else
 160 #include <cyg/io/mxc_nfc.h>
 161 #endif
 162
 163 #ifndef NAND_LAUNCH_REG
 164 #define NAND_LAUNCH_REG                         0xDEADEEEE
 165 #define NAND_CONFIGURATION1_REG         0xDEADEEEE
 166 #define NFC_FLASH_CONFIG2_REG           0xDEADEEEE
 167 #define NFC_FLASH_CONFIG2_ECC_EN        0xDEADEEEE
 168 #define write_nfc_ip_reg(a, b)
 169 #endif
 170
 171 #ifndef MXCFLASH_SELECT_MULTI
 172 void flash_query(void *data)
 173 #else
 174 void nandflash_query(void *data)
 175 #endif
 176 {
 177         u32 id[2];
 178         read_nflash_id(&id[0], 0);
 179         nfc_printf(NFC_DEBUG_MAX, "%s(ID=0x%02x: 0x%02x, 0x%02x, 0x%02x)\n", __FUNCTION__,
 180                            id[0] & 0xff, (id[0] >> 8) & 0xff, (id[0] >> 16) & 0xff, id[0] >> 24);
 181         memcpy(data, id, sizeof(id));
 182 }
 183
 184 #ifndef MXCFLASH_SELECT_MULTI
 185 int flash_program_buf(void *addr, void *data, int len)
 186 #else
 187 int nandflash_program_buf(void *addr, void *data, int len)
 188 #endif
 189 {
 190         nfc_printf(NFC_DEBUG_MAX, "%s(addr=%p, data=%p, len=0x%08x)\n",
 191                            __FUNCTION__, addr, data, len);
 192         return nfc_program_region((u32)addr, data, len);
 193 }
 194
 195 #ifndef MXCFLASH_SELECT_MULTI
 196 int flash_erase_block(void *block, unsigned int size)
 197 #else
 198 int nandflash_erase_block(void *block, unsigned int size)
 199 #endif
 200 {
 201         nfc_printf(NFC_DEBUG_MAX, "%s(block=%p, size=0x%08x)\n",
 202                            __FUNCTION__, block, size);
 203         return nfc_erase_region((u32)block, size, 1, 0);
 204 }
 205
 206 #ifndef MXCFLASH_SELECT_MULTI
 207 bool flash_code_overlaps(void *start, void *end)
 208 #else
 209 bool nandflash_code_overlaps(void *start, void *end)
 210 #endif
 211 {
 212         extern unsigned char _stext[], _etext[];
 213
 214         return ((((unsigned long)&_stext >= (unsigned long)start) &&
 215                          ((unsigned long)&_stext < (unsigned long)end)) ||
 216                         (((unsigned long)&_etext >= (unsigned long)start) &&
 217                          ((unsigned long)&_etext < (unsigned long)end)));
 218 }
 219
 220 #ifndef MXCFLASH_SELECT_MULTI
 221 int flash_hwr_map_error(int e)
 222 #else
 223 int nandflash_hwr_map_error(int e)
 224 #endif
 225 {
 226         return e;
 227 }
 228
 229 #ifndef MXCFLASH_SELECT_MULTI
 230 int flash_lock_block(void *block)
 231 #else
 232 int nandflash_lock_block(void *block)
 233 #endif
 234 {
 235         // Not supported yet
 236         return 0;
 237 }
 238
 239 #ifndef MXCFLASH_SELECT_MULTI
 240 int flash_unlock_block(void *block, int block_size, int blocks)
 241 #else
 242 int nandflash_unlock_block(void *block, int block_size, int blocks)
 243 #endif
 244 {
 245         // Not supported yet
 246         return 0;
 247 }
 248
 249 //----------------------------------------------------------------------------
 250 // Now that device properties are defined, include magic for defining
 251 // accessor type and constants.
 252 #include <cyg/io/flash_dev.h>
 253
 254 // Information about supported devices
 255 typedef struct flash_dev_info {
 256         cyg_uint16       device_id;
 257         cyg_uint16       device_id2;
 258         cyg_uint16       device_id3;
 259         cyg_uint16       device_id4;
 260         cyg_uint16       page_size;
 261         cyg_uint16       spare_size;
 262         cyg_uint32       pages_per_block;
 263         cyg_uint32       block_size;
 264         cyg_int32        block_count;
 265         cyg_uint32       device_size;
 266         cyg_uint32       port_size;             // x8 or x16 IO
 267         cyg_uint32       type;                  // SLC vs MLC
 268         cyg_uint32       options;
 269         cyg_uint32       fis_start_addr;
 270         cyg_uint32       bi_off;
 271         cyg_uint32       bbt_blk_max_nr;
 272         cyg_uint8        vendor_info[96];
 273         cyg_uint32       col_cycle;                // number of column address cycles
 274         cyg_uint32       row_cycle;                // number of row address cycles
 275         cyg_uint32       max_bad_blk;
 276 } flash_dev_info_t;
 277
 278 static const flash_dev_info_t *flash_dev_info;
 279 static const flash_dev_info_t supported_devices[] = {
 280 #include <cyg/io/mxc_nand_parts.inl>
 281 };
 282 #define NUM_DEVICES NUM_ELEMS(supported_devices)
 283
 284 #define COL_CYCLE                                       flash_dev_info->col_cycle
 285 #define ROW_CYCLE                                       flash_dev_info->row_cycle
 286 #define NF_PG_SZ                                        ((flash_dev_info->page_size) * num_of_nand_chips)
 287 #define NF_SPARE_SZ                                     ((flash_dev_info->spare_size) * num_of_nand_chips)
 288 #define NF_PG_PER_BLK                           flash_dev_info->pages_per_block
 289 #define NF_DEV_SZ                                       ((flash_dev_info->device_size) * num_of_nand_chips_for_nandsize)
 290 #define NF_BLK_SZ                                       ((flash_dev_info->block_size) * num_of_nand_chips)
 291 #define NF_BLK_CNT                                      ((flash_dev_info->block_count) / scale_block_cnt)
 292 #define NF_VEND_INFO                            flash_dev_info->vendor_info
 293 #define NF_OPTIONS                                      flash_dev_info->options
 294 #define NF_BBT_MAX_NR                           flash_dev_info->bbt_blk_max_nr
 295 #define NF_OPTIONS                                      flash_dev_info->options
 296 #define NF_BI_OFF                                       flash_dev_info->bi_off
 297
 298 #define MXC_NAND_ADDR_MASK                              (NF_DEV_SZ - 1)
 299 #define BLOCK_TO_OFFSET(blk)                    ((blk) * NF_PG_PER_BLK * NF_PG_SZ)
 300 #define BLOCK_TO_PAGE(blk)                              ((blk) * NF_PG_PER_BLK)
 301 #define BLOCK_PAGE_TO_OFFSET(blk, pge)  (((blk) * NF_PG_PER_BLK + (pge)) * NF_PG_SZ)
 302 #define OFFSET_TO_BLOCK(offset)                 ((u32)((offset) / (NF_PG_SZ * NF_PG_PER_BLK)))
 303 #define OFFSET_TO_PAGE(offset)                  ((u32)((offset) / NF_PG_SZ) % NF_PG_PER_BLK)
 304
 305 static u8 *g_bbt, *g_page_buf;
 306 static u32 g_bbt_sz;
 307 static bool mxcnfc_init_ok = false;
 308 static bool mxc_nfc_scan_done;
 309
 310 // this callback allows the platform specific function to be called right
 311 // after flash_dev_query()
 312 nfc_setup_func_t *nfc_setup = NULL;
 313
 314 // this callback allows the platform specific iomux setup
 315 nfc_iomuxsetup_func_t *nfc_iomux_setup = NULL;
 316
 317 static flash_addr_t flash_region_start;
 318 static flash_addr_t flash_region_end;
 319 static int flash_enable;
 320
 321 /* This assumes reading the flash with monotonically increasing flash addresses */
 322 static flash_addr_t nfc_l_to_p(flash_addr_t addr)
 323 {
 324         if (g_block_offset == 0) {
 325                 return addr & MXC_NAND_ADDR_MASK;
 326         } else {
 327                 flash_addr_t ra;
 328                 u32 block = (addr & MXC_NAND_ADDR_MASK) / NF_BLK_SZ;
 329                 u32 offset = addr % NF_BLK_SZ;
 330
 331                 ra = (block + g_block_offset) * NF_BLK_SZ + offset;
 332                 if (offset == 0) {
 333                         nfc_printf(NFC_DEBUG_MIN,
 334                                            "Remapping block %u at addr 0x%08llx to block %u at addr 0x%08llx\n",
 335                                            block, (u64)addr, block + g_block_offset, (u64)ra);
 336                 }
 337                 return ra;
 338         }
 339 }
 340
 341 static int flash_addr_valid(flash_addr_t addr)
 342 {
 343         if (!flash_enable) {
 344                 nfc_printf(NFC_DEBUG_MIN, "No flash area enabled\n");
 345                 return 1;
 346         }
 347         if (addr < flash_region_start || addr >= flash_region_end) {
 348                 diag_printf("Flash address 0x%08llx is outside valid region 0x%08llx..0x%08llx\n",
 349                                         (u64)addr, (u64)flash_region_start, (u64)flash_region_end);
 350                 return 0;
 351         }
 352         return 1;
 353 }
 354
 355 /* FIXME: we should pass flash_addr_t as arguments */
 356 void mxc_flash_enable(void *start, void *end)
 357 {
 358         flash_addr_t s = (unsigned long)start & MXC_NAND_ADDR_MASK;
 359         flash_addr_t e = (unsigned long)end & MXC_NAND_ADDR_MASK;
 360
 361         if (flash_enable++ == 0) {
 362                 flash_region_start = s;
 363                 flash_region_end = e;
 364                 diag_printf1("Enabling flash region 0x%08llx..0x%08llx\n",
 365                                          (u64)s, (u64)e);
 366                 g_block_offset = 0;
 367         } else {
 368                 if (s < flash_region_start ||
 369                         e > flash_region_end) {
 370                         diag_printf("** WARNING: Enable 0x%08llx..0x%08llx outside enabled flash region 0x%08llx..0x%08llx\n",
 371                                                 (u64)s, (u64)e, (u64)flash_region_start, (u64)flash_region_end);
 372                 }
 373         }
 374 }
 375
 376 void mxc_flash_disable(void *start, void *end)
 377 {
 378         flash_addr_t s = (unsigned long)start & MXC_NAND_ADDR_MASK;
 379         flash_addr_t e = (unsigned long)end & MXC_NAND_ADDR_MASK;
 380
 381         if (flash_enable) {
 382                 if (--flash_enable == 0) {
 383                         diag_printf1("Disabling flash region 0x%08llx..0x%08llx\n",
 384                                                  (u64)s, (u64)e);
 385                         if (s != flash_region_start ||
 386                                 e != flash_region_end) {
 387                                 diag_printf("** Error: Disable 0x%08llx..0x%08llx not equal to enabled flash region 0x%08llx..0x%08llx\n",
 388                                                 (u64)s, (u64)e, (u64)flash_region_start, (u64)flash_region_end);
 389                         }
 390                 }
 391         } else {
 392                 diag_printf("** Error: unbalanced call to flash_disable()\n");
 393         }
 394 }
 395
 396 int
 397 #ifndef MXCFLASH_SELECT_MULTI
 398 flash_hwr_init(void)
 399 #else
 400 nandflash_hwr_init(void)
 401 #endif
 402 {
 403         u32 id[2];
 404         int i;
 405
 406         nfc_printf(NFC_DEBUG_MAX, "%s()\n", __FUNCTION__);
 407
 408         if (nfc_iomux_setup)
 409                 nfc_iomux_setup();
 410
 411         NFC_SET_NFC_ACTIVE_CS(0);
 412         NFC_CMD_INPUT(FLASH_Reset);
 413
 414         // Look through table for device data
 415         flash_dev_query(&id[0]);
 416         flash_dev_info = supported_devices;
 417         for (i = 0; i < NUM_DEVICES; i++) {
 418                 if ((flash_dev_info->device_id == (id[0] & 0xffff)) &&
 419                         (flash_dev_info->device_id2 == 0xFFFF ||
 420                          flash_dev_info->device_id2 == (id[0] >> 16)))
 421                         break;
 422                 flash_dev_info++;
 423         }
 424
 425         // Did we find the device? If not, return error.
 426         if (NUM_DEVICES == i) {
 427                 diag_printf("Unrecognized NAND part: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
 428                                         id[0] & 0xff, (id[0] >> 8) & 0xff, (id[0] >> 16) & 0xff, id[0] >> 24);
 429                 return FLASH_ERR_DRV_WRONG_PART;
 430         }
 431
 432         nand_flash_index = i;
 433         mxcnfc_init_ok = true;
 434
 435         if (NF_PG_SZ == 2048) {
 436                 g_is_2k_page = true;
 437                 g_spare_only_read_ok = false;
 438         }
 439         if (NF_PG_SZ == 4096) {
 440                 g_is_4k_page = true;
 441                 g_spare_only_read_ok = false;
 442         }
 443
 444         nfc_printf(NFC_DEBUG_MED, "%s(): %d out of NUM_DEVICES=%d, id=0x%02x\n",
 445                            __FUNCTION__, i, NUM_DEVICES, flash_dev_info->device_id);
 446
 447         if (nfc_setup) {
 448                 g_nfc_version = nfc_setup(NF_PG_SZ / num_of_nand_chips, flash_dev_info->port_size,
 449                                                                   flash_dev_info->type, num_of_nand_chips);
 450         }
 451         diag_printf1("NFC version: %02x\n", g_nfc_version);
 452         if (g_nfc_version == MXC_NFC_V3) {
 453                 for (i = 2; i <= NUM_OF_CS_LINES; i++) {
 454                         u32 id_tmp[2];
 455                         read_nflash_id(&id_tmp[0], i - 1);
 456                         if (id[0] != id_tmp[0]) {
 457                                 break;
 458                         }
 459                         /* Support interleave with 1, 2, 4, 8 chips */
 460                         if (i == (num_of_nand_chips * 2)) {
 461                                 num_of_nand_chips = i;
 462                         }
 463                         NFC_CMD_INPUT(FLASH_Reset);
 464                 }
 465
 466                 if (nfc_setup && (num_of_nand_chips > 1)) {
 467                         nfc_setup(NF_PG_SZ / num_of_nand_chips, flash_dev_info->port_size,
 468                                                    flash_dev_info->type, num_of_nand_chips);
 469                 }
 470         }
 471
 472         NFC_ARCH_INIT();
 473
 474         g_bbt_sz = NF_BLK_CNT / 4;
 475         g_bbt = malloc(g_bbt_sz); // two bit for each block
 476         if (g_bbt == NULL) {
 477                 diag_printf("%s(): failed to allocate %d byte for bbt\n", __FUNCTION__, g_bbt_sz);
 478                 return FLASH_ERR_PROTOCOL;
 479         }
 480
 481         g_page_buf = malloc(NF_PG_SZ); // for programming less than one page size buffer
 482         if (g_page_buf == NULL) {
 483                 diag_printf("%s(): failed to allocate %d byte page buffer\n", __FUNCTION__,
 484                                         NF_PG_SZ);
 485                 return FLASH_ERR_PROTOCOL;
 486         }
 487         memset(g_bbt, 0, g_bbt_sz);
 488
 489         /* For now cap off the Device size to 2GB */
 490         i = 1;
 491         while ((i <= num_of_nand_chips) && ((NF_DEV_SZ * i) < 0x80000000)) {
 492                 num_of_nand_chips_for_nandsize = i;
 493                 i *= 2;
 494         }
 495
 496         scale_block_cnt = num_of_nand_chips / num_of_nand_chips_for_nandsize;
 497         // Hard wired for now
 498         flash_info.block_size = NF_BLK_SZ;
 499         flash_info.blocks = NF_BLK_CNT - CYGNUM_FLASH_NAND_BBT_BLOCKS;
 500         flash_info.start = (void *)MXC_NAND_BASE_DUMMY;
 501         flash_info.end = (void *)(MXC_NAND_BASE_DUMMY + NF_DEV_SZ -
 502                                                           CYGNUM_FLASH_NAND_BBT_BLOCKS * NF_BLK_SZ);
 503
 504         mxc_nfc_scan(false); // look for table
 505
 506         diag_printf1("%s(): block_size=0x%08x, blocks=0x%08x, start=%p, end=%p\n",
 507                                  __FUNCTION__, flash_info.block_size, flash_info.blocks,
 508                                  flash_info.start, flash_info.end);
 509
 510         return FLASH_ERR_OK;
 511 }
 512
 513 // used by redboot/current/src/flash.c
 514 int mxc_nand_fis_start(void)
 515 {
 516         return flash_dev_info->fis_start_addr * num_of_nand_chips;
 517 }
 518
 519 static inline u8 get_byte(cyg_uint16 *buf, int offs)
 520 {
 521         cyg_uint16 word = buf[offs >> 1];
 522         if (offs & 1) {
 523                 return word >> 8;
 524         }
 525         return word & 0xff;
 526 }
 527
 528 static inline void store_byte(cyg_uint16 *buf, int offs, u8 val)
 529 {
 530         cyg_uint16 word = buf[offs >> 1];
 531
 532         if (offs & 1) {
 533                 word = (word & 0x00ff) | ((u16)val << 8);
 534         } else {
 535                 word = (word & 0xff00) | val;
 536         }
 537         buf[offs >> 1] = word;
 538 }
 539
 540 static inline bool nfc_verify_addr(unsigned long dst, unsigned long len)
 541 {
 542         if (dst < NAND_MAIN_BUF0 || dst + len >= NAND_SPAR_BUF3 + NFC_SPARE_BUF_SZ) {
 543                 diag_printf("%s: Bad NFC Buffer address 0x%08lx\n", __FUNCTION__, dst);
 544                 return false;
 545         }
 546         return true;
 547 }
 548
 549 static void nfc_buf_read(void *dst, unsigned long src, u32 len)
 550 {
 551         u16 *s = (u16 *)(src & ~1);
 552         u8 *bp = dst;
 553
 554         if (len == 0) {
 555                 return;
 556         }
 557         if (src + len < src) {
 558                 diag_printf("%s: Bad address range 0x%08lx .. 0x%08lx\n", __FUNCTION__,
 559                                         src, src + len);
 560         }
 561         if ((unsigned long)dst + len < (unsigned long)dst) {
 562                 diag_printf("%s: Bad address range 0x%08lx .. 0x%08lx\n", __FUNCTION__,
 563                                         (unsigned long)dst, (unsigned long)dst + len);
 564         }
 565         if (src < NAND_MAIN_BUF0 || src + len >= NAND_SPAR_BUF3 + NF_PG_SZ) {
 566                 diag_printf("%s: Bad NFC Buffer address 0x%08lx\n", __FUNCTION__, src);
 567                 return;
 568         }
 569         if ((unsigned long)dst >= NAND_MAIN_BUF0 &&
 570                 (unsigned long)dst < NAND_SPAR_BUF3 + NF_PG_SZ) {
 571                 diag_printf("%s: Bad memory address 0x%08lx\n", __FUNCTION__,
 572                                         (unsigned long)dst);
 573                 return;
 574         }
 575         if (src & 1) {
 576                 *bp++ = get_byte(s, 1);
 577                 s++;
 578                 len--;
 579         }
 580         if ((unsigned long)bp & 1) {
 581                 while (len > 1) {
 582                         u16 word = *s++;
 583                         *bp++ = word & 0xff;
 584                         *bp++ = word >> 8;
 585                         len -= 2;
 586                 }
 587         } else {
 588                 u16 *wp = (u16 *)bp;
 589
 590                 while (len > 1) {
 591                         *wp++ = *s++;
 592                         len -= 2;
 593                 }
 594                 bp = (u8*)wp;
 595         }
 596         if (len != 0) {
 597                 u16 word = *s;
 598                 *bp = word & 0xff;
 599         }
 600 }
 601
 602 static void nfc_buf_write(unsigned long dst, void *src, u32 len)
 603 {
 604         u8 *bp = src;
 605         u16 *d = (u16 *)(dst & ~1);
 606
 607         if (len == 0) {
 608                 return;
 609         }
 610         if (!nfc_verify_addr(dst, len)) {
 611                 return;
 612         }
 613         if (dst & 1) {
 614                 store_byte(d, 1, *bp);
 615                 d++;
 616                 bp++;
 617                 len--;
 618         }
 619         if ((unsigned long)bp & 1) {
 620                 while (len > 1) {
 621                         u16 word;
 622                         word = *bp++;
 623                         word |= (u16)(*bp++) << 8;
 624                         *d++ = word;
 625                         len -= 2;
 626                 }
 627         } else {
 628                 u16 *wp = (u16 *)bp;
 629                 while (len > 1) {
 630                         *d++ = *wp++;
 631                         len -= 2;
 632                 }
 633                 bp = (u8 *)wp;
 634         }
 635         if (len != 0) {
 636                 store_byte(d, 1, *bp);
 637         }
 638 }
 639
 640 #ifndef NFC_V3_0
 641 /*!
 642  * Starts the address input cycles for different operations as defined in ops.
 643  *
 644  * @param ops                   operations as defined in enum nfc_addr_ops
 645  * @param pg_no                 page number offset from 0
 646  * @param pg_off                byte offset within the page
 647  * @param is_erase              don't care for earlier NFC
 648  * @param cs_line                don't care for earlier NFC
 649  */
 650 static void start_nfc_addr_ops(u32 ops, u32 pg_no, u32 pg_off, u32 is_erase,
 651                                    u32 cs_line, u32 num_of_chips)
 652 {
 653         int i;
 654
 655         switch (ops) {
 656         case FLASH_Read_ID:
 657                 /* Only supports one NAND chip (CS0) */
 658                 if (cs_line != 0)
 659                         return;
 660                 NFC_ADDR_INPUT(0);
 661                 return;
 662         case FLASH_Read_Mode1:
 663         case FLASH_Program:
 664                 for (i = 0; i < COL_CYCLE; i++, pg_off >>= 8) {
 665                         NFC_ADDR_INPUT(pg_off & 0xFF);
 666                 }
 667                 // don't break on purpose
 668         case FLASH_Block_Erase:
 669                 for (i = 0; i < ROW_CYCLE; i++, pg_no >>= 8) {
 670                         NFC_ADDR_INPUT(pg_no & 0xFF);
 671                 }
 672                 break;
 673         default:
 674                 diag_printf("!!!!!! %s(): wrong ops: %d !!!!!\n", __FUNCTION__, ops);
 675                 return;
 676         }
 677 }
 678 #endif                                  // #ifndef NFC_V3_0
 679
 680 static void read_nflash_id(u32 *id, u32 cs_line)
 681 {
 682         volatile u32 *ptr = (volatile u32*)NAND_MAIN_BUF0;
 683
 684     nfc_printf(NFC_DEBUG_MIN, "%s: read flash id from chip %d @ %p\n",
 685                            __FUNCTION__, cs_line, ptr);
 686
 687         NFC_PRESET(MXC_UNLOCK_BLK_END);
 688         NFC_SET_NFC_ACTIVE_CS(cs_line);
 689         NFC_CMD_INPUT(FLASH_Read_ID);
 690
 691         start_nfc_addr_ops(FLASH_Read_ID, 0, 0, 0, cs_line, num_of_nand_chips);
 692         NFC_DATA_OUTPUT(RAM_BUF_0, FDO_FLASH_ID, g_ecc_enable);
 693
 694     *id++ = *ptr++;
 695     *id++ = *ptr++;
 696 }
 697
 698 static void mark_blk_bad(unsigned int block, unsigned char *buf,
 699                                                  enum blk_bad_type bad_type)
 700 {
 701         unsigned int off = block >> 2;           // byte offset - each byte can hold status for 4 blocks
 702         unsigned int sft = (block & 3) << 1;  // bit shift 0, 2, 4, 6
 703         unsigned char val = buf[off];
 704
 705         if (block > NF_BLK_CNT) {
 706                 diag_printf("%s: Block number %u out of range: 0..%u\n", __FUNCTION__,
 707                                         block, NF_BLK_CNT - 1);
 708                 return;
 709         }
 710         val = (val & ~(3 << sft)) | (bad_type << sft);
 711         buf[off] = val;
 712 }
 713
 714 /*!
 715  * Checks to see if a block is bad. If buf is not NULL, it indicates a valid
 716  * BBT in the RAM. In this case, it assumes to have 2-bit to represent each
 717  * block for good or bad
 718  *                              * 11b:  block is good
 719  *                              * 00b:  block is factory marked bad
 720  *                              * 01b:  block is marked bad due to wear
 721  *                              * 10b:  block is marked reserved (for BBT)
 722  * If buf is NULL, then it indicates a low level scan based on the certain
 723  * offset value in certain pages and certain offset to be non-0xFF. In this
 724  * case, the HW ECC will be turned off.
 725  *
 726  * @param block         0-based block number
 727  * @param buf           BBT buffer. Could be NULL (see above explanation)
 728  *
 729  * @return                      1 if bad block; 0 otherwise
 730  */
 731 static int nfc_is_badblock(u32 block, u8 *buf)
 732 {
 733         u32 off;           // byte offset
 734         u32 sft;           // bit shift 0, 2, 4, 6
 735         flash_addr_t addr;
 736         u16 temp, i;
 737         int res;
 738         u32 pg_no;
 739
 740         if (buf) {
 741                 // use BBT
 742                 off = block >> 2;               // byte offset
 743                 sft = (block & 3) << 1;  // bit shift 0, 2, 4, 6
 744                 res = (buf[off] >> sft) & 0x3;
 745                 if (res) {
 746                         addr = BLOCK_TO_OFFSET(block);
 747                         diag_printf1("Block %u at 0x%08llx is marked %s (%d) in BBT@%p[%02x] mask %02x\n",
 748                                                  block, (u64)addr, res == BLK_RESERVED ? "reserved" :
 749                                                  res == BLK_BAD_FACTORY ? "factory bad" : "runtime bad",
 750                                                  res, buf, off, 3 << sft);
 751                 }
 752                 return res;
 753         }
 754
 755         // need to do low level scan with ECC off
 756         if (NF_OPTIONS & NAND_BBT_SCANLSTPAGE) {
 757                 if (g_is_4k_page || g_is_2k_page) {
 758                         addr = (block + 1) * NF_BLK_SZ - NF_PG_SZ;
 759                         pg_no = addr / NF_PG_SZ;
 760                         for (i = 0; i < num_of_nand_chips; i++) {
 761                                 // we don't do partial page read here. No ecc either
 762                                 nfc_read_pg_random(pg_no, 0, ECC_FORCE_OFF, i, num_of_nand_chips);
 763                                 temp = readw((u32)NAND_MAIN_BUF0 + NF_BI_OFF);
 764                                 if ((temp & 0xFF) != 0xFF) {
 765                                         return BLK_BAD_FACTORY;
 766                                 }
 767                         }
 768                 } else {
 769                         diag_printf("only 2K/4K page is supported\n");
 770                         // die here -- need to fix the SW
 771                         while (1);
 772                 }
 773                 return 0;
 774         }
 775         addr = block * NF_BLK_SZ;
 776         pg_no = addr / NF_PG_SZ;
 777         for (i = 0; i < num_of_nand_chips; i++) {
 778                 nfc_read_pg_random(pg_no, 0, ECC_FORCE_OFF, i, num_of_nand_chips); // no ecc
 779                 if (g_is_2k_page || g_is_4k_page) {
 780                         temp = readw(NAND_MAIN_BUF0 + NF_BI_OFF);
 781                 } else {
 782                         temp = readw(NAND_SPAR_BUF0 + 4) >> 8; // BI is at 5th byte in spare area
 783                 }
 784                 if ((temp & 0xFF) != 0xFF) {
 785                         return BLK_BAD_FACTORY;
 786                 }
 787         }
 788         if (NF_OPTIONS & NAND_BBT_SCAN2NDPAGE) {
 789                 addr += NF_PG_SZ;
 790                 pg_no++;
 791                 for (i = 0; i < num_of_nand_chips; i++) {
 792                         nfc_read_pg_random(pg_no, 0, ECC_FORCE_OFF, i, num_of_nand_chips); // no ecc
 793                         if (g_is_2k_page || g_is_4k_page) {
 794                                 temp = readw(NAND_MAIN_BUF0 + NF_BI_OFF);
 795                         } else {
 796                                 temp = readw(NAND_SPAR_BUF0 + 4) >> 8; // BI is at 5th byte in spare area
 797                         }
 798                         if ((temp & 0xFF) != 0xFF) {
 799                                 return BLK_BAD_FACTORY;
 800                         }
 801                 }
 802         }
 803         return 0;
 804 }
 805
 806 /*
 807  * check_short_pattern - [GENERIC] check if a pattern is in the buffer
 808  * @buf:        the buffer to search
 809  * @td:         search pattern descriptor
 810  *
 811  * Check for a pattern at the given place. Used to search bad block
 812  * tables and good / bad block identifiers.
 813 */
 814 static int check_short_pattern(void *buf, struct nand_bbt_descr *td)
 815 {
 816         int i;
 817
 818         for (i = 0; i < td->len; i++) {
 819                 if (get_byte(buf, td->offs + i) != td->pattern[i]) {
 820                         return -1;
 821                 }
 822         }
 823         return 0;
 824 }
 825
 826 static int nfc_write_page(u32 pg_no, u32 pg_off, u32 ecc_force);
 827 /*
 828  * Program g_bbt into the NAND block with offset at g_main_bbt_addr.
 829  * This assumes that the g_bbt has been built already.
 830  *
 831  * If g_main_bbt_addr is 0, search for a free block from the bottom 4 blocks (but make
 832  * sure not re-using the mirror block). If g_mirror_bbt_page is 0, do the same thing.
 833  * Otherwise, just use g_main_bbt_addr, g_mirror_bbt_page numbers to prgram the
 834  * g_bbt into those two blocks.
 835  * todo: need to do the version to see which one is newer.
 836  *
 837  * @return      0 if successful; -1 otherwise.
 838  */
 839 static int mxc_nfc_write_bbt_page(struct nand_bbt_descr *td)
 840 {
 841         int ret;
 842         u32 block = td->pages / NF_PG_PER_BLK;
 843         flash_addr_t addr = td->pages * NF_PG_SZ;
 844
 845         ret = nfc_erase_blk(addr);
 846         if (ret != 0) {
 847                 diag_printf("Failed to erase bbt block %u\n", block);
 848                 return ret;
 849         }
 850         ret = nfc_write_page(td->pages, 0, 0);
 851         if (ret != 0) {
 852                 diag_printf("Failed to write bbt block %u\n", block);
 853                 return ret;
 854         }
 855         mark_blk_bad(block, g_bbt, BLK_RESERVED);
 856         return 0;
 857 }
 858
 859 static inline void mxc_nfc_buf_clear(unsigned long buf, u8 pattern, int size)
 860 {
 861         int i;
 862         u16 *p = (u16 *)buf;
 863         u16 fill = pattern;
 864
 865         fill = (fill << 8) | pattern;
 866         for (i = 0; i < size >> 1; i++) {
 867                 p[i] = fill;
 868         }
 869 }
 870
 871 static int mxc_nfc_write_bbt(struct nand_bbt_descr *td, struct nand_bbt_descr *md)
 872 {
 873         int ret = -1;
 874         int block;
 875         int pg_offs = 0;
 876         int page = 0;
 877         u16 *buf = (u16 *)NAND_MAIN_BUF0;
 878
 879         for (block = NF_BLK_CNT - 1; block >= NF_BLK_CNT - td->maxblocks - 1; block--) {
 880                 int pg = block * NF_PG_PER_BLK;
 881
 882                 if ((nfc_is_badblock(block, g_bbt) & 1) == 0) {
 883                         if (md != NULL && md->pages == pg) {
 884                                 continue;
 885                         }
 886                         td->pages = pg;
 887                         break;
 888                 }
 889         }
 890         if (td->pages < 0) {
 891                 return -1;
 892         }
 893         mxc_nfc_buf_clear(NAND_SPAR_BUF0, 0xff, NF_SPARE_SZ);
 894         mxc_nfc_buf_clear(NAND_MAIN_BUF0, 0xff, NF_PG_SZ);
 895         diag_printf1("%s: Updating bbt %c%c%c%c version %d\n", __FUNCTION__,
 896                                  td->pattern[0], td->pattern[1], td->pattern[2], td->pattern[3], td->version);
 897         nfc_buf_write(NAND_SPAR_BUF0 + td->offs, td->pattern, td->len);
 898         store_byte((u16 *)NAND_SPAR_BUF0, td->veroffs, td->version);
 899
 900         for (block = 0, pg_offs = 0; block < NF_BLK_CNT; pg_offs++) {
 901                 u16 tmp = 0xffff;
 902                 int i;
 903
 904                 if (pg_offs << 1 >= NF_PG_SZ) {
 905                         ret = mxc_nfc_write_bbt_page(td);
 906                         if (ret != 0) {
 907                                 return ret;
 908                         }
 909                         page++;
 910                         mxc_nfc_buf_clear(NAND_SPAR_BUF0, 0xff, NF_SPARE_SZ);
 911                         mxc_nfc_buf_clear(NAND_MAIN_BUF0, 0xff, NF_PG_SZ);
 912                         pg_offs = 0;
 913                 }
 914                 for (i = 0; i < 16 && block < NF_BLK_CNT; i += 2, block++) {
 915                         u8 code = nfc_is_badblock(block, g_bbt);
 916                         if ((code & 1) != 0) {
 917                                 tmp &= ~(code << i);
 918                                 diag_printf1("%s: bad block %u pattern[%p] 0x%04x mask 0x%04x\n", __FUNCTION__,
 919                                                          block, &buf[pg_offs], tmp, 0x03 << i);
 920                         }
 921                 }
 922                 buf[pg_offs] = tmp;
 923         }
 924         if (pg_offs > 0) {
 925                 diag_printf1("%s: Writing final bbt block %d page %d\n", __FUNCTION__,
 926                                          td->pages / NF_PG_PER_BLK, page);
 927                 ret = mxc_nfc_write_bbt_page(td);
 928         }
 929         return ret;
 930 }
 931
 932 static int mxc_nfc_update_bbt(struct nand_bbt_descr *td, struct nand_bbt_descr *md)
 933 {
 934         int ret;
 935
 936         if (td == NULL) {
 937                 return -1;
 938         }
 939         if (td->pages < 0 && (md == NULL || md->pages == -1)) {
 940                 td->version = 1;
 941         } else {
 942                 if (md != NULL && md->pages >= 0) {
 943                         if (md->version >= td->version) {
 944                                 td->version = ++md->version;
 945                         } else {
 946                                 md->version = ++td->version;
 947                         }
 948                 } else {
 949                         td->version++;
 950                 }
 951         }
 952         ret = mxc_nfc_write_bbt(td, md);
 953         if (ret) {
 954                 diag_printf("** Error: Failed to update main BBT\n");
 955         }
 956         if (md) {
 957                 ret = mxc_nfc_write_bbt(md, td);
 958                 if (ret) {
 959                         diag_printf("** Error: Failed to update mirror BBT\n");
 960                 }
 961         }
 962         return ret;
 963 }
 964
 965 static int program_bbt_to_flash(void)
 966 {
 967         return mxc_nfc_update_bbt(g_mxc_nfc_bbt_main_descr, g_mxc_nfc_bbt_mirror_descr);
 968 }
 969
 970 /*!
 971  * Unconditionally erase a block without checking the BI field.
 972  * Note that there is NO error checking for passed-in ra.
 973  *
 974  * @param ra            starting address in the raw address space (offset)
 975  *                                      Must be block-aligned
 976  * @return                      0 if successful; -1 otherwise
 977  */
 978 static int nfc_erase_blk(u32 ra)
 979 {
 980         u16 flash_status, i;
 981         u32 pg_no, pg_off;
 982
 983         if (g_nfc_version == MXC_NFC_V3) {
 984                 // combine the two commands for erase
 985                 writel((FLASH_Start_Erase << 8) | FLASH_Block_Erase, NAND_CMD_REG);
 986                 pg_no = ra / NF_PG_SZ;
 987                 pg_off = ra % NF_PG_SZ;
 988                 for (i = 0; i < num_of_nand_chips; i++) {
 989                         start_nfc_addr_ops(FLASH_Block_Erase, pg_no, pg_off, 1, i, num_of_nand_chips);
 990                         // start auto-erase
 991                         writel(NAND_LAUNCH_AUTO_ERASE, NAND_LAUNCH_REG);
 992                         wait_op_done();
 993                         pg_off = 0;
 994                 }
 995                 flash_status = NFC_STATUS_READ();
 996                 // check I/O bit 0 to see if it is 0 for success
 997                 if ((flash_status & ((0x1 << num_of_nand_chips) - 1)) != 0) {
 998                         return -1;
 999                 }
1000         } else {
1001                 NFC_CMD_INPUT(FLASH_Block_Erase);
1002                 start_nfc_addr_ops(FLASH_Block_Erase, ra / NF_PG_SZ, ra % NF_PG_SZ,
1003                                                    1, 0, num_of_nand_chips);
1004                 NFC_CMD_INPUT(FLASH_Start_Erase);
1005
1006                 flash_status = NFC_STATUS_READ();
1007
1008                 // check I/O bit 0 to see if it is 0 for success
1009                 if ((flash_status & 0x1) != 0) {
1010                         return -1;
1011                 }
1012         }
1013         return 0;
1014 }
1015
1016 /*!
1017  * Program a block of data in the flash. This function doesn't do
1018  * bad block checking. But if program fails, it return error.
1019  * Note: If "len" is less than a block it will program up to a page's
1020  *               boundary. If not within a page boundary, then it fills the
1021  *               rest of the page with 0xFF.
1022  *
1023  * @param ra            destination raw flash address
1024  * @param buf           source address in the RAM
1025  * @param len           len to be programmed
1026  *
1027  * @return                      0 if successful; -1 otherwise
1028  */
1029 static int nfc_program_blk(u32 ra, u8 *buf, u32 len)
1030 {
1031         u32 temp = num_of_nand_chips;
1032
1033         /* Needed when romupdate is called */
1034         if (ra == 0)
1035                 num_of_nand_chips = 1;
1036
1037         for (; len >= NF_PG_SZ; len -= NF_PG_SZ) {
1038                 if (nfc_write_pg_random(ra / NF_PG_SZ, ra % NF_PG_SZ, buf, 0) != 0) {
1039                         return -1;
1040                 }
1041                 ra += NF_PG_SZ;
1042                 buf += NF_PG_SZ;
1043         }
1044         if (len != 0) {
1045                 memset(g_page_buf + len, 0xFF, NF_PG_SZ - len);
1046                 memcpy(g_page_buf, buf, len);
1047                 if (nfc_write_pg_random(ra / NF_PG_SZ, ra % NF_PG_SZ, g_page_buf, 0) != 0) {
1048                         num_of_nand_chips = temp;
1049                         return -1;
1050                 }
1051         }
1052         num_of_nand_chips = temp;
1053         return 0;
1054 }
1055
1056 /*!
1057  * Erase a range of NAND flash good blocks only.
1058  * It skips bad blocks and update the BBT once it sees new bad block due to erase.
1059  * @param addr                  raw NAND flash address. it has to be block size aligned
1060  * @param len                   number of bytes
1061  * @param skip_bad              if 1, don't erase bad block; otherwise, always erase
1062  * @param verbose               use true to print more messages
1063  *
1064  * @return                              FLASH_ERR_OK (0) if successful; non-zero otherwise
1065  */
1066 int nfc_erase_region(flash_addr_t addr, u32 len, bool skip_bad, bool verbose)
1067 {
1068         u32 sz, blk, update = 0, j = 0;
1069
1070         nfc_printf(NFC_DEBUG_MED, "%s: addr=0x%08llx len=0x%08x\n",
1071                            __FUNCTION__, (u64)addr, len);
1072
1073         if ((addr % NF_BLK_SZ) != 0) {
1074                 diag_printf("Error: flash address 0x%08llx not block aligned\n", addr);
1075                 return FLASH_ERR_INVALID;
1076         }
1077         if ((len % NF_BLK_SZ) != 0 || len == 0) {
1078                 diag_printf("Error: invalid length %u (must be > 0 and block aligned)\n", len);
1079                 return FLASH_ERR_INVALID;
1080         }
1081         addr &= MXC_NAND_ADDR_MASK;
1082         // now addr has to be block aligned
1083         for (sz = 0; sz < len; addr += NF_BLK_SZ, j++, sz += NF_BLK_SZ) {
1084                 if (!flash_addr_valid(addr)) {
1085                         return 0;
1086                 }
1087                 blk = OFFSET_TO_BLOCK(addr);
1088                 if (skip_bad && nfc_is_badblock(blk, g_bbt)) {
1089                         diag_printf("\nSkipping bad block %u at addr 0x%08llx\n",
1090                                                 blk, (u64)addr);
1091                         continue;
1092                 }
1093                 if (nfc_erase_blk(addr) != 0) {
1094                         diag_printf("\n** Error: Failed to erase block %u at addr 0x%08llx\n",
1095                                             blk, (u64)addr);
1096                         mark_blk_bad(blk, g_bbt, BLK_BAD_RUNTIME);
1097                         // we don't need to update the table immediately here since even
1098                         // with power loss now, we should see the same erase error again.
1099                         update++;
1100                         continue;
1101                 }
1102                 if (verbose) {
1103                         if ((j % 0x20) == 0)
1104                                 diag_printf("\n%s 0x%08llx: ", skip_bad ? "Erase" : "FORCE erase", (u64)addr);
1105                         diag_printf(".");
1106                 }
1107         }
1108         if (update) {
1109                 if (program_bbt_to_flash() != 0) {
1110                         diag_printf("\nError: Failed to update bad block table\n");
1111                         return FLASH_ERR_PROGRAM;
1112                 }
1113                 diag_printf("\nnew bad blocks=%d\n", update);
1114         }
1115         return FLASH_ERR_OK;
1116 }
1117
1118 /*!
1119  * Program a range of NAND flash in blocks only.
1120  * It skips bad blocks and update the BBT once it sees new bad block due to program.
1121  * @param addr                  raw NAND flash address. it has to be block size aligned
1122  * @param len                   number of bytes
1123  * @return                              FLASH_ERR_OK (0) if successful; non-zero otherwise
1124  */
1125 int nfc_program_region(flash_addr_t addr, u8 *buf, u32 len)
1126 {
1127         u32 sz, blk, update = 0, partial_block_size;
1128
1129         nfc_printf(NFC_DEBUG_MED, "%s: addr=0x%08llx, len=0x%08x\n",
1130                            __FUNCTION__, (u64)addr, len);
1131
1132         if ((addr % (NF_PG_SZ / num_of_nand_chips)) != 0) {
1133                 diag_printf("Error: flash address 0x%08llx not page aligned\n", (u64)addr);
1134                 return FLASH_ERR_INVALID;
1135         }
1136         if (len == 0) {
1137                 diag_printf("Error: invalid length\n");
1138                 return FLASH_ERR_INVALID;
1139         }
1140
1141         partial_block_size = addr % NF_BLK_SZ;
1142
1143         mxc_nfc_buf_clear(NAND_SPAR_BUF0, 0xff, NF_SPARE_SZ);
1144         addr = nfc_l_to_p(addr);
1145         while (1) {
1146                 if (!flash_addr_valid(addr)) {
1147                         diag_printf("\nToo many bad blocks in flash region 0x%08llx..0x%08llx\n",
1148                                                 (u64)flash_region_start, (u64)flash_region_end);
1149                         return FLASH_ERR_INVALID;
1150                 }
1151                 blk = OFFSET_TO_BLOCK(addr);
1152                 if (nfc_is_badblock(blk, g_bbt)) {
1153                         diag_printf("\nSkipping bad block %u at addr 0x%08llx\n", blk, addr);
1154                         goto incr_address;
1155                 }
1156
1157                 sz = (len >= partial_block_size) ? partial_block_size : len;
1158
1159                 if (nfc_program_blk(addr, buf, sz) != 0) {
1160                         update++;
1161                         diag_printf("\nError: Failed to program flash block %u at addr 0x%08llx\n",
1162                                                 blk, (u64)addr);
1163                         mark_blk_bad(blk, g_bbt, BLK_BAD_RUNTIME);
1164                         // we don't need to update the table immediately here since even
1165                         // with power loss now, we should see the same program error again.
1166                         goto incr_address;
1167                 }
1168                 diag_printf(".");
1169
1170                 len -= sz;
1171                 buf += sz;
1172                 if (len == 0)
1173                         break;
1174
1175 incr_address:
1176                 addr += partial_block_size;
1177                 partial_block_size = NF_BLK_SZ;
1178                 g_block_offset++;
1179         }
1180         if (update) {
1181                 if (program_bbt_to_flash() != 0) {
1182                         diag_printf("\nError: Failed to update bad block table\n");
1183                         return -1;
1184                 }
1185         }
1186         return FLASH_ERR_OK;
1187 }
1188
1189 /*!
1190  * Read data from raw NAND flash address to memory. The MSB of the passed-
1191  * in flash address will be masked off inside the function.
1192  * It skips bad blocks and read good blocks of data for "len" bytes.
1193  *
1194  * @param addr                  NAND flash address.
1195  * @param buf                   memory buf where data will be copied to
1196  * @param len                   number of bytes
1197  * @return                              FLASH_ERR_OK (0) if successful; non-zero otherwise
1198  */
1199 int nfc_read_region(flash_addr_t addr, u8 *buf, u32 len)
1200 {
1201         u32 start_point = 0, pg_no;
1202         unsigned int offset = addr % NF_PG_SZ;
1203         int chk_bad = 1;
1204
1205         nfc_printf(NFC_DEBUG_MED, "%s: addr=0x%08llx, offset=%03x buf=0x%p, len=0x%08x\n",
1206                            __FUNCTION__, addr, offset, buf, len);
1207
1208         addr = nfc_l_to_p(addr);
1209         if (addr < (u32)flash_info.start || (addr + len) > (u32)flash_info.end || len == 0) {
1210                 diag_printf("** Error: flash address 0x%08llx..0x%08llx outside valid range %p..%p\n",
1211                                         (u64)addr, (u64)addr + len - 1, flash_info.start, flash_info.end);
1212                 return FLASH_ERR_INVALID;
1213         }
1214
1215         while (len > 0) {
1216                 int i;
1217
1218                 if (!flash_addr_valid(addr)) {
1219                         diag_printf("Too many bad blocks in flash region 0x%08llx..0x%08llx\n",
1220                                                 (u64)flash_region_start, (u64)flash_region_end);
1221                         return FLASH_ERR_INVALID;
1222                 }
1223                 if (chk_bad) {
1224                         int blk = OFFSET_TO_BLOCK(addr);
1225
1226                         if (nfc_is_badblock(blk, g_bbt)) {
1227                                 diag_printf("Skipping bad block %u at addr 0x%08llx\n", blk, (u64)addr);
1228                                 addr += NF_BLK_SZ;
1229                                 g_block_offset++;
1230                                 continue;
1231                         }
1232                         chk_bad = 0;
1233                 }
1234
1235                 pg_no = addr / NF_PG_SZ;
1236                 if (offset != 0) {
1237                         /* Find which interleaved NAND device */
1238                         start_point = offset / (NF_PG_SZ / num_of_nand_chips);
1239                 } else {
1240                         start_point = 0;
1241                 }
1242                 for (i = start_point; i < num_of_nand_chips; i++) {
1243                         int chunk_size = (NF_PG_SZ - offset) / num_of_nand_chips;
1244
1245                         if (chunk_size > len)
1246                                 chunk_size = len;
1247                         nfc_printf(NFC_DEBUG_MED, "Reading page %d addr 0x%08llx chip %d len 0x%03x\n",
1248                                            pg_no, (u64)addr, i, chunk_size);
1249                         if (nfc_read_page(i, pg_no, 0) != 0) {
1250                                 diag_printf("** Error: Failed to read flash block %u at addr 0x%08llx\n",
1251                                                         OFFSET_TO_BLOCK(addr), (u64)addr);
1252                                 return FLASH_ERR_INVALID;
1253                         }
1254                         // now do the copying
1255                         nfc_buf_read(buf, NAND_MAIN_BUF0 + offset, chunk_size);
1256
1257                         buf += chunk_size;
1258                         len -= chunk_size;
1259                         addr += NF_PG_SZ / num_of_nand_chips - offset;
1260                         offset = 0;
1261                 }
1262                 chk_bad = (addr % NF_BLK_SZ) == 0;
1263         }
1264
1265         return FLASH_ERR_OK;
1266 }
1267
1268 /*
1269  * Support only either program for main area only. Or spare-area only for 512B.
1270  * If one wants to write to the spare-area, then before calling this function,
1271  * the spare area NFC RAM buffer has to be setup already. This function doesn't touch
1272  * the spare area NFC RAM buffer.
1273  *
1274  * @param pg_no                 page number offset from 0
1275  * @param pg_off                byte offset within the page
1276  * @param buf                   data buffer in the RAM to be written to NAND flash
1277  * @param ecc_force             can force ecc to be off. Otherwise, by default it is on
1278  *                                              unless the page offset is non-zero
1279  *
1280  * @return      0 if successful; non-zero otherwise
1281  */
1282 // SP-only opearation is not supported anymore !!!
1283 static int nfc_write_pg_random(u32 pg_no, u32 pg_off, u8 *buf, u32 ecc_force)
1284 {
1285         u16 flash_status;
1286         u32 ecc = NFC_FLASH_CONFIG2_ECC_EN, v, i;
1287         u32 write_count = NF_PG_SZ, start_point = 0, rba, rba_count = 0;
1288
1289         // the 2nd condition is to test for unaligned page address -- ecc has to be off.
1290         if (ecc_force == ECC_FORCE_OFF || pg_off != 0) {
1291                 ecc = 0;
1292         }
1293
1294         diag_printf1("%s(0x%x, 0x%x, %d)\n", __FUNCTION__, pg_no, pg_off, ecc_force);
1295
1296         switch (g_nfc_version & 0xf0) {
1297         case MXC_NFC_V3:
1298                 /* Check if Page size is greater than NFC buffer */
1299                 do {
1300                         if (write_count <= NFC_BUFSIZE) {
1301                                 // No need to worry about the spare area
1302                                 nfc_buf_write(NAND_MAIN_BUF0, buf, write_count);
1303                                 write_count = 0;
1304                         } else {
1305                                 // No need to worry about the spare area
1306                                 nfc_buf_write(NAND_MAIN_BUF0, buf, NFC_BUFSIZE);
1307                                 write_count -= NFC_BUFSIZE;
1308                                 buf += NFC_BUFSIZE;
1309                         }
1310                         // combine the two commands for program
1311                         writel((FLASH_Program << 8) | FLASH_Send_Data, NAND_CMD_REG);
1312
1313                         for (i = start_point; i < num_of_nand_chips; i++) {
1314                                 rba = rba_count * ((NF_PG_SZ / num_of_nand_chips) / 512);
1315                                 /* Completely wrote out the NFC buffer, break and copy more to the NFC buffer */
1316                                 if (rba > 7) {
1317                                         rba_count = 0;
1318                                         break;
1319                                 }
1320
1321                                 // For ECC
1322                                 v = readl(NFC_FLASH_CONFIG2_REG) & ~NFC_FLASH_CONFIG2_ECC_EN;
1323                                 // setup config2 register for ECC enable or not
1324                                 write_nfc_ip_reg(v | ecc, NFC_FLASH_CONFIG2_REG);
1325
1326                                 start_nfc_addr_ops(FLASH_Program, pg_no, pg_off, 0, i, num_of_nand_chips);
1327
1328                                 // start auto-program
1329                                 writel(NAND_LAUNCH_AUTO_PROG, NAND_LAUNCH_REG);
1330                                 if (i < (num_of_nand_chips - i))
1331                                         wait_for_auto_prog_done();
1332                                 else
1333                                         wait_op_done();
1334                                 pg_off = 0;
1335                                 rba_count++;
1336                         }
1337                         start_point = i;
1338                 } while (write_count > 0);
1339                 flash_status = NFC_STATUS_READ();
1340                 // check I/O bit 0 to see if it is 0 for success
1341                 if ((flash_status & ((0x1 << num_of_nand_chips) - 1)) != 0) {
1342                         return -1;
1343                 }
1344                 break;
1345         default:
1346                 if (g_nfc_version != MXC_NFC_V1) {
1347                         int i;
1348
1349                         for (i = 1; i < NFC_SPARE_BUF_SZ / 16; i++) {
1350                                 memcpy((void *)(NAND_SPAR_BUF0 + i * NFC_SPARE_BUF_SZ),
1351                                            (void *)(NAND_SPAR_BUF0 + i * 16), 16);
1352                         }
1353                 }
1354                 nfc_buf_write(NAND_MAIN_BUF0, buf, NF_PG_SZ);
1355 #ifdef BARKER_CODE_SWAP_LOC
1356                 // To replace the data at offset MXC_NAND_BOOT_LOAD_BARKER with
1357                 // the address of the NFC base. This is needed for certain platforms.
1358                 if (pg_no == 0) {
1359                         diag_printf("\n[INFO]: copy data at 0x%x to spare area and set it to 0x%x\n",
1360                                                 BARKER_CODE_SWAP_LOC, BARKER_CODE_VAL);
1361                         writel(readl(NFC_BASE + BARKER_CODE_SWAP_LOC), NAND_SPAR_BUF0);
1362                         // todo: set BARKER_CODE_VAL and BARKER_CODE_SWAP_LOC for skye, etc.
1363                         writel(BARKER_CODE_VAL, NFC_BASE + BARKER_CODE_SWAP_LOC);
1364                 }
1365 #endif
1366                 NFC_CMD_INPUT(FLASH_Send_Data);
1367                 start_nfc_addr_ops(FLASH_Program, pg_no, pg_off, 0, 0, num_of_nand_chips);
1368
1369                 NFC_DATA_INPUT(RAM_BUF_0, NFC_MAIN_ONLY, ecc);
1370                 if (g_is_4k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
1371                         diag_printf("4K page with multi cycle write is not supported\n");
1372                         return -1;
1373                 }
1374                 if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
1375                         NFC_DATA_INPUT_2k(RAM_BUF_1);
1376                         NFC_DATA_INPUT_2k(RAM_BUF_2);
1377                         NFC_DATA_INPUT_2k(RAM_BUF_3);
1378                 }
1379                 NFC_CMD_INPUT(FLASH_Program);
1380
1381                 flash_status = NFC_STATUS_READ();
1382                 // check I/O bit 0 to see if it is 0 for success
1383                 if ((flash_status & 0x1) != 0) {
1384                         diag_printf("** Error: failed to program page %u at 0x%08x status=0x%02x\n",
1385                                                 pg_no, pg_no * NF_PG_SZ + pg_off, flash_status);
1386                         return -1;
1387                 }
1388         }
1389         return 0;
1390 }
1391
1392 #ifndef NFC_V3_0
1393 // for version V1 and V2 of NFC
1394 static int nfc_read_pg_random(u32 pg_no, u32 pg_off, u32 ecc_force, u32 cs_line,
1395                                                           u32 num_of_nand_chips)
1396 {
1397         u32 t1, ecc = 1;
1398         u8 t2 = 0, t3 = 0, t4 = 0, t5 = 0, t6 = 0, t7 = 0, t8 = 0;
1399         int res = 0;
1400
1401         nfc_printf(NFC_DEBUG_MAX, "%s: reading page %u offset 0x%03x (addr 0x%08llx)\n",
1402                            __FUNCTION__, pg_no, pg_off, (flash_addr_t)pg_no * NF_PG_SZ + pg_off);
1403
1404         if (ecc_force == ECC_FORCE_OFF || pg_off != 0 )
1405                 ecc = 0;
1406
1407         NFC_CMD_INPUT(FLASH_Read_Mode1);
1408         start_nfc_addr_ops(FLASH_Read_Mode1, pg_no, pg_off, 0, 0, num_of_nand_chips);
1409
1410         if (g_is_2k_page || g_is_4k_page) {
1411                 NFC_CMD_INPUT(FLASH_Read_Mode1_LG);
1412         }
1413
1414         NFC_DATA_OUTPUT(RAM_BUF_0, FDO_PAGE_SPARE, ecc);
1415         switch (g_nfc_version & 0xf0) {
1416         case MXC_NFC_V1:
1417                 t1 = readw(ECC_STATUS_RESULT_REG);
1418                 if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
1419                         NFC_DATA_OUTPUT(RAM_BUF_1, FDO_PAGE_SPARE, ecc);
1420                         t2 = readw(ECC_STATUS_RESULT_REG);
1421                         NFC_DATA_OUTPUT(RAM_BUF_2, FDO_PAGE_SPARE, ecc);
1422                         t3 = readw(ECC_STATUS_RESULT_REG);
1423                         NFC_DATA_OUTPUT(RAM_BUF_3, FDO_PAGE_SPARE, ecc);
1424                         t4 = readw(ECC_STATUS_RESULT_REG);
1425                 }
1426
1427                 if (ecc && ((t1 & 0xA) != 0x0 || (t2 & 0xA) != 0x0 ||
1428                                         (t3 & 0xA) != 0x0 || (t4 & 0xA) != 0x0)) {
1429                         diag_printf("\n** Error: ECC error page %u, col %u: ECC status=0x%x:0x%x:0x%x:0x%x\n",
1430                                                 pg_no, pg_off, t1, t2, t3, t4);
1431                         res = -1;
1432                         goto out;
1433                 }
1434                 break;
1435         case MXC_NFC_V2:
1436                 if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
1437                         NFC_DATA_OUTPUT(RAM_BUF_1, FDO_PAGE_SPARE, ecc);
1438                         NFC_DATA_OUTPUT(RAM_BUF_2, FDO_PAGE_SPARE, ecc);
1439                         NFC_DATA_OUTPUT(RAM_BUF_3, FDO_PAGE_SPARE, ecc);
1440                 }
1441                 if (ecc) {
1442                         t1 = readl(ECC_STATUS_RESULT_REG);
1443                         if (g_is_2k_page || g_is_4k_page) {
1444                                 t2 = (t1 >> 4) & 0xF;
1445                                 t3 = (t1 >> 8) & 0xF;
1446                                 t4 = (t1 >> 12) & 0xF;
1447                                 if (g_is_4k_page) {
1448                                         t5 = (t1 >> 16) & 0xF;
1449                                         t6 = (t1 >> 20) & 0xF;
1450                                         t7 = (t1 >> 24) & 0xF;
1451                                         t8 = (t1 >> 28) & 0xF;
1452                                 }
1453                         }
1454                         if ((t1 = (t1 & 0xF)) > 4 || t2 > 4 || t3 > 4 || t4 > 4 ||
1455                                 t5 > 4 || t6 > 4 || t7 > 4 || t8 > 4) {
1456                                 diag_printf("\n** Error: ECC error reading block %u page %u\n",
1457                                                         pg_no / NF_PG_PER_BLK, pg_no % NF_PG_PER_BLK);
1458                                 diag_printf("   ECC status=%x:%x:%x:%x:%x:%x:%x:%x\n",
1459                                                         t1, t2, t3, t4, t5, t6, t7, t8);
1460                                 res = -1;
1461                                 goto out;
1462                         }
1463                 }
1464                 break;
1465         default:
1466                 diag_printf("Unknown NFC version: %d\n", g_nfc_version);
1467                 return -1;
1468         }
1469         if (g_nfc_version != MXC_NFC_V1) {
1470                 int i;
1471
1472                 for (i = 1; i < NFC_SPARE_BUF_SZ / 16; i++) {
1473                         memcpy((void *)(NAND_SPAR_BUF0 + i * 16),
1474                                    (void *)(NAND_SPAR_BUF0 + i * NFC_SPARE_BUF_SZ), 16);
1475                 }
1476         }
1477 #ifdef BARKER_CODE_SWAP_LOC
1478         // To replace the data at offset BARKER_CODE_SWAP_LOC with the address of the NFC base
1479         // This is needed for certain platforms
1480         if (pg_no == 0) {
1481                 diag_printf("\n[INFO]: copy back data from spare to 0x%x\n", BARKER_CODE_SWAP_LOC);
1482                 writel(readl(NAND_SPAR_BUF0), NFC_BASE + BARKER_CODE_SWAP_LOC);
1483         }
1484 #endif
1485
1486 out:
1487         return res;
1488 }
1489 #endif                  // ifndef NFC_V3_0
1490
1491 /*!
1492  * Read a page's both main and spare area from NAND flash to the internal RAM buffer.
1493  * It always reads data to the internal buffer 0.
1494  *
1495  * @param cs_line       which NAND device is used
1496  * @param pg_no    page number of the device
1497  * @param pg_off        offset within a page
1498  *
1499  * @return                              0 if no error or 1-bit error; -1 otherwise
1500  */
1501 static int nfc_read_page(u32 cs_line, u32 pg_no, u32 pg_off)
1502 {
1503         return nfc_read_pg_random(pg_no, pg_off, ECC_FORCE_ON, cs_line, num_of_nand_chips);
1504 }
1505
1506 static int nfc_write_page(u32 pg_no, u32 pg_off, u32 ecc_force)
1507 {
1508         u16 flash_status;
1509         u32 ecc = NFC_FLASH_CONFIG2_ECC_EN;
1510
1511         diag_printf1("Writing page %u addr 0x%08llx\n",
1512                                  pg_no, (u64)pg_no * NF_PG_SZ + pg_off);
1513         if (ecc_force == ECC_FORCE_OFF || pg_off != 0) {
1514                 ecc = 0;
1515         }
1516
1517         if (g_nfc_version == MXC_NFC_V3) {
1518                 int i;
1519                 u32 v;
1520                 u32 start_point = 0, rba, rba_count = 0;
1521
1522                 // combine the two commands for program
1523                 writel((FLASH_Program << 8) | FLASH_Send_Data, NAND_CMD_REG);
1524
1525                 for (i = start_point; i < num_of_nand_chips; i++) {
1526                         rba = rba_count * ((NF_PG_SZ / num_of_nand_chips) / 512);
1527                         /* Completely wrote out the NFC buffer, break and copy more to the NFC buffer */
1528                         if (rba > 7) {
1529                                 rba_count = 0;
1530                                 break;
1531                         }
1532
1533                         // For ECC
1534                         v = readl(NFC_FLASH_CONFIG2_REG) & ~NFC_FLASH_CONFIG2_ECC_EN;
1535                         // setup config2 register for ECC enable or not
1536                         write_nfc_ip_reg(v | ecc, NFC_FLASH_CONFIG2_REG);
1537
1538                         start_nfc_addr_ops(FLASH_Program, pg_no, pg_off, 0, i, num_of_nand_chips);
1539
1540                         // start auto-program
1541                         writel(NAND_LAUNCH_AUTO_PROG, NAND_LAUNCH_REG);
1542                         if (i < (num_of_nand_chips - i))
1543                                 wait_for_auto_prog_done();
1544                         else
1545                                 wait_op_done();
1546                         pg_off = 0;
1547                         rba_count++;
1548                 }
1549                 start_point = i;
1550                 flash_status = NFC_STATUS_READ();
1551         } else {
1552                 if (g_nfc_version != MXC_NFC_V1) {
1553                         int i;
1554
1555                         for (i = NFC_SPARE_BUF_SZ / 16 - 1; i >= 0; i--) {
1556                                 memcpy((void *)(NAND_SPAR_BUF0 + i * NFC_SPARE_BUF_SZ),
1557                                            (void *)(NAND_SPAR_BUF0 + i * 16), 16);
1558                         }
1559                 }
1560                 NFC_CMD_INPUT(FLASH_Send_Data);
1561                 start_nfc_addr_ops(FLASH_Program, pg_no, pg_off, 0, 0, num_of_nand_chips);
1562
1563                 NFC_DATA_INPUT(RAM_BUF_0, NFC_MAIN_ONLY, ecc);
1564                 if (g_is_4k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
1565                         diag_printf("4K page with multi cycle write is not supported\n");
1566                         return -1;
1567                 }
1568                 if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
1569                         NFC_DATA_INPUT_2k(RAM_BUF_1);
1570                         NFC_DATA_INPUT_2k(RAM_BUF_2);
1571                         NFC_DATA_INPUT_2k(RAM_BUF_3);
1572                 }
1573                 NFC_CMD_INPUT(FLASH_Program);
1574
1575                 flash_status = NFC_STATUS_READ();
1576         }
1577         if ((flash_status & 0x1) != 0) {
1578                 diag_printf("** Error: failed to program page %u at addr 0x%08llx\n",
1579                                         pg_no, (u64)pg_no * NF_PG_SZ + pg_off);
1580                 return -1;
1581         }
1582         return 0;
1583 }
1584
1585 // Read data into buffer
1586 #ifndef MXCFLASH_SELECT_MULTI
1587 int flash_read_buf(void *addr, void *data, int len)
1588 #else
1589 int nandflash_read_buf(void *addr, void *data, int len)
1590 #endif
1591 {
1592         flash_addr_t flash_addr = (unsigned long)addr;
1593         return nfc_read_region(flash_addr, data, len);
1594 }
1595
1596 void mxc_nfc_print_info(void)
1597 {
1598         diag_printf("[0x%08x bytes]: %u blocks of %u pages of %u bytes each.\n",
1599                                 NF_DEV_SZ, NF_BLK_CNT,
1600                                 NF_PG_PER_BLK, NF_PG_SZ);
1601 }
1602
1603 static int mxc_nfc_isbad_bbt(u16 *bbt, int block)
1604 {
1605         cyg_uint8 res;
1606
1607         block <<= 1;
1608         res = (get_byte(bbt, block >> 3) >> (block & 0x06)) & 0x03;
1609         res ^= 0x03;
1610         return res;
1611 }
1612
1613 static int mxc_nfc_search_bbt(struct nand_bbt_descr *td)
1614 {
1615         int i;
1616
1617         td->pages = -1;
1618         for (i = 0; i < NF_BBT_MAX_NR; i++) {
1619                 u32 blk = NF_BLK_CNT - i - 1;
1620                 flash_addr_t addr = blk * NF_BLK_SZ;
1621
1622                 if (nfc_read_pg_random(addr / NF_PG_SZ, addr % NF_PG_SZ,
1623                                                            ECC_FORCE_ON, 0, num_of_nand_chips) != 0) {
1624                         diag_printf("Failed to read bbt page %u at 0x%08llx\n",
1625                                                 (u32)(addr / NF_PG_SZ), addr);
1626                         continue;
1627                 }
1628                 if (check_short_pattern((void *)NAND_SPAR_BUF0, td) == 0) {
1629                         diag_printf1("found BBT at block %u addr %08llx\n", blk, (u64)addr);
1630                         td->pages = blk * NF_PG_PER_BLK;
1631                         td->version = get_byte((void *)NAND_SPAR_BUF0, td->veroffs);
1632                         mark_blk_bad(blk, g_bbt, BLK_RESERVED);
1633                         diag_printf1("Found version %d BBT at block %d (0x%08llx)\n",
1634                                                  td->version, td->pages / NF_PG_PER_BLK,
1635                                                  (u64)td->pages * NF_PG_SZ);
1636                         return 0;
1637                 }
1638         }
1639         return 1;
1640 }
1641
1642 /*
1643  * Look for the BBT depending on the passed-in lowlevel value.
1644  * @param       lowlevel        If true, then it does a low level scan based on factory
1645  *                                              marked BI(block info) field with ECC off to decide if a
1646  *                                              block is bad.
1647  *                                              If false, then it checks to see if an existing BBT in the
1648  *                                              flash or not. If not, then it returns -1. If yes, it will
1649  *                                              prints out the number of bad blocks.
1650  *
1651  * @return      number of bad blocks for the whole nand flash
1652  *
1653  * Note: For a brand new flash, this function has to be called with
1654  *               lowlevel=true.
1655  *
1656  *
1657  */
1658 static int mxc_nfc_scan(bool lowlevel)
1659 {
1660         u32 bad = 0, i;
1661         u32 count1 = 0, count2 = 0;
1662         u8 *buf = NULL;
1663         struct nand_bbt_descr *td = g_mxc_nfc_bbt_main_descr;
1664         struct nand_bbt_descr *md = g_mxc_nfc_bbt_mirror_descr;
1665
1666         nfc_printf(NFC_DEBUG_MAX, "%s()\n", __FUNCTION__);
1667         mxc_nfc_scan_done = 0;
1668
1669         if (g_nfc_debug_measure) {
1670                 count1 = hal_timer_count();
1671         }
1672         // read out the last 4 blocks for marker
1673         // need to keep where is the td and md block number
1674         if (!lowlevel) {
1675                 struct nand_bbt_descr *bd;
1676
1677                 diag_printf1("Searching for BBT in the flash ...\n");
1678                 if (mxc_nfc_search_bbt(td) != 0) {
1679                         diag_printf("No main BBT found in flash\n");
1680                 }
1681                 if (md && mxc_nfc_search_bbt(md) != 0) {
1682                         diag_printf("No mirror BBT found in flash\n");
1683                 }
1684                 if (td->pages == -1 && (!md || md->pages == -1)) {
1685                         diag_printf("No BBT found. Need to do \"nand scan\" first\n");
1686                         return -1;
1687                 }
1688                 if (td->pages >= 0 && (md == NULL || md->version <= td->version)) {
1689                         bd = td;
1690                         nfc_printf(NFC_DEBUG_MIN, "Using normal bbt at page %d\n", bd->pages);
1691                 } else if (md != NULL && md->pages >= 0) {
1692                         bd = md;
1693                         nfc_printf(NFC_DEBUG_MIN, "Using mirror bbt at page %d\n", bd->pages);
1694                 } else {
1695                         diag_printf("** Error: Failed to read bbt from flash\n");
1696                         return -1;
1697                 }
1698                 nfc_read_page(0, bd->pages, 0);
1699                 for (i = 0; i < NF_BLK_CNT; i++) {
1700                         int res = mxc_nfc_isbad_bbt((u16 *)NAND_MAIN_BUF0, i);
1701                         if (res) {
1702                                 // construct the bad block table
1703                                 mark_blk_bad(i, g_bbt, res);
1704                                 bad++;
1705                         }
1706                 }
1707                 buf = g_bbt;
1708         } else {
1709                 diag_printf("Doing low level scan to construct BBT\n");
1710                 for (i = 0; i < NF_BLK_CNT; i++) {
1711                         int res = nfc_is_badblock(i, buf);
1712                         if (res) {
1713                                 // construct the bad block table
1714                                 if (!buf)
1715                                         mark_blk_bad(i, g_bbt, res);
1716                                 bad++;
1717                         }
1718                 }
1719         }
1720         diag_printf1("Total bad blocks: %d\n", bad);
1721         if (g_nfc_debug_measure) {
1722                 count2 = hal_timer_count();
1723                 diag_printf("counter1=0x%x, counter2=0x%x, diff=0x%x (%u usec)\n",
1724                                         count1, count2, count2 - count1,
1725                                         (count2 - count1) * 1000000 / 32768);
1726         }
1727         mxc_nfc_scan_done = 1;
1728         return bad;
1729 }
1730
1731 ////////////////////////// "nand" commands support /////////////////////////
1732 // Image management functions
1733 local_cmd_entry("info",
1734                                 "Show nand flash info (number of good/bad blocks)",
1735                                 "",
1736                                 nand_info,
1737                                 NAND_cmds
1738                    );
1739
1740 local_cmd_entry("show",
1741                                 "Show a page main/spare areas or spare area only (-s)",
1742                                 "-f <raw page address> | -b <block> [-s]",
1743                                 nand_show,
1744                                 NAND_cmds
1745                    );
1746
1747 local_cmd_entry("read",
1748                                 "Read data from nand flash into RAM",
1749                                 "-f <raw addr> -b <mem_load_addr> -l <byte len> [-c <col>]\n"
1750                                 "      Note -c is only for 2K-page for value <0, 2048+64-1>",
1751                                 nand_read,
1752                                 NAND_cmds
1753                    );
1754
1755 local_cmd_entry("write",
1756                                 "Write data from RAM into nand flash",
1757                                 "-f <raw address> -b <memory_address> -l <image_length> [-c <col_addr>]",
1758                                 nand_write,
1759                                 NAND_cmds
1760                    );
1761
1762 local_cmd_entry("erase",
1763                                 "Erase nand flash contents",
1764                                 "-f <raw address> -l <length> [-o]\n"
1765                                 "             -o: force erase (even for bad blocks)",
1766                                 nand_erase,
1767                                 NAND_cmds
1768                    );
1769
1770 local_cmd_entry("scan",
1771                                 "Scan bad blocks and may also save bad block table into the NAND flash.",
1772                                 "[-o] [-r]\n"
1773                                 "No argument: save existing bad block table (BBT)\n"
1774                                 "            -r: re-scan with ECC off and save BBT -- for brand NEW flash\n"
1775                                 "            -o: force erase all, reconstruct BBT (no ECC) and save BBT -- for development.",
1776                                 nand_scan,
1777                                 NAND_cmds
1778                    );
1779
1780 local_cmd_entry("debug",
1781                                 "Various NAND debug features ",
1782                                 "<0> no debug messages <default>\n"
1783                                 "             <1> min debug messages\n"
1784                                 "             <2> med debug messages\n"
1785                                 "             <3> max debug messages\n"
1786                                 "             <4> enable(default)/disable h/w ECC for both r/w\n"
1787                                 "             <5> disable(default)/enalbe spare-only read\n"
1788                                 "             <9> enable/disable measurement\n"
1789                                 "             no parameter - display current debug setup",
1790                                 nand_debug_fun,
1791                                 NAND_cmds
1792                                 );
1793
1794 local_cmd_entry("bad",
1795                                 "Mark bad block in BBT",
1796                                 "[-f <raw address>] [-b <block number>] [-c]\n"
1797                                 "           -c: clear bad block mark\n"
1798                                 "           -f and -b are mutually exclusive",
1799                                 nand_bad,
1800                                 NAND_cmds
1801                                 );
1802
1803 // Define table boundaries
1804 CYG_HAL_TABLE_BEGIN( __NAND_cmds_TAB__, NAND_cmds);
1805 CYG_HAL_TABLE_END( __NAND_cmds_TAB_END__, NAND_cmds);
1806
1807 extern struct cmd __NAND_cmds_TAB__[], __NAND_cmds_TAB_END__;
1808
1809 // CLI function
1810 static cmd_fun do_nand_cmds;
1811 RedBoot_nested_cmd("nand",
1812                    "Utility function to NAND flash using raw address",
1813                    "{cmds}",
1814                    do_nand_cmds,
1815                    __NAND_cmds_TAB__, &__NAND_cmds_TAB_END__
1816                   );
1817
1818 static void nand_usage(char *why)
1819 {
1820         diag_printf("*** invalid 'nand' command: %s\n", why);
1821         cmd_usage(__NAND_cmds_TAB__, &__NAND_cmds_TAB_END__, "nand ");
1822 }
1823
1824 static u32 curr_addr;
1825 static void nand_show(int argc, char *argv[])
1826 {
1827         u32 ra, block;
1828         bool flash_addr_set = false;
1829         bool block_set = false;
1830         bool spar_only = false;
1831         struct option_info opts[3];
1832
1833         init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
1834                           &ra, &flash_addr_set, "NAND FLASH memory byte address");
1835         init_opts(&opts[1], 'b', true, OPTION_ARG_TYPE_NUM,
1836                           &block, &block_set, "NAND FLASH memory block number");
1837         init_opts(&opts[2], 's', false, OPTION_ARG_TYPE_FLG,
1838                           &spar_only, NULL, "Spare only");
1839
1840         if (!scan_opts(argc, argv, 2, opts, NUM_ELEMS(opts), NULL, 0, NULL)) {
1841                 return;
1842         }
1843         if (flash_addr_set && block_set) {
1844                 nand_usage("options -f and -b are mutually exclusive");
1845                 return;
1846         } else if (flash_addr_set) {
1847                 curr_addr = ra;
1848         } else if (block_set) {
1849                 ra = BLOCK_TO_OFFSET(block) + (unsigned long)flash_info.start;
1850                 curr_addr = ra;
1851         } else {
1852                 ra = curr_addr;
1853                 curr_addr += NF_PG_SZ;
1854         }
1855
1856         if (ra % NF_PG_SZ) {
1857                 diag_printf("** Error: flash address must be page aligned\n");
1858                 return;
1859         }
1860
1861         ra &= MXC_NAND_ADDR_MASK;
1862         if (nfc_is_badblock(OFFSET_TO_BLOCK(ra), g_bbt)) {
1863                 diag_printf("This is a bad block\n");
1864         }
1865
1866         print_page(ra, spar_only);
1867 }
1868
1869 /*!
1870  * For low level nand read command. It doesn't check for bad block or not
1871  */
1872 static void nand_read(int argc, char *argv[])
1873 {
1874         int len;
1875         u32 mem_addr, ra, col, i, pg_no, pg_off;
1876         bool mem_addr_set = false;
1877         bool flash_addr_set = false;
1878         bool length_set = false;
1879         bool col_set = false;
1880         struct option_info opts[4];
1881         int j = 0;
1882         bool ecc_status = g_ecc_enable;
1883
1884         init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
1885                           &mem_addr, &mem_addr_set, "memory base address");
1886         init_opts(&opts[1], 'f', true, OPTION_ARG_TYPE_NUM,
1887                           &ra, &flash_addr_set, "FLASH memory base address");
1888         init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM,
1889                           &len, &length_set, "image length [in FLASH]");
1890         init_opts(&opts[3], 'c', true, OPTION_ARG_TYPE_NUM,
1891                           &col, &col_set, "column addr");
1892
1893         if (!scan_opts(argc, argv, 2, opts, NUM_ELEMS(opts), NULL, 0, NULL)) {
1894                 nand_usage("invalid arguments");
1895                 return;
1896         }
1897
1898         if (ra % NF_PG_SZ) {
1899                 diag_printf("** Error: flash address must be page aligned\n");
1900                 return;
1901         }
1902
1903         if (!mem_addr_set || !flash_addr_set || !length_set) {
1904                 nand_usage("** Error: required parameter missing");
1905                 return;
1906         }
1907         if ((mem_addr < (CYG_ADDRESS)ram_start) ||
1908                 ((mem_addr+len) >= (CYG_ADDRESS)ram_end)) {
1909                 diag_printf("** WARNING: RAM address: 0x%08x may be invalid\n", mem_addr);
1910                 diag_printf("   valid range is 0x%p-0x%p\n", ram_start, ram_end);
1911         }
1912
1913         if (col_set) {
1914                 diag_printf("Random read at page %u, column 0x%04x\n",
1915                                         ra / NF_PG_SZ, col);
1916
1917                 if (g_is_2k_page || g_is_4k_page) {
1918                         g_ecc_enable = false;
1919                 }
1920                 nfc_read_pg_random(ra / NF_PG_SZ, col, ECC_FORCE_OFF, 0, num_of_nand_chips);
1921                 if (g_is_2k_page || g_is_4k_page) {
1922                         g_ecc_enable = ecc_status;
1923                 }
1924                 nfc_buf_read((void *)mem_addr, NAND_MAIN_BUF0, NF_PG_SZ);
1925                 return;
1926         }
1927
1928         // ensure integer multiple of page size
1929         len = (len + NF_PG_SZ - 1) & ~(NF_PG_SZ - 1);
1930         ra &= MXC_NAND_ADDR_MASK;
1931         do {
1932                 if (OFFSET_TO_BLOCK(ra) > (NF_BLK_CNT - 1)) {
1933                         diag_printf("\n** Error: flash address: 0x%08x out of range\n", ra);
1934                         return;
1935                 }
1936                 if (nfc_is_badblock(OFFSET_TO_BLOCK(ra), g_bbt)) {
1937                         diag_printf("\nSkipping bad block %u at addr=0x%08llx\n",
1938                                                 OFFSET_TO_BLOCK(ra), (u64)ra);
1939                         ra = (OFFSET_TO_BLOCK(ra) + 1) *  NF_BLK_SZ;
1940                         continue;
1941                 }
1942                 pg_no = ra / NF_PG_SZ;
1943                 pg_off = ra % NF_PG_SZ;
1944                 for (i = 0; i < num_of_nand_chips; i++) {
1945                         if (nfc_read_page(i, pg_no, pg_off) != 0) {
1946                                 diag_printf("\n** Error: uncorrectable ECC at addr 0x%08x\n", ra);
1947                                 diag_printf("use 'nand bad -b %u' to mark this block in BBT\n",
1948                                                         pg_no / NF_PG_PER_BLK);
1949                         }
1950                         if ((j++ % 0x20) == 0)
1951                                 diag_printf("\n%s 0x%08x: ", __FUNCTION__, ra);
1952                         diag_printf(".");
1953
1954                         nfc_buf_read((void *)mem_addr, NAND_MAIN_BUF0, NF_PG_SZ / num_of_nand_chips);
1955
1956                         ra += NF_PG_SZ / num_of_nand_chips;
1957                         mem_addr += NF_PG_SZ / num_of_nand_chips;
1958                         len -= NF_PG_SZ / num_of_nand_chips;
1959                         pg_off = 0;
1960                 }
1961         } while (len > 0);
1962         diag_printf("\n");
1963 }
1964
1965 static void nand_write(int argc, char *argv[])
1966 {
1967         int len, len_st, j = 0;
1968         u32 mem_addr, mem_addr_st, ra, col;
1969         bool mem_addr_set = false;
1970         bool flash_addr_set = false;
1971         bool length_set = false;
1972         bool col_set = false;
1973         struct option_info opts[4];
1974         bool ecc_status = g_ecc_enable;
1975
1976         init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
1977                           &mem_addr, &mem_addr_set, "memory base address");
1978         init_opts(&opts[1], 'f', true, OPTION_ARG_TYPE_NUM,
1979                           &ra, &flash_addr_set, "FLASH memory base address");
1980         init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM,
1981                           &len, &length_set, "image length [in FLASH]");
1982         init_opts(&opts[3], 'c', true, OPTION_ARG_TYPE_NUM,
1983                           &col, &col_set, "column addr");
1984         if (!scan_opts(argc, argv, 2, opts, NUM_ELEMS(opts), NULL, 0, NULL)) {
1985                 nand_usage("invalid arguments");
1986                 return;
1987         }
1988
1989         if (!mem_addr_set || !flash_addr_set || !length_set) {
1990                 nand_usage("required parameter missing");
1991                 return;
1992         }
1993
1994         if ((mem_addr < (CYG_ADDRESS)ram_start) ||
1995                 ((mem_addr + len) >= (CYG_ADDRESS)ram_end)) {
1996                 diag_printf("** WARNING: RAM address range: %p..%p may be invalid\n",
1997                                         (void *)mem_addr, (void *)(mem_addr + len));
1998                 diag_printf("   valid range is %p-%p\n", (void *)ram_start, (void *)ram_end);
1999         }
2000
2001         if (col_set) {
2002                 diag_printf("Random write at page %u, column %u\n", ra / NF_PG_SZ, col);
2003
2004                 if (g_is_2k_page || g_is_4k_page) {
2005                         g_ecc_enable = false;
2006                 }
2007                 nfc_write_pg_random(ra / NF_PG_SZ, col, (u8 *)mem_addr, 0);
2008                 if (g_is_2k_page || g_is_4k_page) {
2009                         g_ecc_enable = ecc_status;
2010                 }
2011                 return;
2012         }
2013
2014         if ((ra % NF_PG_SZ) != 0) {
2015                 diag_printf("** Error: flash address must be page aligned\n");
2016                 return;
2017         }
2018
2019         mem_addr_st = mem_addr;
2020         len_st = len;
2021         ra &= MXC_NAND_ADDR_MASK;
2022
2023         mxc_nfc_buf_clear(NAND_SPAR_BUF0, 0xff, NF_SPARE_SZ);
2024         do {
2025                 if (OFFSET_TO_BLOCK(ra) > (NF_BLK_CNT - 1)) {
2026                         diag_printf("\nFlash address 0x%08x out of range\n", ra);
2027                         return;
2028                 }
2029                 if (nfc_is_badblock(OFFSET_TO_BLOCK(ra), g_bbt)) {
2030                         diag_printf("\nSkipping bad block %u at addr=0x%08llx\n",
2031                                                 OFFSET_TO_BLOCK(ra), (u64)ra);
2032                         ra = (OFFSET_TO_BLOCK(ra) + 1) *  NF_BLK_SZ;
2033                         continue;
2034                 }
2035
2036                 if ((ra % NF_BLK_SZ) == 0) {
2037                          mem_addr_st = mem_addr;
2038                          len_st = len;
2039                 }
2040                 if (nfc_write_pg_random(ra / NF_PG_SZ, ra % NF_PG_SZ, (u8 *)mem_addr, 0) != 0) {
2041                         if (g_nfc_debug_level >= NFC_DEBUG_DEF) {
2042                                 diag_printf("\nWarning %d: program error at addr 0x%x\n", __LINE__, ra);
2043                         }
2044                         mark_blk_bad(OFFSET_TO_BLOCK(ra), g_bbt, BLK_BAD_RUNTIME);
2045                         ra = (OFFSET_TO_BLOCK(ra) + 1) *  NF_BLK_SZ; //make sure block size aligned
2046                         mem_addr = mem_addr_st; // rewind to block boundary
2047                         len = len_st;
2048                         continue;
2049                 }
2050                 if ((j++ % 0x20) == 0)
2051                         diag_printf("\nProgramming 0x%08x: ", ra);
2052                 diag_printf(".");
2053
2054                 len -= NF_PG_SZ;
2055                 ra += NF_PG_SZ;
2056                 mem_addr += NF_PG_SZ;
2057         } while (len > 0);
2058         diag_printf("\n");
2059 }
2060
2061 void nand_debug_fun(int argc, char *argv[])
2062 {
2063         int opt;
2064         const char *dbg_lvl_str;
2065
2066         if (argc == 3) {
2067                 opt = argv[2][0] - '0';
2068                 switch (opt) {
2069                 case 0:
2070                         g_nfc_debug_level = NFC_DEBUG_NONE;
2071                         break;
2072                 case 1:
2073                         g_nfc_debug_level = NFC_DEBUG_MIN;
2074                         break;
2075                 case 2:
2076                         g_nfc_debug_level = NFC_DEBUG_MED;
2077                         break;
2078                 case 3:
2079                         g_nfc_debug_level = NFC_DEBUG_MAX;
2080                         break;
2081                 case 4:
2082                         g_ecc_enable = g_ecc_enable? false: true;
2083                         break;
2084                 case 5:
2085                         // toggle g_spare_only_read_ok
2086                         g_spare_only_read_ok = g_spare_only_read_ok? false: true;
2087                         break;
2088                 case 9:
2089                         g_nfc_debug_measure = g_nfc_debug_measure? false: true;
2090                         break;
2091
2092                 default:
2093                         diag_printf("%s(%s) not supported\n", __FUNCTION__, argv[2]);
2094                 }
2095         }
2096         switch (g_nfc_debug_level) {
2097         case NFC_DEBUG_NONE:
2098                 dbg_lvl_str = "none";
2099                 break;
2100         case NFC_DEBUG_MIN:
2101                 dbg_lvl_str = "min";
2102                 break;
2103         case NFC_DEBUG_MED:
2104                 dbg_lvl_str = "med";
2105                 break;
2106         case NFC_DEBUG_MAX:
2107                 dbg_lvl_str = "max";
2108                 break;
2109         default:
2110                 dbg_lvl_str = "invalid";
2111         }
2112         diag_printf("Current debug options are:\n");
2113         diag_printf("    h/w ECC: %s\n", g_ecc_enable ? "on" : "off");
2114         diag_printf("    sp-only read: %s\n", g_spare_only_read_ok ? "on" : "off");
2115         diag_printf("    measurement: %s\n", g_nfc_debug_measure ? "on" : "off");
2116         diag_printf("    message level: %s\n", dbg_lvl_str);
2117 }
2118
2119 static void nand_erase(int argc, char *argv[])
2120 {
2121         u32 len, ra;
2122         bool faddr_set = false;
2123         bool force_erase_set = false;
2124         bool length_set = false;
2125         struct option_info opts[4];
2126
2127         init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
2128                   &ra, &faddr_set, "FLASH memory base address");
2129         init_opts(&opts[1], 'l', true, OPTION_ARG_TYPE_NUM,
2130                   &len, &length_set, "length in bytes");
2131         init_opts(&opts[2], 'o', false, OPTION_ARG_TYPE_FLG,
2132                   &force_erase_set, &force_erase_set, "force erases block");
2133
2134         if (!scan_opts(argc, argv, 2, opts, NUM_ELEMS(opts), NULL, 0, NULL)) {
2135                 nand_usage("invalid arguments");
2136                 return;
2137         }
2138
2139         if (!faddr_set || !length_set) {
2140                 nand_usage("missing argument");
2141                 return;
2142         }
2143         if ((ra % NF_BLK_SZ) != 0) {
2144                 diag_printf("Address must be block aligned!\n");
2145                 diag_printf("Block size is 0x%x\n", NF_BLK_SZ);
2146                 return;
2147         }
2148         if ((len % NF_BLK_SZ) != 0) {
2149                 diag_printf("length must be block aligned!\n");
2150                 diag_printf("Block size is 0x%x\n", NF_BLK_SZ);
2151                 return;
2152         }
2153         if (len == 0) {
2154                 diag_printf("length must be > 0!\n");
2155                 return;
2156         }
2157
2158         if (!verify_action("About to erase 0x%08x bytes from nand offset 0x%08x", len, ra)) {
2159                 diag_printf("** Aborted\n");
2160                 return;
2161         }
2162
2163         if (force_erase_set == true) {
2164                 diag_printf("Force erase ...");
2165                 nfc_erase_region(ra, len, 0, 1);
2166                 diag_printf("\n");
2167         } else {
2168                 nfc_erase_region(ra, len, 1, 1);
2169         }
2170         diag_printf("\n");
2171 }
2172
2173 extern void romupdate(int argc, char *argv[]);
2174 static void nand_scan(int argc, char *argv[])
2175 {
2176         bool force_erase = false;
2177         bool force_rescan = false;
2178         struct option_info opts[2];
2179
2180         init_opts(&opts[0], 'o', false, OPTION_ARG_TYPE_FLG,
2181                   &force_erase, NULL, "force erases block first");
2182
2183         init_opts(&opts[1], 'r', false, OPTION_ARG_TYPE_FLG,
2184                   &force_rescan, NULL, "force low level re-scan");
2185
2186         if (!scan_opts(argc, argv, 2, opts, NUM_ELEMS(opts), NULL, 0, NULL)) {
2187                 nand_usage("invalid arguments");
2188                 return;
2189         }
2190
2191         if (!force_erase && !force_rescan && !mxc_nfc_scan_done) {
2192                 diag_printf("Need to build BBT first with \"nand scan [-o|-r]\"\n");
2193                 return;
2194         }
2195         if (force_erase) {
2196                 void *bbt = g_bbt;
2197
2198                 diag_printf("Force erase first ...\n");
2199                 g_bbt = NULL;
2200                 // do force erase, skipping bad blocks. After this call, g_bbt should be re-built
2201                 // for the whole NAND flash.
2202                 if (nfc_erase_region(0, NF_DEV_SZ, true, false) != 0) {
2203                         g_bbt = bbt;
2204                         return;
2205                 }
2206                 g_bbt = bbt;
2207                 mxc_nfc_scan_done = 0;
2208                 diag_printf("\n");
2209         }
2210         if (force_rescan) {
2211                 diag_printf("Force re-scan ...\n");
2212                 memset(g_bbt, 0, g_bbt_sz);
2213                 mxc_nfc_scan(true);
2214         }
2215         // program g_bbt into the flash
2216         diag_printf("Writing BBT to flash\n");
2217         if (program_bbt_to_flash() != 0) {
2218                 diag_printf("Error: Failed to write BBT to flash\n");
2219         }
2220         if (force_erase) {
2221                 romupdate(0, NULL);
2222         }
2223 }
2224
2225 static void nand_info(int argc, char *argv[])
2226 {
2227         u32 i, j = 0;
2228
2229         if (nand_flash_index == -1) {
2230                 diag_printf("Can't find valid NAND flash: %d\n", __LINE__);
2231                 return;
2232         }
2233
2234         diag_printf("\nType:\t\t %s\n", NF_VEND_INFO);
2235         diag_printf("Total size:\t 0x%08x bytes (%d MiB)\n", NF_DEV_SZ, NF_DEV_SZ / SZ_1M);
2236         diag_printf("Total blocks:\t 0x%x (%d)\n", NF_BLK_CNT, NF_BLK_CNT);
2237         diag_printf("Block size:\t 0x%x (%d)\n", NF_BLK_SZ, NF_BLK_SZ);
2238         diag_printf("Page size:\t 0x%x (%d)\n", NF_PG_SZ, NF_PG_SZ);
2239         diag_printf("Spare size:\t 0x%x (%d)\n", NF_SPARE_SZ, NF_SPARE_SZ);
2240         diag_printf("Pages per block: 0x%x (%d)\n", NF_PG_PER_BLK, NF_PG_PER_BLK);
2241
2242         if (mxc_nfc_scan(false) == -1) {
2243                 return;
2244         }
2245         diag_printf("\n");
2246         for (i = 0; i < NF_BLK_CNT; i++) {
2247                 int res = nfc_is_badblock(i, g_bbt);
2248                 if (res & ~BLK_RESERVED) {
2249                         diag_printf("block %d at offset 0x%08x is a %s bad block\n",
2250                                                 i, i * NF_BLK_SZ, res == BLK_BAD_FACTORY ? "factory" : "runtime");
2251                         j++;
2252                 }
2253         }
2254         diag_printf("==================================\n");
2255         diag_printf("Found %d bad block(s) out of %d\n", j, i);
2256 }
2257
2258 static void nand_bad(int argc, char *argv[])
2259 {
2260         u32 ra;
2261         u32 block;
2262         bool ra_set = false;
2263         bool block_set = false;
2264         bool clear = false;
2265         struct option_info opts[3];
2266         int bad;
2267
2268         init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
2269                           &ra, &ra_set, "FLASH memory base address");
2270         init_opts(&opts[1], 'b', true, OPTION_ARG_TYPE_NUM,
2271                           &block, &block_set, "block number");
2272         init_opts(&opts[2], 'c', false, OPTION_ARG_TYPE_FLG,
2273                           &clear, NULL, "clear bad block marker");
2274
2275         if (!scan_opts(argc, argv, 2, opts, NUM_ELEMS(opts), NULL, 0, NULL)) {
2276                 nand_usage("invalid arguments");
2277                 return;
2278         }
2279
2280         if (!ra_set && !block_set) {
2281                 nand_usage("missing argument");
2282                 return;
2283         }
2284         if (ra_set && block_set) {
2285                 nand_usage("options -f and -b are mutually exclusive");
2286                 return;
2287         } else if (ra_set) {
2288                 block = OFFSET_TO_BLOCK(ra & MXC_NAND_ADDR_MASK);
2289         } else {
2290                 ra = BLOCK_TO_OFFSET(block) + (unsigned long)flash_info.start;
2291         }
2292         if ((ra % NF_BLK_SZ) != 0) {
2293                 diag_printf("Address is not block aligned!\n");
2294                 diag_printf("Block size is 0x%08x\n", NF_BLK_SZ);
2295                 return;
2296         }
2297
2298         bad = nfc_is_badblock(block, g_bbt);
2299         if ((bad && !clear) || (!bad && clear)) {
2300                 diag_printf("block %5u at address 0x%08x is already %s\n",
2301                                         block, ra, bad ? "bad" : "good");
2302                 return;
2303         }
2304         if (clear && bad != BLK_BAD_RUNTIME) {
2305                 diag_printf("Refusing to mark a factory bad block as good!\n");
2306                 return;
2307         }
2308         if (!verify_action("Mark block %u at address 0x%08x %s in BBT",
2309                                            block, ra, clear ? "good" : "bad")) {
2310                 diag_printf("** Aborted\n");
2311                 return;
2312         }
2313
2314         nfc_printf(NFC_DEBUG_MIN, "Marking block %5u at 0x%08x %s\n",
2315                            block, ra, clear ? "good" : "bad");
2316         mark_blk_bad(block, g_bbt, clear ? 0 : BLK_BAD_RUNTIME);
2317         mxc_nfc_update_bbt(g_mxc_nfc_bbt_main_descr,
2318                                            g_mxc_nfc_bbt_mirror_descr);
2319 }
2320
2321 static void do_nand_cmds(int argc, char *argv[])
2322 {
2323         struct cmd *cmd;
2324
2325         if (!mxcnfc_init_ok) {
2326 #ifdef CYGHWR_DEVS_FLASH_MXC_MULTI
2327                 diag_printf("Warning: NAND flash hasn't been initialized. Try \"factive nand\" first\n\n");
2328 #else
2329                 diag_printf("Error: NAND flash hasn't been initialized\n");
2330 #endif
2331                 return;
2332         }
2333
2334         if (argc < 2) {
2335                 nand_usage("too few arguments");
2336                 return;
2337         }
2338
2339         if ((cmd = cmd_search(__NAND_cmds_TAB__, &__NAND_cmds_TAB_END__,
2340                                                   argv[1])) != NULL) {
2341                 cmd->fun(argc, argv);
2342                 return;
2343         }
2344         nand_usage("unrecognized command");
2345 }
2346
2347 /*!
2348  * Display a memory region by 16-bit words
2349  * @param pkt   pointer to the starting address of the memory
2350  * @param len   byte length of the buffer to be displayed
2351  */
2352 static void print_pkt_16(u16 *pkt, u32 len)
2353 {
2354         diag_printf("******************** %d bytes********************\n", len);
2355         u32 i = 0, tempLen = (len + 1) / 2;
2356
2357         while (tempLen != 0) {
2358                 if (tempLen >= 8) {
2359                         diag_printf("[%03x-%03x] ", i * 2, (i * 2) + 14);
2360                         diag_printf("%04x %04x %04x %04x %04x %04x %04x %04x\n",
2361                                                 pkt[i], pkt[i + 1], pkt[i + 2], pkt[i + 3],
2362                                                 pkt[i + 4], pkt[i + 5], pkt[i + 6], pkt[i + 7]);
2363                         tempLen -= 8;
2364                         i += 8;
2365                 } else {
2366                         if (tempLen != 0) {
2367                                 diag_printf("[%03x-%03x]", i * 2, (i + tempLen) * 2);
2368                                 while (tempLen-- != 0) {
2369                                         diag_printf(" %04x", pkt[i++]);
2370                                 }
2371                                 diag_printf("\n");
2372                         }
2373                         diag_printf("*************************************************\n");
2374                         return;
2375                 }
2376         }
2377 }
2378
2379 // addr = starting byte address within NAND flash
2380 static void print_page(u32 addr, bool spare_only)
2381 {
2382         u32 i, pg_no, pg_off;
2383         u32 blk_num = OFFSET_TO_BLOCK(addr), pg_num = OFFSET_TO_PAGE(addr);
2384
2385         if (addr % NF_PG_SZ) {
2386                 diag_printf("Non page-aligned read not supported here: 0x%x\n", addr);
2387                 return;
2388         }
2389         pg_no = addr / NF_PG_SZ;
2390         pg_off = addr % NF_PG_SZ;
2391         for (i = 0; i < num_of_nand_chips; i++) {
2392                 if (nfc_read_page(i, pg_no, pg_off) != 0) {
2393                         diag_printf("Error %d: uncorrectable. But still printing ...\n", __LINE__);
2394                 }
2395                 pg_off = 0;
2396                 diag_printf("\n============ Printing block(%d) page(%d)  ==============\n",
2397                                         blk_num, pg_num);
2398
2399                 diag_printf("<<<<<<<<< spare area >>>>>>>>>\n");
2400                 print_pkt_16((u16*)NAND_SPAR_BUF0, NF_SPARE_SZ);
2401
2402                 if (!spare_only) {
2403                         diag_printf("<<<<<<<<< main area >>>>>>>>>\n");
2404                         print_pkt_16((u16*)NAND_MAIN_BUF0, NF_PG_SZ / num_of_nand_chips);
2405                 }
2406
2407                 diag_printf("\n");
2408         }
2409 }