//#####DESCRIPTIONBEGIN####
//
// Author(s): Fred Fan
-// Contributors:
+// Contributors:
// Date: 2006-08-23
-// Purpose:
-// Description:
+// Purpose:
+// Description:
//
//####DESCRIPTIONEND####
//
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_io.h>
-
/* The defines of event bits */
#define FEC_EVENT_HBERR 0x80000000
#define FEC_EVENT_BABR 0x40000000
#define FEC_RESET 0x00000001
#define FEC_ETHER_EN 0x00000002
-/* the defins of MII operation */
+/* the defins of MII operation */
#define FEC_MII_ST 0x40000000
#define FEC_MII_OP_OFF 28
#define FEC_MII_OP_MASK 0x03
#define FEC_MII_DATA_OFF 0
#define FEC_MII_DATA_MASK 0x0000FFFF
-#define FEC_MII_FRAME ( FEC_MII_ST | FEC_MII_TA )
+#define FEC_MII_FRAME ( FEC_MII_ST | FEC_MII_TA )
#define FEC_MII_OP(x) ( ((x) & FEC_MII_OP_MASK) << FEC_MII_OP_OFF )
#define FEC_MII_PA(pa) (((pa)& FEC_MII_PA_MASK) << FEC_MII_PA_OFF)
#define FEC_MII_RA(ra) (((ra)& FEC_MII_RA_MASK) << FEC_MII_RA_OFF)
#define FEC_TCR_FDEN 0x00000004
/*the defines of buffer description*/
-#define FEC_BD_RX_NUM 32
+#define FEC_BD_RX_NUM 256
#define FEC_BD_TX_NUM 2
-typedef struct mxc_fec_reg_s
+#ifdef CYGPKG_HAL_ARM_MX25
+/*the defines for MIIGSK */
+
+/* RMII frequency control: 0=50MHz, 1=5MHz */
+#define MIIGSK_CFGR_FRCONT (1 << 6)
+
+/* loopback mode */
+#define MIIGSK_CFGR_LBMODE (1 << 4)
+
+/* echo mode */
+#define MIIGSK_CFGR_EMODE (1 << 3)
+
+/* MII gasket mode field */
+#define MIIGSK_CFGR_IF_MODE_MASK (3 << 0)
+
+/* MMI/7-Wire mode */
+#define MIIGSK_CFGR_IF_MODE_MII (0 << 0)
+
+/* RMII mode */
+#define MIIGSK_CFGR_IF_MODE_RMII (1 << 0)
+
+/* reflects MIIGSK Enable bit (RO) */
+#define MIIGSK_ENR_READY (1 << 2)
+
+/* enable MIGSK (set by default) */
+#define MIIGSK_ENR_EN (1 << 1)
+#endif
+
+typedef struct mxc_fec_reg_s
{
unsigned long res1;
/*0x004*/ unsigned long eir; /* Interrupt Event Register */
/*0x180*/ unsigned long erdsr; /*Pointer to Receive Descriptor Ring*/
/*0x184*/ unsigned long etdsr; /*Pointer to Transmit Descriptor Ring*/
/*0x188*/ unsigned long emrbr; /*Maximum Receive Buffer size*/
+#ifdef CYGPKG_HAL_ARM_MX25
+ unsigned long res13[93];
+/*0x300*/ unsigned short miigsk_cfgr; /* MIIGSK Configuration Register */
+ unsigned short res14[3];
+/*0x308*/ unsigned short miigsk_enr; /* MIIGSK Enable Register */
+#endif
} mxc_fec_reg_t;
#define BD_RX_ST_EMPTY 0x8000
{
unsigned short int length; /*packet size*/
unsigned short int status; /*control & statue of this buffer description*/
- unsigned char * data; /*frame buffer address*/
+ unsigned char *data; /*frame buffer address*/
} mxc_fec_bd_t;
-typedef struct mxc_fec_priv_s
+typedef struct mxc_fec_priv_s
{
- mxc_fec_reg_t * hw_reg; /*the register base address of FEC*/
+ mxc_fec_reg_t *hw_reg; /*the register base address of FEC*/
#ifdef CYGPKG_DEVS_ETH_PHY
eth_phy_access_t *phy;
#else
unsigned char res[2];
unsigned long status; /*the status of FEC device:link-status etc.*/
unsigned long tx_key; /*save the key delivered from send function*/
- mxc_fec_bd_t * rx_bd; /*the receive buffer description ring*/
- mxc_fec_bd_t * rx_cur; /*the next recveive buffer description*/
- mxc_fec_bd_t * tx_bd; /*the transmit buffer description rign*/
- mxc_fec_bd_t * tx_cur; /*the next transmit buffer description*/
- /*TODO: Add interrupt about fields*/
- /*TODO: Add timer about fields*/
+ mxc_fec_bd_t *rx_bd; /*the receive buffer description ring*/
+ mxc_fec_bd_t *rx_cur; /*the next recveive buffer description*/
+ mxc_fec_bd_t *tx_bd; /*the transmit buffer description rign*/
+ mxc_fec_bd_t *tx_cur; /*the next transmit buffer description*/
+ cyg_bool (*provide_esa)(unsigned char *);
} mxc_fec_priv_t;
#define MXC_FEC_PRIVATE(x) ((mxc_fec_priv_t *)(x)->driver_private)
#define FEC_STATUS_100M 0x10000000
/*The defines about PHY */
+#ifndef FEC_PHY_ADDR
#define PHY_PORT_ADDR 0x01
+#else
+#define PHY_PORT_ADDR FEC_PHY_ADDR
+#endif
#define PHY_CTRL_REG 0x00
#define PHY_CTRL_RESET 0x8000
#define PHY_CTRL_AUTO_NEG 0x1000
#define PHY_CTRL_FULL_DPLX 0x0100
-#define PHY_STATUS_REG 0x01
+#define PHY_STATUS_REG 0x01
#define PHY_STATUS_LINK_ST 0x0004
#define PHY_IDENTIFY_1 0x02
#define PHY_DIAG_RATE 0x0400
#define PHY_MODE_REG 0x15
-#define PHY_LED_SEL 0x200
+#define PHY_LED_SEL 0x200
+
+#define PHY_AUTO_NEG_REG 0x5
+#define PHY_AUTO_10BASET 0x20
+#define PHY_AUTO_10BASET_DPLX 0x40
+#define PHY_AUTO_100BASET 0x80
+#define PHY_AUTO_100BASET_DPLX 0x100
+
+#define PHY_AUTO_NEG_EXP_REG 0x6
+#define PHY_AUTO_NEG_NEW_PAGE 0x2
+#define PHY_AUTO_NEG_CAP 0x1
+#define PHY_INT_SRC_REG 29
+#define PHY_INT_AUTO_NEG 0x40
#define FEC_COMMON_TICK 2
#define FEC_COMMON_TIMEOUT (1000*1000)
#define FEC_MII_TICK 2