);
/*!
- * This is to calculate various parameters based on reference clock and
+ * This is to calculate various parameters based on reference clock and
* targeted clock based on the equation:
* t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
* This calculation is based on a fixed MFD value for simplicity.
*
* @return 0 if successful; non-zero otherwise.
*/
-int calc_pll_params(u32 ref, u32 target, u32 *p_pd,
+int calc_pll_params(u32 ref, u32 target, u32 *p_pd,
u32 *p_mfi, u32 *p_mfn, u32 *p_mfd)
{
u64 pd, mfi, mfn, n_target = (u64)target, n_ref = (u64)ref;
pll_mfd_fixed = 1024;
}
- // Make sure targeted freq is in the valid range. Otherwise the
+ // Make sure targeted freq is in the valid range. Otherwise the
// following calculation might be wrong!!!
if (target < PLL_FREQ_MIN || target > PLL_FREQ_MAX) {
return ERR_WRONG_CLK;
/*!
* This function assumes the expected core clock has to be changed by
* modifying the PLL. This is NOT true always but for most of the times,
- * it is. So it assumes the PLL output freq is the same as the expected
+ * it is. So it assumes the PLL output freq is the same as the expected
* core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
- * In the latter case, it will try to increase the presc value until
+ * In the latter case, it will try to increase the presc value until
* (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
* calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
- * on the targeted PLL and reference input clock to the PLL. Lastly,
+ * on the targeted PLL and reference input clock to the PLL. Lastly,
* it sets the register based on these values along with the dividers.
* Note 1) There is no value checking for the passed-in divider values
* so the caller has to make sure those values are sensible.
* 4) This function should not have allowed diag_printf() calls since
* the serial driver has been stoped. But leave then here to allow
* easy debugging by NOT calling the cyg_hal_plf_serial_stop().
- *
+ *
* @param ref pll input reference clock (32KHz or 26MHz)
* @param core_clk core clock in Hz
- * @param ahb_div ahb divider to divide the core clock to get ahb clock
+ * @param ahb_div ahb divider to divide the core clock to get ahb clock
* (ahb_div - 1) needs to be set in the register
* @param ipg_div ipg divider to divide the ahb clock to get ipg clock
* (ipg_div - 1) needs to be set in the register
diag_printf("can't make hsp_div=%d\n", hsp_div);
return ERR_NO_PRESC;
}
-
+
// get nfc_div - make sure optimal NFC clock but less than NFC_CLK_MAX
for (nfc_div = 1; nfc_div <= NFC_PODF_MAX; nfc_div++) {
if ((pll / (ahb_div * nfc_div)) <= NFC_CLK_MAX) {
return ret;
}
#ifdef CMD_CLOCK_DEBUG
- diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
+ diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
ref, pll, pd, mfi, mfn, mfd);
#endif
writel(pdr0, CCM_BASE_ADDR + CLKCTL_PDR0);
// calculate new pdr0
pdr0 &= ~0x00003FFF;
- pdr0 |= ((hsp_div - 1) << 11) | ((nfc_div - 1) << 8) | ((ipg_div - 1) << 6) |
+ pdr0 |= ((hsp_div - 1) << 11) | ((nfc_div - 1) << 8) | ((ipg_div - 1) << 6) |
((ahb_div - 1) << 3) | ((presc - 1) << 0);
// update PLL register
ipg_div = data[2]; // actual register field + 1
if (core_clk < (PLL_FREQ_MIN / PRESC_MAX) || core_clk > PLL_FREQ_MAX) {
- diag_printf("Targeted core clock should be within [%d - %d]\n",
+ diag_printf("Targeted core clock should be within [%d - %d]\n",
PLL_FREQ_MIN / PRESC_MAX, PLL_FREQ_MAX);
return;
}
- // find the ahb divider
+ // find the ahb divider
if (ahb_div > AHB_DIV_MAX) {
diag_printf("Invalid AHB divider: %d. Maximum value is %d\n",
ahb_div, AHB_DIV_MAX);
}
}
if (ahb_div > AHB_DIV_MAX || (core_clk / ahb_div) > AHB_CLK_MAX) {
- diag_printf("Can't make AHB=%d since max=%d\n",
+ diag_printf("Can't make AHB=%d since max=%d\n",
core_clk / ahb_div, AHB_CLK_MAX);
return;
}
// find the ipg divider
ahb_clk = core_clk / ahb_div;
if (ipg_div > IPG_DIV_MAX) {
- diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
+ diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
ipg_div, IPG_DIV_MAX);
return;
}
ipg_div++; // Make it =2
}
if (ipg_div > IPG_DIV_MAX || (ahb_clk / ipg_div) > IPG_CLK_MAX) {
- diag_printf("Can't make IPG=%d since max=%d\n",
+ diag_printf("Can't make IPG=%d since max=%d\n",
(ahb_clk / ipg_div), IPG_CLK_MAX);
return;
}
ipg_clk = ahb_clk / ipg_div;
- diag_printf("Trying to set core=%d ahb=%d ipg=%d...\n",
+ diag_printf("Trying to set core=%d ahb=%d ipg=%d...\n",
core_clk, ahb_clk, ipg_clk);
// stop the serial to be ready to adjust the clock
diag_printf("===========================================");
diag_printf("=============\n");
- diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
get_peri_clock(UART1_BAUD),
get_peri_clock(SSI1_BAUD),
get_peri_clock(SSI2_BAUD),
diag_printf("===========================================");
diag_printf("=============\n");
- diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
get_peri_clock(FIRI_BAUD),
get_peri_clock(SIM_BAUD),
get_peri_clock(MSTICK1_CLK),
val = readl(IOMUXC_BASE_ADDR + 0x80);
writel((val & 0xFFFF) | 0x12120000, IOMUXC_BASE_ADDR + 0x80);
- writel(0x12121212, IOMUXC_BASE_ADDR + 0x84);
- writel(0x12121212, IOMUXC_BASE_ADDR + 0x88);
+ writel(0x12123812, IOMUXC_BASE_ADDR + 0x84);
+
+ val = readl(IOMUXC_BASE_ADDR + 0x88);
+ writel((val & 0xFFFFFF00) | 0x12, IOMUXC_BASE_ADDR + 0x88);
+
+ /* Select CSPI 1 signals */
+ val = readl(IOMUXC_BASE_ADDR + 0x8);
+ writel((val | 0x4), IOMUXC_BASE_ADDR + 0x8);
+
+ val = readl(IOMUXC_BASE_ADDR + 0x78);
+ writel((val & 0xFFFFFF) | 0x24000000, IOMUXC_BASE_ADDR + 0x78);
+
+ val = readl(IOMUXC_BASE_ADDR + 0x7C);
+ writel((val & 0xFFFFFF00) | 0x24, IOMUXC_BASE_ADDR + 0x7C);
+
writel(0x12121212, IOMUXC_BASE_ADDR + 0x8C);
+
+ val = readl(IOMUXC_BASE_ADDR + 0x88);
+ writel((val & 0xFF) | 0x12121200, IOMUXC_BASE_ADDR + 0x88);
+}
+
+// The clocks are on by default. But need to setup the IOMUX
+void mxc_i2c_init(unsigned int module_base)
+{
+ unsigned int val, reg;
+
+ switch (module_base) {
+ case I2C_BASE_ADDR:
+ reg = IOMUXC_BASE_ADDR + 0xA0;
+ val = (readl(reg) & 0xFFFF0000) | 0x1212; // func mode
+ writel(val, reg);
+ break;
+ case I2C2_BASE_ADDR:
+ reg = IOMUXC_BASE_ADDR + 0x88;
+ val = (readl(reg) & 0xFFFFFF00) | 0x24; // alt mode 1
+ writel(val, reg);
+ reg = IOMUXC_BASE_ADDR + 0x84;
+ val = (readl(reg) & 0x00FFFFFF) | 0x24000000; // alt mode 1
+ writel(val, reg);
+ break;
+ case I2C3_BASE_ADDR:
+ reg = IOMUXC_BASE_ADDR + 0x84;
+ val = (readl(reg) & 0xFFFFFF00) | 0x24; // alt mode 1
+ writel(val, reg);
+ reg = IOMUXC_BASE_ADDR + 0x80;
+ val = (readl(reg) & 0x00FFFFFF) | 0x24000000; // alt mode 1
+ writel(val, reg);
+ break;
+ default:
+ diag_printf("Invalide I2C base: 0x%x\n", module_base);
+ return;
+ }
}
/*!
case SIM_BAUD:
clk_sel = ccmr & (1 << 24);
pdf = (mpdr0 >> 16) & 0x1F;
- ret_val = (clk_sel != 0) ? get_main_clock(IPG_CLK) :
+ ret_val = (clk_sel != 0) ? get_main_clock(IPG_CLK) :
pll_clock(USB_PLL) / (pdf + 1);
break;
case SSI1_BAUD:
case CSI_BAUD:
clk_sel = ccmr & (1 << 25);
pdf = (mpdr0 >> 23) & 0x1FF;
- ret_val = (clk_sel != 0) ? (pll_clock(SER_PLL) / (pdf + 1)) :
+ ret_val = (clk_sel != 0) ? (pll_clock(SER_PLL) / (pdf + 1)) :
(pll_clock(USB_PLL) / (pdf + 1));
break;
case FIRI_BAUD:
cosr = readl(CCM_BASE_ADDR + CLKCTL_COSR);
diag_printf("%s\n", clko_name[(cosr & 0xF) + 1]);
- diag_printf("COSR register[0x%x] = 0x%x\n",
+ diag_printf("COSR register[0x%x] = 0x%x\n",
(CCM_BASE_ADDR + CLKCTL_COSR), cosr);
}
/*
* The action should be either:
- * POLL_FUSE_PRGD
+ * POLL_FUSE_PRGD
* or:
* POLL_FUSE_SNSD
*/
int addr, addr_l, addr_h, reg_addr;
fuse_op_start();
-
+
addr = ((bank << 11) | (row << 3) | (bit & 0x7));
/* Set IIM Program Upper Address */
addr_h = (addr >> 8) & 0x000000FF;
#define INIT_STRING "12345678"
static char ready_to_blow[] = INIT_STRING;
-void quick_itoa(u32 num, char *a)
+void quick_itoa(u32 num, char *a)
{
- int i, j, k;
+ int i, j, k;
for (i = 0; i <= 7; i++) {
j = (num >> (4 * i)) & 0xF;
k = (j < 10) ? '0' : ('a' - 0xa);
}
return;
} else if (argc == 3) {
- if (strcasecmp(argv[1], "nandboot") == 0 &&
+ if (strcasecmp(argv[1], "nandboot") == 0 &&
strcasecmp(argv[2], ready_to_blow) == 0) {
#if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31)
diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
projects / karo-tx-redboot.git / blobdiff