};
#define PLL_FREQ_MAX(_ref_clk_) (4 * _ref_clk_ * PLL_MFI_MAX)
-#define PLL_FREQ_MIN(_ref_clk_) ((2 * _ref_clk_ * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
+#define PLL_FREQ_MIN(_ref_clk_) ((4 * _ref_clk_ * PLL_MFI_MIN) / PLL_PD_MAX)
#define MAX_DDR_CLK 400000000
#define AHB_CLK_MAX 133333333
#define IPG_CLK_MAX (AHB_CLK_MAX / 2)
// Now got pd and mfi already
mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
- dbg("%d: ref=%d, target=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
+ dbg("%d: ref=%d, target=%d, pd=%d, mfi=%d, mfn=%d, mfd=%d\n",
__LINE__, ref, target, pd, mfi, mfn, mfd);
- i = 1;
- if (mfn != 0)
+ if (mfn != 0) {
i = gcd(mfd, mfn);
+ mfn /= i;
+ mfd /= i;
+ } else {
+ mfd = 1;
+ }
pll->pd = pd;
pll->mfi = mfi;
- pll->mfn = mfn / i;
- pll->mfd = mfd / i;
+ pll->mfn = mfn;
+ pll->mfd = mfd;
return 0;
}
if (core_clk != 0) {
if ((core_clk < PLL_FREQ_MIN(PLL_REF_CLK)) || (core_clk > PLL_FREQ_MAX(PLL_REF_CLK))) {
- diag_printf("Targeted core clock should be within [%d - %d]\n",
- PLL_FREQ_MIN(PLL_REF_CLK), PLL_FREQ_MAX(PLL_REF_CLK));
+ diag_printf("Targeted core clock should be within [%d - %d] MHz\n",
+ PLL_FREQ_MIN(PLL_REF_CLK) / SZ_DEC_1M,
+ PLL_FREQ_MAX(PLL_REF_CLK) / SZ_DEC_1M);
return;
}
}