+
+#define AHBDIV (MPLL_REF_CLK_kHz * 2 / 3 / 1000 / CYGHWR_HAL_ARM_SOC_SYSTEM_CLOCK)
+
+#define CSCR_AHB_DIV(n) ((((n) & 3) - 1) << 8)
+#define CSCR_ARM_DIV(n) ((((n) & 3) - 1) << 12)
+#define CSCR_ARM_SRC(n) ((!!(n)) << 15)
+#define CSCR_MCU_SEL(n) ((!!(n)) << 16)
+#define CSCR_SP_SEL(n) ((!!(n)) << 17)
+#define CSCR_USB_DIV(n) ((((n) & 7) - 1) << 28)
+
+#define MPLL_CLK_DIV(khz) ((MPLL_REF_CLK_kHz * 2 / 3 + (khz) - 1) / (khz) - 1)
+#define MPLL_CLK_DIV2(khz) ((MPLL_REF_CLK_kHz * 4 / 3 + (khz) - 1) / (khz) - 4)
+#define SPLL_CLK_DIV(khz) ((SPLL_REF_CLK_kHz + (khz) - 1) / (khz) - 1)
+#define SPLL_CLK_DIV2(khz) ((SPLL_REF_CLK_kHz * 2 + (khz) - 1) / (khz) - 4)
+
+#define PCDR0_SSI2_DIV(pll, n) ((pll##_CLK_DIV2(n) & 0x3f) << 26)
+#define PCDR0_CLKO_DIV(n) ((((n) - 1) & 0x7) << 22)
+#define PCDR0_SSI1_DIV(pll, n) ((pll##_CLK_DIV2(n) & 0x3f) << 16)
+#define PCDR0_H264_DIV(pll, n) ((pll##_CLK_DIV2(n) & 0x3f) << 10)
+#define PCDR0_NFC_DIV(n) ((MPLL_CLK_DIV(n) & 0xf) << 6)
+#define PCDR0_MSHC_DIV(pll, n) ((pll##_CLK_DIV(n) & 0x3f) << 0)
+#define PCDR0_CLKO_EN (1 << 25)
+
+#define PCDR1_PER1_DIV(n) ((MPLL##_CLK_DIV(n) & 0x3f) << 0)
+#define PCDR1_PER2_DIV(n) ((MPLL##_CLK_DIV(n) & 0x3f) << 8)
+#define PCDR1_PER3_DIV(n) ((MPLL##_CLK_DIV(n) & 0x3f) << 16)
+#define PCDR1_PER4_DIV(n) ((MPLL##_CLK_DIV(n) & 0x3f) << 24)
+
+#ifndef PLL_REF_CLK_32768HZ
+#define MPLL_SRC (1 << 16)
+#define SPLL_SRC (1 << 17)
+#define FPM_ENABLE (1 << 2)
+#else
+#define MPLL_SRC (0 << 16)
+#define SPLL_SRC (0 << 17)
+#define FPM_ENABLE (1 << 2)
+#endif
+
+SOC_CRM_CSCR2_W: .word 0x03f00003 | \
+ FPM_ENABLE | MPLL_SRC | SPLL_SRC | \
+ CSCR_AHB_DIV(AHBDIV) | \
+ CSCR_ARM_DIV(1) | \
+ CSCR_USB_DIV(4) | \
+ CSCR_ARM_SRC(MPLL_REF_CLK_kHz / 1000 == CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK)
+SOC_CRM_PCDR0_W: .word PCDR0_SSI2_DIV(MPLL, 66500) | \
+ PCDR0_CLKO_DIV(8) | PCDR0_CLKO_EN | \
+ PCDR0_SSI1_DIV(MPLL, 66500) | \
+ PCDR0_H264_DIV(MPLL, 133000) | \
+ PCDR0_NFC_DIV(16625) | \
+ PCDR0_MSHC_DIV(MPLL, 66500)
+SOC_CRM_PCDR1_W: .word PCDR1_PER1_DIV(13300) | \
+ PCDR1_PER2_DIV(26600) | \
+ PCDR1_PER3_DIV(66500) | \
+ PCDR1_PER4_DIV(26600)