Merge branch 'tx53-ddr-calib'

diff --git a/README.KARO b/README.KARO
deleted file mode 100644 (file)
index 700e125..0000000
--- a/README.KARO
+++ /dev/null
@@ -1,28 +0,0 @@
-Build instructions for KARO specific RedBoot under Linux
-========================================================
-
-1. Prerequisites:
------------------
-
-- Make sure the gcc cross-compiler 'arm-linux-gcc' is installed and
-  can be found via the PATH environment variable
-- Determine what configuration (.ecc files in redboot/config/) is
-  required for the board that you want to program (see the file
-  'readme.txt' in the RedBoot directory of the Starterkit CD.)
-
-2. Configuring Redboot:
------------------------
-- Either edit the corresponding .ecc file or use the graphical
-  configuration tool installed under redboot/tools/bin/configtool to
-  modify and save the configuration settings.
-
-3. Compiling Redboot:
----------------------
-- enter the base directory 'redboot' of the redboot source tree
-- run sh build.sh [config[.ecc]] to build all or one specific
-  configuration
-
-
-The binary file that should be programmed into the flash rom of the
-Triton module is the '.bin' file that can be found under
-build/<config_name>/<config_name>_install/bin/

diff --git a/ReleaseNotes.txt b/ReleaseNotes.txt
index 4d9c2874f8e1e0bb22c43ac3626bbeb99796d7e3..8009f17869a9a7bc458b65911cda14248ca424dd 100755 (executable)
--- a/ReleaseNotes.txt
+++ b/ReleaseNotes.txt
@@ -2,6 +2,12 @@
   Ka-Ro Electronics GmbH
 
   ===========================================================
+ v1.5.6 (2013-08-19)
+  Changes:
+    TX53:
+      - updated SDRAM initialization to work with NT5CB128M16 mask
+        revision 'F' (see: TX53-PCN-2013-08.pdf)
+
  v1.5.5 (2012-09-25)
   Changes:
     TX27:

diff --git a/config/TX27-40x0.ecc b/config/TX27-40x0.ecc
index 0715ffb6214da1faf54d65abe74be87a5eb5ce19..4f59d2a54ee529bc161a9cd1cd38e34bfab54d38 100644 (file)
--- a/config/TX27-40x0.ecc
+++ b/config/TX27-40x0.ecc
@@ -3169,6 +3169,10 @@ cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
     #     CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT (unknown) == 0
     #   --> 399
     # Legal values: 266 399
+
+    # The following properties are affected by this value
+    # option CYGOPT_MX27_WORKAROUND_ENGcm11563
+    #     Requires: CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == "399"
 };
 
 # System clock (hclk) rate
@@ -3534,6 +3538,22 @@ cdl_option CYGPKG_HAL_ARM_TX27_CFLAGS_REMOVE {
     # Default value: ""
 };
 
+# Enable workaround for Erratum ENGcm11563
+# This option enables the software workaround for
+# ENGcm11563 (ARM core lockup due to invalid
+# duty cycle of ARM clock at 399 MHz.
+#
+cdl_option CYGOPT_MX27_WORKAROUND_ENGcm11563 {
+    # Flavor: bool
+    # No user value, uncomment the following line to provide one.
+    # user_value 1
+    # value_source default
+    # Default value: 1
+    # Requires: CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == "399"
+    #     CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == 399
+    #   --> 1
+};
+
 # <
 # Memory layout
 #

diff --git a/config/TX27-40x1.ecc b/config/TX27-40x1.ecc
index fdc182113c39e346c95de17a34078c0d285394a3..94bcb263eacac16b774c380687068630904e3a0f 100644 (file)
--- a/config/TX27-40x1.ecc
+++ b/config/TX27-40x1.ecc
@@ -3169,6 +3169,10 @@ cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
     #     CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT (unknown) == 0
     #   --> 399
     # Legal values: 266 399
+
+    # The following properties are affected by this value
+    # option CYGOPT_MX27_WORKAROUND_ENGcm11563
+    #     Requires: CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == "399"
 };
 
 # System clock (hclk) rate
@@ -3533,6 +3537,22 @@ cdl_option CYGPKG_HAL_ARM_TX27_CFLAGS_REMOVE {
     # Default value: ""
 };
 
+# Enable workaround for Erratum ENGcm11563
+# This option enables the software workaround for
+# ENGcm11563 (ARM core lockup due to invalid
+# duty cycle of ARM clock at 399 MHz.
+#
+cdl_option CYGOPT_MX27_WORKAROUND_ENGcm11563 {
+    # Flavor: bool
+    # No user value, uncomment the following line to provide one.
+    # user_value 1
+    # value_source default
+    # Default value: 1
+    # Requires: CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == "399"
+    #     CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == 399
+    #   --> 1
+};
+
 # <
 # Memory layout
 #

diff --git a/packages/hal/arm/mx27/karo/v1_0/cdl/hal_arm_tx27.cdl b/packages/hal/arm/mx27/karo/v1_0/cdl/hal_arm_tx27.cdl
index 4bc5414269b5c5821aa8e462298f820fc29e03c9..45dd774ce43a664451ab26e7e6a1f206e99878e9 100644 (file)
--- a/packages/hal/arm/mx27/karo/v1_0/cdl/hal_arm_tx27.cdl
+++ b/packages/hal/arm/mx27/karo/v1_0/cdl/hal_arm_tx27.cdl
@@ -247,6 +247,16 @@ cdl_package CYGPKG_HAL_ARM_TX27KARO {
                 the set of global flags if present."
         }
 
+        cdl_option CYGOPT_MX27_WORKAROUND_ENGcm11563 {
+            display "Enable workaround for Erratum ENGcm11563"
+            flavor bool
+            default_value { 1 }
+           requires      {CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == "399"}
+            description   "
+                This option enables the software workaround for
+                ENGcm11563 (ARM core lockup due to invalid
+               duty cycle of ARM clock at 399 MHz."
+        }
     }
 
     cdl_component CYGHWR_MEMORY_LAYOUT {

diff --git a/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h b/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h
index 295e446ca750b3a5492f2a76469302d05c919c66..e6edab5724161d1954928d307f0e93ceb3edb155 100644 (file)
--- a/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h
+++ b/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h
@@ -413,9 +413,11 @@ NAND_ClockSetup:
        ldr     r0, SOC_CRM_BASE_W
        // disable PLL update first
        ldr     r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+       /* clear ARM_SRC & ARM_DIV required as workaround for ENGcm12387 */
+       bic     r1, r1, #((1 << 15) | (3 << 12))
        orr     r1, r1, #(1 << 31)
 #ifdef PLL_REF_CLK_32768HZ
-       orr     r1, r1, #(1 << 3)       // disable OSC26M
+       orr     r1, r1, #(1 << 3)       // disable 26MHz osc
 #else
        bic     r1, r1, #(1 << 3)       // enable 26MHz osc
 #endif
@@ -430,6 +432,12 @@ NAND_ClockSetup:
        str     r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
 
        ldr     r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+#ifdef PLL_REF_CLK_32768HZ
+       // Make sure to use CKIL
+       bic     r1, r1, #(3 << 16)
+#else
+       orr     r1, r1, #(3 << 16)      // select 26MHz
+#endif
        orr     r1, r1, #(0x3 << 18)    // SPLL_RESTART | MPLL_RESTART
        orr     r1, r1, #(0x3 << 0)     // SPLL_ENABLE | MPLL_ENABLE
        str     r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]