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(parent: f779d73) | patch
pantheon: define CONFIG_SYS_CACHELINE_SIZE
authorLei Wen <[leiwen@marvell.com]>
Tue, 1 Nov 2011 10:55:56 +0000 (16:25 +0530)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Thu, 3 Nov 2011 21:56:22 +0000 (22:56 +0100)
commit0caac5f4155a1db6c5ce921c7f9294b6b46e7744
treec8749f7c0bb033051d9ea07f2d950fd527023098tree | snapshot
parentf779d739d67653c0d77f50cb18c315b2d39de075commit | diff
pantheon: define CONFIG_SYS_CACHELINE_SIZE

By default, on Pantheon SoC DCache Lnd ICache line
lengths are 32 bytes long

Signed-off-by: Lei Wen <leiwen@marvell.com>
arch/arm/include/asm/arch-pantheon/config.h diff | blob | history
UBoot for KaRo TX COM modules