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ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3
authorMarek Vasut <marex@denx.de>
Sun, 19 Jul 2015 05:03:15 +0000 (07:03 +0200)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 06:17:31 +0000 (08:17 +0200)
commit21db0e764dca4f8701922b300eb4ab1b0acd27a3
tree178b0136bfbca93e4821e16b7af83fdd5d21a688tree | snapshot
parent2cfeb514aa0a7233a49bda707b4b7472f9a4e641commit | diff
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3

Clean up odd multiline loop, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
drivers/ddr/altera/sequencer.c diff | blob | history
UBoot for KaRo TX COM modules