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Blackfin: add workaround for anomaly 05000242
authorMike Frysinger <vapier@gentoo.org>
Sat, 4 Apr 2009 12:10:22 +0000 (08:10 -0400)
committerMike Frysinger <vapier@gentoo.org>
Mon, 6 Apr 2009 21:37:48 +0000 (17:37 -0400)
commit48ab1509254a4c175e4f65c478a978928ffe09ec
tree16a43aec668305a3dce6e08be4fc5f1387574cfetree | snapshot
parentce1fe4ba6bb9df7c57351436fa17d1af8bbe7916commit | diff
Blackfin: add workaround for anomaly 05000242

DESCRIPTION:
If the DF bit is set prior to a hardware reset, the PLL will continue to
divide CLKIN by 2 after the hardware reset, but the DF bit itself will be
cleared in the PLL_CTL register.

WORKAROUND:
Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by
2 after reset.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
cpu/blackfin/initcode.c diff | blob | history
UBoot for KaRo TX COM modules