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driver/ddr/fsl: Fix MRC_CYC calculation for DDR3
authorYork Sun <yorksun@freescale.com>
Tue, 2 Dec 2014 19:18:09 +0000 (11:18 -0800)
committerYork Sun <yorksun@freescale.com>
Mon, 15 Dec 2014 17:15:12 +0000 (09:15 -0800)
commit938bbb6013f051808c08204184e94d0cdcb6dbff
tree8102d1ed2cb0ef18f642c606d4ade71219c62f64tree | snapshot
parent84d13c58104ea121a8d38a1d9c71e404d8666875commit | diff
driver/ddr/fsl: Fix MRC_CYC calculation for DDR3

For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.

DDR4 is not affected by this change.

Signed-off-by: York Sun <yorksun@freescale.com>
drivers/ddr/fsl/ctrl_regs.c diff | blob | history
UBoot for KaRo TX COM modules