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(parent: 0caac5f) | patch
armada100: define CONFIG_SYS_CACHELINE_SIZE
authorLei Wen <[leiwen@marvell.com]>
Tue, 1 Nov 2011 10:55:56 +0000 (16:25 +0530)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Thu, 3 Nov 2011 21:56:22 +0000 (22:56 +0100)
commitabbbbdd7e1232cfe5ccde8da9d4cc1fa609f8456
treeb591517ea82849ff240017312972bfc0daf3fe42tree | snapshot
parent0caac5f4155a1db6c5ce921c7f9294b6b46e7744commit | diff
armada100: define CONFIG_SYS_CACHELINE_SIZE

By default, on Armada100 SoC DCache Lnd ICache line
lengths are 32 bytes long

Signed-off-by: Lei Wen <leiwen@marvell.com>
arch/arm/include/asm/arch-armada100/config.h diff | blob | history
UBoot for KaRo TX COM modules