1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
4 The follow error types are supported:
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
9 The following section describes the EDAC DT node binding.
12 - compatible : Shall be "apm,xgene-edac".
13 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
14 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
15 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
16 - regmap-efuse : Regmap of the PMD efuse resource.
17 - reg : First resource shall be the CPU bus (PCP) resource.
18 - interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
21 Required properties for memory controller subnode:
22 - compatible : Shall be "apm,xgene-edac-mc".
23 - reg : First resource shall be the memory controller unit
25 - memory-controller : Instance number of the memory controller.
27 Required properties for PMD subnode:
28 - compatible : Shall be "apm,xgene-edac-pmd" or
29 "apm,xgene-edac-pmd-v2".
30 - reg : First resource shall be the PMD resource.
31 - pmd-controller : Instance number of the PMD controller.
35 compatible = "apm,xgene-csw", "syscon";
36 reg = <0x0 0x7e200000 0x0 0x1000>;
40 compatible = "apm,xgene-mcb", "syscon";
41 reg = <0x0 0x7e700000 0x0 0x1000>;
45 compatible = "apm,xgene-mcb", "syscon";
46 reg = <0x0 0x7e720000 0x0 0x1000>;
49 efuse: efuse@1054a000 {
50 compatible = "apm,xgene-efuse", "syscon";
51 reg = <0x0 0x1054a000 0x0 0x20>;
55 compatible = "apm,xgene-edac";
60 regmap-mcba = <&mcba>;
61 regmap-mcbb = <&mcbb>;
62 regmap-efuse = <&efuse>;
63 reg = <0x0 0x78800000 0x0 0x100>;
64 interrupts = <0x0 0x20 0x4>,
69 compatible = "apm,xgene-edac-mc";
70 reg = <0x0 0x7e800000 0x0 0x1000>;
71 memory-controller = <0>;
75 compatible = "apm,xgene-edac-pmd";
76 reg = <0x0 0x7c000000 0x0 0x200000>;