Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt

   1 NVIDIA Tegra host1x
   2
   3 Required properties:
   4 - compatible: "nvidia,tegra<chip>-host1x"
   5 - reg: Physical base address and length of the controller's registers.
   6 - interrupts: The interrupt outputs from the controller.
   7 - #address-cells: The number of cells used to represent physical base addresses
   8   in the host1x address space. Should be 1.
   9 - #size-cells: The number of cells used to represent the size of an address
  10   range in the host1x address space. Should be 1.
  11 - ranges: The mapping of the host1x address space to the CPU address space.
  12
  13 The host1x top-level node defines a number of children, each representing one
  14 of the following host1x client modules:
  15
  16 - mpe: video encoder
  17
  18   Required properties:
  19   - compatible: "nvidia,tegra<chip>-mpe"
  20   - reg: Physical base address and length of the controller's registers.
  21   - interrupts: The interrupt outputs from the controller.
  22
  23 - vi: video input
  24
  25   Required properties:
  26   - compatible: "nvidia,tegra<chip>-vi"
  27   - reg: Physical base address and length of the controller's registers.
  28   - interrupts: The interrupt outputs from the controller.
  29
  30 - epp: encoder pre-processor
  31
  32   Required properties:
  33   - compatible: "nvidia,tegra<chip>-epp"
  34   - reg: Physical base address and length of the controller's registers.
  35   - interrupts: The interrupt outputs from the controller.
  36
  37 - isp: image signal processor
  38
  39   Required properties:
  40   - compatible: "nvidia,tegra<chip>-isp"
  41   - reg: Physical base address and length of the controller's registers.
  42   - interrupts: The interrupt outputs from the controller.
  43
  44 - gr2d: 2D graphics engine
  45
  46   Required properties:
  47   - compatible: "nvidia,tegra<chip>-gr2d"
  48   - reg: Physical base address and length of the controller's registers.
  49   - interrupts: The interrupt outputs from the controller.
  50
  51 - gr3d: 3D graphics engine
  52
  53   Required properties:
  54   - compatible: "nvidia,tegra<chip>-gr3d"
  55   - reg: Physical base address and length of the controller's registers.
  56
  57 - dc: display controller
  58
  59   Required properties:
  60   - compatible: "nvidia,tegra<chip>-dc"
  61   - reg: Physical base address and length of the controller's registers.
  62   - interrupts: The interrupt outputs from the controller.
  63
  64   Each display controller node has a child node, named "rgb", that represents
  65   the RGB output associated with the controller. It can take the following
  66   optional properties:
  67   - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  68   - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  69   - nvidia,edid: supplies a binary EDID blob
  70   - nvidia,panel: phandle of a display panel
  71
  72 - hdmi: High Definition Multimedia Interface
  73
  74   Required properties:
  75   - compatible: "nvidia,tegra<chip>-hdmi"
  76   - reg: Physical base address and length of the controller's registers.
  77   - interrupts: The interrupt outputs from the controller.
  78   - vdd-supply: regulator for supply voltage
  79   - pll-supply: regulator for PLL
  80
  81   Optional properties:
  82   - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  83   - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  84   - nvidia,edid: supplies a binary EDID blob
  85   - nvidia,panel: phandle of a display panel
  86
  87 - tvo: TV encoder output
  88
  89   Required properties:
  90   - compatible: "nvidia,tegra<chip>-tvo"
  91   - reg: Physical base address and length of the controller's registers.
  92   - interrupts: The interrupt outputs from the controller.
  93
  94 - dsi: display serial interface
  95
  96   Required properties:
  97   - compatible: "nvidia,tegra<chip>-dsi"
  98   - reg: Physical base address and length of the controller's registers.
  99
 100 Example:
 101
 102 / {
 103         ...
 104
 105         host1x {
 106                 compatible = "nvidia,tegra20-host1x", "simple-bus";
 107                 reg = <0x50000000 0x00024000>;
 108                 interrupts = <0 65 0x04   /* mpcore syncpt */
 109                               0 67 0x04>; /* mpcore general */
 110
 111                 #address-cells = <1>;
 112                 #size-cells = <1>;
 113
 114                 ranges = <0x54000000 0x54000000 0x04000000>;
 115
 116                 mpe {
 117                         compatible = "nvidia,tegra20-mpe";
 118                         reg = <0x54040000 0x00040000>;
 119                         interrupts = <0 68 0x04>;
 120                 };
 121
 122                 vi {
 123                         compatible = "nvidia,tegra20-vi";
 124                         reg = <0x54080000 0x00040000>;
 125                         interrupts = <0 69 0x04>;
 126                 };
 127
 128                 epp {
 129                         compatible = "nvidia,tegra20-epp";
 130                         reg = <0x540c0000 0x00040000>;
 131                         interrupts = <0 70 0x04>;
 132                 };
 133
 134                 isp {
 135                         compatible = "nvidia,tegra20-isp";
 136                         reg = <0x54100000 0x00040000>;
 137                         interrupts = <0 71 0x04>;
 138                 };
 139
 140                 gr2d {
 141                         compatible = "nvidia,tegra20-gr2d";
 142                         reg = <0x54140000 0x00040000>;
 143                         interrupts = <0 72 0x04>;
 144                 };
 145
 146                 gr3d {
 147                         compatible = "nvidia,tegra20-gr3d";
 148                         reg = <0x54180000 0x00040000>;
 149                 };
 150
 151                 dc@54200000 {
 152                         compatible = "nvidia,tegra20-dc";
 153                         reg = <0x54200000 0x00040000>;
 154                         interrupts = <0 73 0x04>;
 155
 156                         rgb {
 157                                 status = "disabled";
 158                         };
 159                 };
 160
 161                 dc@54240000 {
 162                         compatible = "nvidia,tegra20-dc";
 163                         reg = <0x54240000 0x00040000>;
 164                         interrupts = <0 74 0x04>;
 165
 166                         rgb {
 167                                 status = "disabled";
 168                         };
 169                 };
 170
 171                 hdmi {
 172                         compatible = "nvidia,tegra20-hdmi";
 173                         reg = <0x54280000 0x00040000>;
 174                         interrupts = <0 75 0x04>;
 175                         status = "disabled";
 176                 };
 177
 178                 tvo {
 179                         compatible = "nvidia,tegra20-tvo";
 180                         reg = <0x542c0000 0x00040000>;
 181                         interrupts = <0 76 0x04>;
 182                         status = "disabled";
 183                 };
 184
 185                 dsi {
 186                         compatible = "nvidia,tegra20-dsi";
 187                         reg = <0x54300000 0x00040000>;
 188                         status = "disabled";
 189                 };
 190         };
 191
 192         ...
 193 };