1 * Renesas Electronics Ethernet AVB
3 This file provides information on what the device node for the Ethernet AVB
7 - compatible: "renesas,etheravb-r8a7790" if the device is a part of R8A7790 SoC.
8 "renesas,etheravb-r8a7794" if the device is a part of R8A7794 SoC.
9 "renesas,etheravb-r8a7795" if the device is a part of R8A7795 SoC.
10 "renesas,etheravb-rcar-gen2" for generic R-Car Gen 2 compatible interface.
11 "renesas,etheravb-rcar-gen3" for generic R-Car Gen 3 compatible interface.
13 When compatible with the generic version, nodes must list the
14 SoC-specific version corresponding to the platform first
15 followed by the generic version.
17 - reg: offset and length of (1) the register block and (2) the stream buffer.
18 - interrupts: A list of interrupt-specifiers, one for each entry in
20 If interrupt-names is not present, an interrupt specifier
21 for a single muxed interrupt.
22 - phy-mode: see ethernet.txt file in the same directory.
23 - phy-handle: see ethernet.txt file in the same directory.
24 - #address-cells: number of address cells for the MDIO bus, must be equal to 1.
25 - #size-cells: number of size cells on the MDIO bus, must be equal to 0.
26 - clocks: clock phandle and specifier pair.
27 - pinctrl-0: phandle, referring to a default pin configuration node.
30 - interrupt-parent: the phandle for the interrupt controller that services
31 interrupts for this device.
32 - interrupt-names: A list of interrupt names.
33 For the R8A7795 SoC this property is mandatory;
34 it should include one entry per channel, named "ch%u",
35 where %u is the channel number ranging from 0 to 24.
36 For other SoCs this property is optional; if present
37 it should contain "mux" for a single muxed interrupt.
38 - pinctrl-names: pin configuration state name ("default").
39 - renesas,no-ether-link: boolean, specify when a board does not provide a proper
41 - renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is
42 active-low instead of normal active-high.
47 compatible = "renesas,etheravb-r8a7795", "renesas,etheravb-rcar-gen3";
48 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
49 interrupt-parent = <&gic>;
50 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
53 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
57 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
75 interrupt-names = "ch0", "ch1", "ch2", "ch3",
76 "ch4", "ch5", "ch6", "ch7",
77 "ch8", "ch9", "ch10", "ch11",
78 "ch12", "ch13", "ch14", "ch15",
79 "ch16", "ch17", "ch18", "ch19",
80 "ch20", "ch21", "ch22", "ch23",
82 clocks = <&mstp8_clks R8A7795_CLK_ETHERAVB>;
83 power-domains = <&cpg_clocks>;
84 phy-mode = "rgmii-id";
87 pinctrl-0 = <ðer_pins>;
88 pinctrl-names = "default";
89 renesas,no-ether-link;
93 phy0: ethernet-phy@0 {
107 interrupt-parent = <&gpio2>;
108 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;