4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
19 select EDAC_ATOMIC_SCRUB
20 select GENERIC_ALLOCATOR
21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
23 select GENERIC_IDLE_POLL_SETUP
24 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW
26 select GENERIC_IRQ_SHOW_LEVEL
27 select GENERIC_PCI_IOMAP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select GENERIC_STRNCPY_FROM_USER
31 select GENERIC_STRNLEN_USER
32 select HANDLE_DOMAIN_IRQ
33 select HARDIRQS_SW_RESEND
34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
38 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
39 select HAVE_ARCH_TRACEHOOK
41 select HAVE_CC_STACKPROTECTOR
42 select HAVE_CONTEXT_TRACKING
43 select HAVE_C_RECORDMCOUNT
44 select HAVE_DEBUG_KMEMLEAK
45 select HAVE_DMA_API_DEBUG
47 select HAVE_DMA_CONTIGUOUS if MMU
48 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
49 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
50 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
51 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
52 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
53 select HAVE_GENERIC_DMA_COHERENT
54 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
55 select HAVE_IDE if PCI || ISA || PCMCIA
56 select HAVE_IRQ_TIME_ACCOUNTING
57 select HAVE_KERNEL_GZIP
58 select HAVE_KERNEL_LZ4
59 select HAVE_KERNEL_LZMA
60 select HAVE_KERNEL_LZO
62 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
63 select HAVE_KRETPROBES if (HAVE_KPROBES)
65 select HAVE_MOD_ARCH_SPECIFIC
66 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
67 select HAVE_OPTPROBES if !THUMB2_KERNEL
68 select HAVE_PERF_EVENTS
70 select HAVE_PERF_USER_STACK_DUMP
71 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
72 select HAVE_REGS_AND_STACK_ACCESS_API
73 select HAVE_SYSCALL_TRACEPOINTS
75 select HAVE_VIRT_CPU_ACCOUNTING_GEN
76 select IRQ_FORCED_THREADING
77 select MODULES_USE_ELF_REL
80 select OLD_SIGSUSPEND3
81 select PERF_USE_VMALLOC
83 select SYS_SUPPORTS_APM_EMULATION
84 # Above selects are sorted alphabetically; please add new ones
85 # according to that. Thanks.
87 The ARM series is a line of low-power-consumption RISC chip designs
88 licensed by ARM Ltd and targeted at embedded applications and
89 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
90 manufactured, but legacy ARM-based PC hardware remains popular in
91 Europe. There is an ARM Linux project with a web page at
92 <http://www.arm.linux.org.uk/>.
94 config ARM_HAS_SG_CHAIN
95 select ARCH_HAS_SG_CHAIN
98 config NEED_SG_DMA_LENGTH
101 config ARM_DMA_USE_IOMMU
103 select ARM_HAS_SG_CHAIN
104 select NEED_SG_DMA_LENGTH
108 config ARM_DMA_IOMMU_ALIGNMENT
109 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
113 DMA mapping framework by default aligns all buffers to the smallest
114 PAGE_SIZE order which is greater than or equal to the requested buffer
115 size. This works well for buffers up to a few hundreds kilobytes, but
116 for larger buffers it just a waste of address space. Drivers which has
117 relatively small addressing window (like 64Mib) might run out of
118 virtual space with just a few allocations.
120 With this parameter you can specify the maximum PAGE_SIZE order for
121 DMA IOMMU buffers. Larger buffers will be aligned only to this
122 specified order. The order is expressed as a power of two multiplied
127 config MIGHT_HAVE_PCI
130 config SYS_SUPPORTS_APM_EMULATION
135 select GENERIC_ALLOCATOR
146 The Extended Industry Standard Architecture (EISA) bus was
147 developed as an open alternative to the IBM MicroChannel bus.
149 The EISA bus provided some of the features of the IBM MicroChannel
150 bus while maintaining backward compatibility with cards made for
151 the older ISA bus. The EISA bus saw limited use between 1988 and
152 1995 when it was made obsolete by the PCI bus.
154 Say Y here if you are building a kernel for an EISA-based machine.
161 config STACKTRACE_SUPPORT
165 config HAVE_LATENCYTOP_SUPPORT
170 config LOCKDEP_SUPPORT
174 config TRACE_IRQFLAGS_SUPPORT
178 config RWSEM_XCHGADD_ALGORITHM
182 config ARCH_HAS_ILOG2_U32
185 config ARCH_HAS_ILOG2_U64
188 config ARCH_HAS_BANDGAP
191 config FIX_EARLYCON_MEM
194 config GENERIC_HWEIGHT
198 config GENERIC_CALIBRATE_DELAY
202 config ARCH_MAY_HAVE_PC_FDC
208 config NEED_DMA_MAP_STATE
211 config ARCH_SUPPORTS_UPROBES
214 config ARCH_HAS_DMA_SET_COHERENT_MASK
217 config GENERIC_ISA_DMA
223 config NEED_RET_TO_USER
231 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
232 default DRAM_BASE if REMAP_VECTORS_TO_RAM
235 The base address of exception vectors. This must be two pages
238 config ARM_PATCH_PHYS_VIRT
239 bool "Patch physical to virtual translations at runtime" if EMBEDDED
241 depends on !XIP_KERNEL && MMU
242 depends on !ARCH_REALVIEW || !SPARSEMEM
244 Patch phys-to-virt and virt-to-phys translation functions at
245 boot and module load time according to the position of the
246 kernel in system memory.
248 This can only be used with non-XIP MMU kernels where the base
249 of physical memory is at a 16MB boundary.
251 Only disable this option if you know that you do not require
252 this feature (eg, building a kernel for a single machine) and
253 you need to shrink the kernel to the minimal size.
255 config NEED_MACH_IO_H
258 Select this when mach/io.h is required to provide special
259 definitions for this platform. The need for mach/io.h should
260 be avoided when possible.
262 config NEED_MACH_MEMORY_H
265 Select this when mach/memory.h is required to provide special
266 definitions for this platform. The need for mach/memory.h should
267 be avoided when possible.
270 hex "Physical address of main memory" if MMU
271 depends on !ARM_PATCH_PHYS_VIRT
272 default DRAM_BASE if !MMU
273 default 0x00000000 if ARCH_EBSA110 || \
278 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
279 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
280 default 0x20000000 if ARCH_S5PV210
281 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
282 default 0xc0000000 if ARCH_SA1100
284 Please provide the physical address corresponding to the
285 location of main memory in your system.
291 config PGTABLE_LEVELS
293 default 3 if ARM_LPAE
296 source "init/Kconfig"
298 source "kernel/Kconfig.freezer"
303 bool "MMU-based Paged Memory Management Support"
306 Select if you want MMU-based virtualised addressing space
307 support by paged memory management. If unsure, say 'Y'.
310 # The "ARM system type" choice list is ordered alphabetically by option
311 # text. Please add new entries in the option alphabetic order.
314 prompt "ARM system type"
315 default ARCH_VERSATILE if !MMU
316 default ARCH_MULTIPLATFORM if MMU
318 config ARCH_MULTIPLATFORM
319 bool "Allow multiple platforms to be selected"
321 select ARCH_WANT_OPTIONAL_GPIOLIB
322 select ARM_HAS_SG_CHAIN
323 select ARM_PATCH_PHYS_VIRT
327 select GENERIC_CLOCKEVENTS
328 select MIGHT_HAVE_PCI
329 select MULTI_IRQ_HANDLER
333 config ARM_SINGLE_ARMV7M
334 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
336 select ARCH_WANT_OPTIONAL_GPIOLIB
342 select GENERIC_CLOCKEVENTS
348 bool "ARM Ltd. RealView family"
349 select ARCH_WANT_OPTIONAL_GPIOLIB
351 select ARM_TIMER_SP804
353 select COMMON_CLK_VERSATILE
354 select GENERIC_CLOCKEVENTS
355 select GPIO_PL061 if GPIOLIB
357 select NEED_MACH_MEMORY_H
358 select PLAT_VERSATILE
359 select PLAT_VERSATILE_SCHED_CLOCK
361 This enables support for ARM Ltd RealView boards.
363 config ARCH_VERSATILE
364 bool "ARM Ltd. Versatile family"
365 select ARCH_WANT_OPTIONAL_GPIOLIB
367 select ARM_TIMER_SP804
370 select GENERIC_CLOCKEVENTS
371 select HAVE_MACH_CLKDEV
373 select PLAT_VERSATILE
374 select PLAT_VERSATILE_CLOCK
375 select PLAT_VERSATILE_SCHED_CLOCK
376 select VERSATILE_FPGA_IRQ
378 This enables support for ARM Ltd Versatile board.
381 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
382 select ARCH_REQUIRE_GPIOLIB
387 select GENERIC_CLOCKEVENTS
391 Support for Cirrus Logic 711x/721x/731x based boards.
394 bool "Cortina Systems Gemini"
395 select ARCH_REQUIRE_GPIOLIB
398 select GENERIC_CLOCKEVENTS
400 Support for the Cortina Systems Gemini family SoCs
404 select ARCH_USES_GETTIMEOFFSET
407 select NEED_MACH_IO_H
408 select NEED_MACH_MEMORY_H
411 This is an evaluation board for the StrongARM processor available
412 from Digital. It has limited hardware on-board, including an
413 Ethernet interface, two PCMCIA sockets, two serial ports and a
418 select ARCH_HAS_HOLES_MEMORYMODEL
419 select ARCH_REQUIRE_GPIOLIB
421 select ARM_PATCH_PHYS_VIRT
427 select GENERIC_CLOCKEVENTS
429 This enables support for the Cirrus EP93xx series of CPUs.
431 config ARCH_FOOTBRIDGE
435 select GENERIC_CLOCKEVENTS
437 select NEED_MACH_IO_H if !MMU
438 select NEED_MACH_MEMORY_H
440 Support for systems based on the DC21285 companion chip
441 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
444 bool "Hilscher NetX based"
448 select GENERIC_CLOCKEVENTS
450 This enables support for systems based on the Hilscher NetX Soc
456 select NEED_MACH_MEMORY_H
457 select NEED_RET_TO_USER
463 Support for Intel's IOP13XX (XScale) family of processors.
468 select ARCH_REQUIRE_GPIOLIB
471 select NEED_RET_TO_USER
475 Support for Intel's 80219 and IOP32X (XScale) family of
481 select ARCH_REQUIRE_GPIOLIB
484 select NEED_RET_TO_USER
488 Support for Intel's IOP33X (XScale) family of processors.
493 select ARCH_HAS_DMA_SET_COHERENT_MASK
494 select ARCH_REQUIRE_GPIOLIB
495 select ARCH_SUPPORTS_BIG_ENDIAN
498 select DMABOUNCE if PCI
499 select GENERIC_CLOCKEVENTS
500 select MIGHT_HAVE_PCI
501 select NEED_MACH_IO_H
502 select USB_EHCI_BIG_ENDIAN_DESC
503 select USB_EHCI_BIG_ENDIAN_MMIO
505 Support for Intel's IXP4XX (XScale) family of processors.
509 select ARCH_REQUIRE_GPIOLIB
511 select GENERIC_CLOCKEVENTS
512 select MIGHT_HAVE_PCI
516 select PLAT_ORION_LEGACY
518 Support for the Marvell Dove SoC 88AP510
521 bool "Marvell MV78xx0"
522 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
527 select PLAT_ORION_LEGACY
529 Support for the following Marvell MV78xx0 series SoCs:
535 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
540 select PLAT_ORION_LEGACY
541 select MULTI_IRQ_HANDLER
543 Support for the following Marvell Orion 5x series SoCs:
544 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
545 Orion-2 (5281), Orion-1-90 (6183).
548 bool "Marvell PXA168/910/MMP2"
550 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_ALLOCATOR
553 select GENERIC_CLOCKEVENTS
556 select MULTI_IRQ_HANDLER
561 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
564 bool "Micrel/Kendin KS8695"
565 select ARCH_REQUIRE_GPIOLIB
568 select GENERIC_CLOCKEVENTS
569 select NEED_MACH_MEMORY_H
571 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
572 System-on-Chip devices.
575 bool "Nuvoton W90X900 CPU"
576 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_CLOCKEVENTS
582 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
583 At present, the w90x900 has been renamed nuc900, regarding
584 the ARM series product line, you can login the following
585 link address to know more.
587 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
588 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
592 select ARCH_REQUIRE_GPIOLIB
597 select GENERIC_CLOCKEVENTS
601 Support for the NXP LPC32XX family of processors
604 bool "PXA2xx/PXA3xx-based"
607 select ARCH_REQUIRE_GPIOLIB
608 select ARM_CPU_SUSPEND if PM
614 select GENERIC_CLOCKEVENTS
618 select MULTI_IRQ_HANDLER
622 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
628 select ARCH_MAY_HAVE_PC_FDC
629 select ARCH_SPARSEMEM_ENABLE
630 select ARCH_USES_GETTIMEOFFSET
634 select HAVE_PATA_PLATFORM
636 select NEED_MACH_IO_H
637 select NEED_MACH_MEMORY_H
641 On the Acorn Risc-PC, Linux can support the internal IDE disk and
642 CD-ROM interface, serial and parallel port, and the floppy drive.
647 select ARCH_REQUIRE_GPIOLIB
648 select ARCH_SPARSEMEM_ENABLE
653 select GENERIC_CLOCKEVENTS
657 select MULTI_IRQ_HANDLER
658 select NEED_MACH_MEMORY_H
661 Support for StrongARM 11x0 based boards.
664 bool "Samsung S3C24XX SoCs"
665 select ARCH_REQUIRE_GPIOLIB
668 select CLKSRC_SAMSUNG_PWM
669 select GENERIC_CLOCKEVENTS
671 select HAVE_S3C2410_I2C if I2C
672 select HAVE_S3C2410_WATCHDOG if WATCHDOG
673 select HAVE_S3C_RTC if RTC_CLASS
674 select MULTI_IRQ_HANDLER
675 select NEED_MACH_IO_H
678 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
679 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
680 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
681 Samsung SMDK2410 development board (and derivatives).
684 bool "Samsung S3C64XX"
685 select ARCH_REQUIRE_GPIOLIB
690 select CLKSRC_SAMSUNG_PWM
691 select COMMON_CLK_SAMSUNG
693 select GENERIC_CLOCKEVENTS
695 select HAVE_S3C2410_I2C if I2C
696 select HAVE_S3C2410_WATCHDOG if WATCHDOG
700 select PM_GENERIC_DOMAINS if PM
702 select S3C_GPIO_TRACK
704 select SAMSUNG_WAKEMASK
705 select SAMSUNG_WDT_RESET
707 Samsung S3C64XX series based systems
711 select ARCH_HAS_HOLES_MEMORYMODEL
712 select ARCH_REQUIRE_GPIOLIB
714 select GENERIC_ALLOCATOR
715 select GENERIC_CLOCKEVENTS
716 select GENERIC_IRQ_CHIP
722 Support for TI's DaVinci platform.
727 select ARCH_HAS_HOLES_MEMORYMODEL
729 select ARCH_REQUIRE_GPIOLIB
732 select GENERIC_CLOCKEVENTS
733 select GENERIC_IRQ_CHIP
736 select MULTI_IRQ_HANDLER
737 select NEED_MACH_IO_H if PCCARD
738 select NEED_MACH_MEMORY_H
741 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
745 menu "Multiple platform selection"
746 depends on ARCH_MULTIPLATFORM
748 comment "CPU Core family selection"
751 bool "ARMv4 based platforms (FA526)"
752 depends on !ARCH_MULTI_V6_V7
753 select ARCH_MULTI_V4_V5
756 config ARCH_MULTI_V4T
757 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
758 depends on !ARCH_MULTI_V6_V7
759 select ARCH_MULTI_V4_V5
760 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
761 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
762 CPU_ARM925T || CPU_ARM940T)
765 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
766 depends on !ARCH_MULTI_V6_V7
767 select ARCH_MULTI_V4_V5
768 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
769 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
770 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
772 config ARCH_MULTI_V4_V5
776 bool "ARMv6 based platforms (ARM11)"
777 select ARCH_MULTI_V6_V7
781 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
783 select ARCH_MULTI_V6_V7
787 config ARCH_MULTI_V6_V7
789 select MIGHT_HAVE_CACHE_L2X0
791 config ARCH_MULTI_CPU_AUTO
792 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
798 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
803 select HAVE_ARM_ARCH_TIMER
806 # This is sorted alphabetically by mach-* pathname. However, plat-*
807 # Kconfigs may be included either alphabetically (according to the
808 # plat- suffix) or along side the corresponding mach-* source.
810 source "arch/arm/mach-mvebu/Kconfig"
812 source "arch/arm/mach-alpine/Kconfig"
814 source "arch/arm/mach-asm9260/Kconfig"
816 source "arch/arm/mach-at91/Kconfig"
818 source "arch/arm/mach-axxia/Kconfig"
820 source "arch/arm/mach-bcm/Kconfig"
822 source "arch/arm/mach-berlin/Kconfig"
824 source "arch/arm/mach-clps711x/Kconfig"
826 source "arch/arm/mach-cns3xxx/Kconfig"
828 source "arch/arm/mach-davinci/Kconfig"
830 source "arch/arm/mach-digicolor/Kconfig"
832 source "arch/arm/mach-dove/Kconfig"
834 source "arch/arm/mach-ep93xx/Kconfig"
836 source "arch/arm/mach-footbridge/Kconfig"
838 source "arch/arm/mach-gemini/Kconfig"
840 source "arch/arm/mach-highbank/Kconfig"
842 source "arch/arm/mach-hisi/Kconfig"
844 source "arch/arm/mach-integrator/Kconfig"
846 source "arch/arm/mach-iop32x/Kconfig"
848 source "arch/arm/mach-iop33x/Kconfig"
850 source "arch/arm/mach-iop13xx/Kconfig"
852 source "arch/arm/mach-ixp4xx/Kconfig"
854 source "arch/arm/mach-keystone/Kconfig"
856 source "arch/arm/mach-ks8695/Kconfig"
858 source "arch/arm/mach-meson/Kconfig"
860 source "arch/arm/mach-moxart/Kconfig"
862 source "arch/arm/mach-mv78xx0/Kconfig"
864 source "arch/arm/mach-imx/Kconfig"
866 source "arch/arm/mach-mediatek/Kconfig"
868 source "arch/arm/mach-mxs/Kconfig"
870 source "arch/arm/mach-netx/Kconfig"
872 source "arch/arm/mach-nomadik/Kconfig"
874 source "arch/arm/mach-nspire/Kconfig"
876 source "arch/arm/plat-omap/Kconfig"
878 source "arch/arm/mach-omap1/Kconfig"
880 source "arch/arm/mach-omap2/Kconfig"
882 source "arch/arm/mach-orion5x/Kconfig"
884 source "arch/arm/mach-picoxcell/Kconfig"
886 source "arch/arm/mach-pxa/Kconfig"
887 source "arch/arm/plat-pxa/Kconfig"
889 source "arch/arm/mach-mmp/Kconfig"
891 source "arch/arm/mach-qcom/Kconfig"
893 source "arch/arm/mach-realview/Kconfig"
895 source "arch/arm/mach-rockchip/Kconfig"
897 source "arch/arm/mach-sa1100/Kconfig"
899 source "arch/arm/mach-socfpga/Kconfig"
901 source "arch/arm/mach-spear/Kconfig"
903 source "arch/arm/mach-sti/Kconfig"
905 source "arch/arm/mach-s3c24xx/Kconfig"
907 source "arch/arm/mach-s3c64xx/Kconfig"
909 source "arch/arm/mach-s5pv210/Kconfig"
911 source "arch/arm/mach-exynos/Kconfig"
912 source "arch/arm/plat-samsung/Kconfig"
914 source "arch/arm/mach-shmobile/Kconfig"
916 source "arch/arm/mach-sunxi/Kconfig"
918 source "arch/arm/mach-prima2/Kconfig"
920 source "arch/arm/mach-tegra/Kconfig"
922 source "arch/arm/mach-u300/Kconfig"
924 source "arch/arm/mach-uniphier/Kconfig"
926 source "arch/arm/mach-ux500/Kconfig"
928 source "arch/arm/mach-versatile/Kconfig"
930 source "arch/arm/mach-vexpress/Kconfig"
931 source "arch/arm/plat-versatile/Kconfig"
933 source "arch/arm/mach-vt8500/Kconfig"
935 source "arch/arm/mach-w90x900/Kconfig"
937 source "arch/arm/mach-zx/Kconfig"
939 source "arch/arm/mach-zynq/Kconfig"
941 # ARMv7-M architecture
943 bool "Energy Micro efm32"
944 depends on ARM_SINGLE_ARMV7M
945 select ARCH_REQUIRE_GPIOLIB
947 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
951 bool "NXP LPC18xx/LPC43xx"
952 depends on ARM_SINGLE_ARMV7M
953 select ARCH_HAS_RESET_CONTROLLER
955 select CLKSRC_LPC32XX
958 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
959 high performance microcontrollers.
962 bool "STMicrolectronics STM32"
963 depends on ARM_SINGLE_ARMV7M
964 select ARCH_HAS_RESET_CONTROLLER
965 select ARMV7M_SYSTICK
967 select RESET_CONTROLLER
969 Support for STMicroelectronics STM32 processors.
971 # Definitions to make life easier
977 select GENERIC_CLOCKEVENTS
983 select GENERIC_IRQ_CHIP
986 config PLAT_ORION_LEGACY
993 config PLAT_VERSATILE
996 source "arch/arm/firmware/Kconfig"
998 source arch/arm/mm/Kconfig
1001 bool "Enable iWMMXt support"
1002 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1003 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1005 Enable support for iWMMXt context switching at run time if
1006 running on a CPU that supports it.
1008 config MULTI_IRQ_HANDLER
1011 Allow each machine to specify it's own IRQ handler at run time.
1014 source "arch/arm/Kconfig-nommu"
1017 config PJ4B_ERRATA_4742
1018 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1019 depends on CPU_PJ4B && MACH_ARMADA_370
1022 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1023 Event (WFE) IDLE states, a specific timing sensitivity exists between
1024 the retiring WFI/WFE instructions and the newly issued subsequent
1025 instructions. This sensitivity can result in a CPU hang scenario.
1027 The software must insert either a Data Synchronization Barrier (DSB)
1028 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1031 config ARM_ERRATA_326103
1032 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1035 Executing a SWP instruction to read-only memory does not set bit 11
1036 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1037 treat the access as a read, preventing a COW from occurring and
1038 causing the faulting task to livelock.
1040 config ARM_ERRATA_411920
1041 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1042 depends on CPU_V6 || CPU_V6K
1044 Invalidation of the Instruction Cache operation can
1045 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1046 It does not affect the MPCore. This option enables the ARM Ltd.
1047 recommended workaround.
1049 config ARM_ERRATA_430973
1050 bool "ARM errata: Stale prediction on replaced interworking branch"
1053 This option enables the workaround for the 430973 Cortex-A8
1054 r1p* erratum. If a code sequence containing an ARM/Thumb
1055 interworking branch is replaced with another code sequence at the
1056 same virtual address, whether due to self-modifying code or virtual
1057 to physical address re-mapping, Cortex-A8 does not recover from the
1058 stale interworking branch prediction. This results in Cortex-A8
1059 executing the new code sequence in the incorrect ARM or Thumb state.
1060 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1061 and also flushes the branch target cache at every context switch.
1062 Note that setting specific bits in the ACTLR register may not be
1063 available in non-secure mode.
1065 config ARM_ERRATA_458693
1066 bool "ARM errata: Processor deadlock when a false hazard is created"
1068 depends on !ARCH_MULTIPLATFORM
1070 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1071 erratum. For very specific sequences of memory operations, it is
1072 possible for a hazard condition intended for a cache line to instead
1073 be incorrectly associated with a different cache line. This false
1074 hazard might then cause a processor deadlock. The workaround enables
1075 the L1 caching of the NEON accesses and disables the PLD instruction
1076 in the ACTLR register. Note that setting specific bits in the ACTLR
1077 register may not be available in non-secure mode.
1079 config ARM_ERRATA_460075
1080 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1082 depends on !ARCH_MULTIPLATFORM
1084 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1085 erratum. Any asynchronous access to the L2 cache may encounter a
1086 situation in which recent store transactions to the L2 cache are lost
1087 and overwritten with stale memory contents from external memory. The
1088 workaround disables the write-allocate mode for the L2 cache via the
1089 ACTLR register. Note that setting specific bits in the ACTLR register
1090 may not be available in non-secure mode.
1092 config ARM_ERRATA_742230
1093 bool "ARM errata: DMB operation may be faulty"
1094 depends on CPU_V7 && SMP
1095 depends on !ARCH_MULTIPLATFORM
1097 This option enables the workaround for the 742230 Cortex-A9
1098 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1099 between two write operations may not ensure the correct visibility
1100 ordering of the two writes. This workaround sets a specific bit in
1101 the diagnostic register of the Cortex-A9 which causes the DMB
1102 instruction to behave as a DSB, ensuring the correct behaviour of
1105 config ARM_ERRATA_742231
1106 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1107 depends on CPU_V7 && SMP
1108 depends on !ARCH_MULTIPLATFORM
1110 This option enables the workaround for the 742231 Cortex-A9
1111 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1112 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1113 accessing some data located in the same cache line, may get corrupted
1114 data due to bad handling of the address hazard when the line gets
1115 replaced from one of the CPUs at the same time as another CPU is
1116 accessing it. This workaround sets specific bits in the diagnostic
1117 register of the Cortex-A9 which reduces the linefill issuing
1118 capabilities of the processor.
1120 config ARM_ERRATA_643719
1121 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1122 depends on CPU_V7 && SMP
1125 This option enables the workaround for the 643719 Cortex-A9 (prior to
1126 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1127 register returns zero when it should return one. The workaround
1128 corrects this value, ensuring cache maintenance operations which use
1129 it behave as intended and avoiding data corruption.
1131 config ARM_ERRATA_720789
1132 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1135 This option enables the workaround for the 720789 Cortex-A9 (prior to
1136 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1137 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1138 As a consequence of this erratum, some TLB entries which should be
1139 invalidated are not, resulting in an incoherency in the system page
1140 tables. The workaround changes the TLB flushing routines to invalidate
1141 entries regardless of the ASID.
1143 config ARM_ERRATA_743622
1144 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1146 depends on !ARCH_MULTIPLATFORM
1148 This option enables the workaround for the 743622 Cortex-A9
1149 (r2p*) erratum. Under very rare conditions, a faulty
1150 optimisation in the Cortex-A9 Store Buffer may lead to data
1151 corruption. This workaround sets a specific bit in the diagnostic
1152 register of the Cortex-A9 which disables the Store Buffer
1153 optimisation, preventing the defect from occurring. This has no
1154 visible impact on the overall performance or power consumption of the
1157 config ARM_ERRATA_751472
1158 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1160 depends on !ARCH_MULTIPLATFORM
1162 This option enables the workaround for the 751472 Cortex-A9 (prior
1163 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1164 completion of a following broadcasted operation if the second
1165 operation is received by a CPU before the ICIALLUIS has completed,
1166 potentially leading to corrupted entries in the cache or TLB.
1168 config ARM_ERRATA_754322
1169 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1172 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1173 r3p*) erratum. A speculative memory access may cause a page table walk
1174 which starts prior to an ASID switch but completes afterwards. This
1175 can populate the micro-TLB with a stale entry which may be hit with
1176 the new ASID. This workaround places two dsb instructions in the mm
1177 switching code so that no page table walks can cross the ASID switch.
1179 config ARM_ERRATA_754327
1180 bool "ARM errata: no automatic Store Buffer drain"
1181 depends on CPU_V7 && SMP
1183 This option enables the workaround for the 754327 Cortex-A9 (prior to
1184 r2p0) erratum. The Store Buffer does not have any automatic draining
1185 mechanism and therefore a livelock may occur if an external agent
1186 continuously polls a memory location waiting to observe an update.
1187 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1188 written polling loops from denying visibility of updates to memory.
1190 config ARM_ERRATA_364296
1191 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1194 This options enables the workaround for the 364296 ARM1136
1195 r0p2 erratum (possible cache data corruption with
1196 hit-under-miss enabled). It sets the undocumented bit 31 in
1197 the auxiliary control register and the FI bit in the control
1198 register, thus disabling hit-under-miss without putting the
1199 processor into full low interrupt latency mode. ARM11MPCore
1202 config ARM_ERRATA_764369
1203 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1204 depends on CPU_V7 && SMP
1206 This option enables the workaround for erratum 764369
1207 affecting Cortex-A9 MPCore with two or more processors (all
1208 current revisions). Under certain timing circumstances, a data
1209 cache line maintenance operation by MVA targeting an Inner
1210 Shareable memory region may fail to proceed up to either the
1211 Point of Coherency or to the Point of Unification of the
1212 system. This workaround adds a DSB instruction before the
1213 relevant cache maintenance functions and sets a specific bit
1214 in the diagnostic control register of the SCU.
1216 config ARM_ERRATA_775420
1217 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1220 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1221 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1222 operation aborts with MMU exception, it might cause the processor
1223 to deadlock. This workaround puts DSB before executing ISB if
1224 an abort may occur on cache maintenance.
1226 config ARM_ERRATA_798181
1227 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1228 depends on CPU_V7 && SMP
1230 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1231 adequately shooting down all use of the old entries. This
1232 option enables the Linux kernel workaround for this erratum
1233 which sends an IPI to the CPUs that are running the same ASID
1234 as the one being invalidated.
1236 config ARM_ERRATA_773022
1237 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1240 This option enables the workaround for the 773022 Cortex-A15
1241 (up to r0p4) erratum. In certain rare sequences of code, the
1242 loop buffer may deliver incorrect instructions. This
1243 workaround disables the loop buffer to avoid the erratum.
1247 source "arch/arm/common/Kconfig"
1254 Find out whether you have ISA slots on your motherboard. ISA is the
1255 name of a bus system, i.e. the way the CPU talks to the other stuff
1256 inside your box. Other bus systems are PCI, EISA, MicroChannel
1257 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1258 newer boards don't support it. If you have ISA, say Y, otherwise N.
1260 # Select ISA DMA controller support
1265 # Select ISA DMA interface
1270 bool "PCI support" if MIGHT_HAVE_PCI
1272 Find out whether you have a PCI motherboard. PCI is the name of a
1273 bus system, i.e. the way the CPU talks to the other stuff inside
1274 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1275 VESA. If you have PCI, say Y, otherwise N.
1281 config PCI_DOMAINS_GENERIC
1282 def_bool PCI_DOMAINS
1284 config PCI_NANOENGINE
1285 bool "BSE nanoEngine PCI support"
1286 depends on SA1100_NANOENGINE
1288 Enable PCI on the BSE nanoEngine board.
1293 config PCI_HOST_ITE8152
1295 depends on PCI && MACH_ARMCORE
1299 source "drivers/pci/Kconfig"
1300 source "drivers/pci/pcie/Kconfig"
1302 source "drivers/pcmcia/Kconfig"
1306 menu "Kernel Features"
1311 This option should be selected by machines which have an SMP-
1314 The only effect of this option is to make the SMP-related
1315 options available to the user for configuration.
1318 bool "Symmetric Multi-Processing"
1319 depends on CPU_V6K || CPU_V7
1320 depends on GENERIC_CLOCKEVENTS
1322 depends on MMU || ARM_MPU
1325 This enables support for systems with more than one CPU. If you have
1326 a system with only one CPU, say N. If you have a system with more
1327 than one CPU, say Y.
1329 If you say N here, the kernel will run on uni- and multiprocessor
1330 machines, but will use only one CPU of a multiprocessor machine. If
1331 you say Y here, the kernel will run on many, but not all,
1332 uniprocessor machines. On a uniprocessor machine, the kernel
1333 will run faster if you say N here.
1335 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1336 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1337 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1339 If you don't know what to do here, say N.
1342 bool "Allow booting SMP kernel on uniprocessor systems"
1343 depends on SMP && !XIP_KERNEL && MMU
1346 SMP kernels contain instructions which fail on non-SMP processors.
1347 Enabling this option allows the kernel to modify itself to make
1348 these instructions safe. Disabling it allows about 1K of space
1351 If you don't know what to do here, say Y.
1353 config ARM_CPU_TOPOLOGY
1354 bool "Support cpu topology definition"
1355 depends on SMP && CPU_V7
1358 Support ARM cpu topology definition. The MPIDR register defines
1359 affinity between processors which is then used to describe the cpu
1360 topology of an ARM System.
1363 bool "Multi-core scheduler support"
1364 depends on ARM_CPU_TOPOLOGY
1366 Multi-core scheduler support improves the CPU scheduler's decision
1367 making when dealing with multi-core CPU chips at a cost of slightly
1368 increased overhead in some places. If unsure say N here.
1371 bool "SMT scheduler support"
1372 depends on ARM_CPU_TOPOLOGY
1374 Improves the CPU scheduler's decision making when dealing with
1375 MultiThreading at a cost of slightly increased overhead in some
1376 places. If unsure say N here.
1381 This option enables support for the ARM system coherency unit
1383 config HAVE_ARM_ARCH_TIMER
1384 bool "Architected timer support"
1386 select ARM_ARCH_TIMER
1387 select GENERIC_CLOCKEVENTS
1389 This option enables support for the ARM architected timer
1393 select CLKSRC_OF if OF
1395 This options enables support for the ARM timer and watchdog unit
1398 bool "Multi-Cluster Power Management"
1399 depends on CPU_V7 && SMP
1401 This option provides the common power management infrastructure
1402 for (multi-)cluster based systems, such as big.LITTLE based
1405 config MCPM_QUAD_CLUSTER
1409 To avoid wasting resources unnecessarily, MCPM only supports up
1410 to 2 clusters by default.
1411 Platforms with 3 or 4 clusters that use MCPM must select this
1412 option to allow the additional clusters to be managed.
1415 bool "big.LITTLE support (Experimental)"
1416 depends on CPU_V7 && SMP
1419 This option enables support selections for the big.LITTLE
1420 system architecture.
1423 bool "big.LITTLE switcher support"
1424 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1425 select ARM_CPU_SUSPEND
1428 The big.LITTLE "switcher" provides the core functionality to
1429 transparently handle transition between a cluster of A15's
1430 and a cluster of A7's in a big.LITTLE system.
1432 config BL_SWITCHER_DUMMY_IF
1433 tristate "Simple big.LITTLE switcher user interface"
1434 depends on BL_SWITCHER && DEBUG_KERNEL
1436 This is a simple and dummy char dev interface to control
1437 the big.LITTLE switcher core code. It is meant for
1438 debugging purposes only.
1441 prompt "Memory split"
1445 Select the desired split between kernel and user memory.
1447 If you are not absolutely sure what you are doing, leave this
1451 bool "3G/1G user/kernel split"
1452 config VMSPLIT_3G_OPT
1453 bool "3G/1G user/kernel split (for full 1G low memory)"
1455 bool "2G/2G user/kernel split"
1457 bool "1G/3G user/kernel split"
1462 default PHYS_OFFSET if !MMU
1463 default 0x40000000 if VMSPLIT_1G
1464 default 0x80000000 if VMSPLIT_2G
1465 default 0xB0000000 if VMSPLIT_3G_OPT
1469 int "Maximum number of CPUs (2-32)"
1475 bool "Support for hot-pluggable CPUs"
1478 Say Y here to experiment with turning CPUs off and on. CPUs
1479 can be controlled through /sys/devices/system/cpu.
1482 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1486 Say Y here if you want Linux to communicate with system firmware
1487 implementing the PSCI specification for CPU-centric power
1488 management operations described in ARM document number ARM DEN
1489 0022A ("Power State Coordination Interface System Software on
1492 # The GPIO number here must be sorted by descending number. In case of
1493 # a multiplatform kernel, we just want the highest value required by the
1494 # selected platforms.
1497 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1499 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1500 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1501 default 416 if ARCH_SUNXI
1502 default 392 if ARCH_U8500
1503 default 352 if ARCH_VT8500
1504 default 288 if ARCH_ROCKCHIP
1505 default 264 if MACH_H4700
1508 Maximum number of GPIOs in the system.
1510 If unsure, leave the default value.
1512 source kernel/Kconfig.preempt
1516 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1517 ARCH_S5PV210 || ARCH_EXYNOS4
1518 default 128 if SOC_AT91RM9200
1522 depends on HZ_FIXED = 0
1523 prompt "Timer frequency"
1547 default HZ_FIXED if HZ_FIXED != 0
1548 default 100 if HZ_100
1549 default 200 if HZ_200
1550 default 250 if HZ_250
1551 default 300 if HZ_300
1552 default 500 if HZ_500
1556 def_bool HIGH_RES_TIMERS
1558 config THUMB2_KERNEL
1559 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1560 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1561 default y if CPU_THUMBONLY
1563 select ARM_ASM_UNIFIED
1566 By enabling this option, the kernel will be compiled in
1567 Thumb-2 mode. A compiler/assembler that understand the unified
1568 ARM-Thumb syntax is needed.
1572 config THUMB2_AVOID_R_ARM_THM_JUMP11
1573 bool "Work around buggy Thumb-2 short branch relocations in gas"
1574 depends on THUMB2_KERNEL && MODULES
1577 Various binutils versions can resolve Thumb-2 branches to
1578 locally-defined, preemptible global symbols as short-range "b.n"
1579 branch instructions.
1581 This is a problem, because there's no guarantee the final
1582 destination of the symbol, or any candidate locations for a
1583 trampoline, are within range of the branch. For this reason, the
1584 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1585 relocation in modules at all, and it makes little sense to add
1588 The symptom is that the kernel fails with an "unsupported
1589 relocation" error when loading some modules.
1591 Until fixed tools are available, passing
1592 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1593 code which hits this problem, at the cost of a bit of extra runtime
1594 stack usage in some cases.
1596 The problem is described in more detail at:
1597 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1599 Only Thumb-2 kernels are affected.
1601 Unless you are sure your tools don't have this problem, say Y.
1603 config ARM_ASM_UNIFIED
1607 bool "Use the ARM EABI to compile the kernel"
1609 This option allows for the kernel to be compiled using the latest
1610 ARM ABI (aka EABI). This is only useful if you are using a user
1611 space environment that is also compiled with EABI.
1613 Since there are major incompatibilities between the legacy ABI and
1614 EABI, especially with regard to structure member alignment, this
1615 option also changes the kernel syscall calling convention to
1616 disambiguate both ABIs and allow for backward compatibility support
1617 (selected with CONFIG_OABI_COMPAT).
1619 To use this you need GCC version 4.0.0 or later.
1622 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1623 depends on AEABI && !THUMB2_KERNEL
1625 This option preserves the old syscall interface along with the
1626 new (ARM EABI) one. It also provides a compatibility layer to
1627 intercept syscalls that have structure arguments which layout
1628 in memory differs between the legacy ABI and the new ARM EABI
1629 (only for non "thumb" binaries). This option adds a tiny
1630 overhead to all syscalls and produces a slightly larger kernel.
1632 The seccomp filter system will not be available when this is
1633 selected, since there is no way yet to sensibly distinguish
1634 between calling conventions during filtering.
1636 If you know you'll be using only pure EABI user space then you
1637 can say N here. If this option is not selected and you attempt
1638 to execute a legacy ABI binary then the result will be
1639 UNPREDICTABLE (in fact it can be predicted that it won't work
1640 at all). If in doubt say N.
1642 config ARCH_HAS_HOLES_MEMORYMODEL
1645 config ARCH_SPARSEMEM_ENABLE
1648 config ARCH_SPARSEMEM_DEFAULT
1649 def_bool ARCH_SPARSEMEM_ENABLE
1651 config ARCH_SELECT_MEMORY_MODEL
1652 def_bool ARCH_SPARSEMEM_ENABLE
1654 config HAVE_ARCH_PFN_VALID
1655 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1657 config HAVE_GENERIC_RCU_GUP
1662 bool "High Memory Support"
1665 The address space of ARM processors is only 4 Gigabytes large
1666 and it has to accommodate user address space, kernel address
1667 space as well as some memory mapped IO. That means that, if you
1668 have a large amount of physical memory and/or IO, not all of the
1669 memory can be "permanently mapped" by the kernel. The physical
1670 memory that is not permanently mapped is called "high memory".
1672 Depending on the selected kernel/user memory split, minimum
1673 vmalloc space and actual amount of RAM, you may not need this
1674 option which should result in a slightly faster kernel.
1679 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1683 The VM uses one page of physical memory for each page table.
1684 For systems with a lot of processes, this can use a lot of
1685 precious low memory, eventually leading to low memory being
1686 consumed by page tables. Setting this option will allow
1687 user-space 2nd level page tables to reside in high memory.
1689 config CPU_SW_DOMAIN_PAN
1690 bool "Enable use of CPU domains to implement privileged no-access"
1691 depends on MMU && !ARM_LPAE
1694 Increase kernel security by ensuring that normal kernel accesses
1695 are unable to access userspace addresses. This can help prevent
1696 use-after-free bugs becoming an exploitable privilege escalation
1697 by ensuring that magic values (such as LIST_POISON) will always
1698 fault when dereferenced.
1700 CPUs with low-vector mappings use a best-efforts implementation.
1701 Their lower 1MB needs to remain accessible for the vectors, but
1702 the remainder of userspace will become appropriately inaccessible.
1704 config HW_PERF_EVENTS
1708 config SYS_SUPPORTS_HUGETLBFS
1712 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1716 config ARCH_WANT_GENERAL_HUGETLB
1719 config ARM_MODULE_PLTS
1720 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1723 Allocate PLTs when loading modules so that jumps and calls whose
1724 targets are too far away for their relative offsets to be encoded
1725 in the instructions themselves can be bounced via veneers in the
1726 module's PLT. This allows modules to be allocated in the generic
1727 vmalloc area after the dedicated module memory area has been
1728 exhausted. The modules will use slightly more memory, but after
1729 rounding up to page size, the actual memory footprint is usually
1732 Say y if you are getting out of memory errors while loading modules
1736 config FORCE_MAX_ZONEORDER
1737 int "Maximum zone order"
1738 default "12" if SOC_AM33XX
1739 default "9" if SA1111 || ARCH_EFM32
1742 The kernel memory allocator divides physically contiguous memory
1743 blocks into "zones", where each zone is a power of two number of
1744 pages. This option selects the largest power of two that the kernel
1745 keeps in the memory allocator. If you need to allocate very large
1746 blocks of physically contiguous memory, then you may need to
1747 increase this value.
1749 This config option is actually maximum order plus one. For example,
1750 a value of 11 means that the largest free memory block is 2^10 pages.
1752 config ALIGNMENT_TRAP
1754 depends on CPU_CP15_MMU
1755 default y if !ARCH_EBSA110
1756 select HAVE_PROC_CPU if PROC_FS
1758 ARM processors cannot fetch/store information which is not
1759 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1760 address divisible by 4. On 32-bit ARM processors, these non-aligned
1761 fetch/store instructions will be emulated in software if you say
1762 here, which has a severe performance impact. This is necessary for
1763 correct operation of some network protocols. With an IP-only
1764 configuration it is safe to say N, otherwise say Y.
1766 config UACCESS_WITH_MEMCPY
1767 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1769 default y if CPU_FEROCEON
1771 Implement faster copy_to_user and clear_user methods for CPU
1772 cores where a 8-word STM instruction give significantly higher
1773 memory write throughput than a sequence of individual 32bit stores.
1775 A possible side effect is a slight increase in scheduling latency
1776 between threads sharing the same address space if they invoke
1777 such copy operations with large buffers.
1779 However, if the CPU data cache is using a write-allocate mode,
1780 this option is unlikely to provide any performance gain.
1784 prompt "Enable seccomp to safely compute untrusted bytecode"
1786 This kernel feature is useful for number crunching applications
1787 that may need to compute untrusted bytecode during their
1788 execution. By using pipes or other transports made available to
1789 the process as file descriptors supporting the read/write
1790 syscalls, it's possible to isolate those applications in
1791 their own address space using seccomp. Once seccomp is
1792 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1793 and the task is only allowed to execute a few safe syscalls
1794 defined by each seccomp mode.
1807 bool "Xen guest support on ARM"
1808 depends on ARM && AEABI && OF
1809 depends on CPU_V7 && !CPU_V6
1810 depends on !GENERIC_ATOMIC64
1812 select ARCH_DMA_ADDR_T_64BIT
1816 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1823 bool "Flattened Device Tree support"
1826 select OF_EARLY_FLATTREE
1827 select OF_RESERVED_MEM
1829 Include support for flattened device tree machine descriptions.
1832 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1835 This is the traditional way of passing data to the kernel at boot
1836 time. If you are solely relying on the flattened device tree (or
1837 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1838 to remove ATAGS support from your kernel binary. If unsure,
1841 config DEPRECATED_PARAM_STRUCT
1842 bool "Provide old way to pass kernel parameters"
1845 This was deprecated in 2001 and announced to live on for 5 years.
1846 Some old boot loaders still use this way.
1848 # Compressed boot loader in ROM. Yes, we really want to ask about
1849 # TEXT and BSS so we preserve their values in the config files.
1850 config ZBOOT_ROM_TEXT
1851 hex "Compressed ROM boot loader base address"
1854 The physical address at which the ROM-able zImage is to be
1855 placed in the target. Platforms which normally make use of
1856 ROM-able zImage formats normally set this to a suitable
1857 value in their defconfig file.
1859 If ZBOOT_ROM is not enabled, this has no effect.
1861 config ZBOOT_ROM_BSS
1862 hex "Compressed ROM boot loader BSS address"
1865 The base address of an area of read/write memory in the target
1866 for the ROM-able zImage which must be available while the
1867 decompressor is running. It must be large enough to hold the
1868 entire decompressed kernel plus an additional 128 KiB.
1869 Platforms which normally make use of ROM-able zImage formats
1870 normally set this to a suitable value in their defconfig file.
1872 If ZBOOT_ROM is not enabled, this has no effect.
1875 bool "Compressed boot loader in ROM/flash"
1876 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1877 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1879 Say Y here if you intend to execute your compressed kernel image
1880 (zImage) directly from ROM or flash. If unsure, say N.
1882 config ARM_APPENDED_DTB
1883 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1886 With this option, the boot code will look for a device tree binary
1887 (DTB) appended to zImage
1888 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1890 This is meant as a backward compatibility convenience for those
1891 systems with a bootloader that can't be upgraded to accommodate
1892 the documented boot protocol using a device tree.
1894 Beware that there is very little in terms of protection against
1895 this option being confused by leftover garbage in memory that might
1896 look like a DTB header after a reboot if no actual DTB is appended
1897 to zImage. Do not leave this option active in a production kernel
1898 if you don't intend to always append a DTB. Proper passing of the
1899 location into r2 of a bootloader provided DTB is always preferable
1902 config ARM_ATAG_DTB_COMPAT
1903 bool "Supplement the appended DTB with traditional ATAG information"
1904 depends on ARM_APPENDED_DTB
1906 Some old bootloaders can't be updated to a DTB capable one, yet
1907 they provide ATAGs with memory configuration, the ramdisk address,
1908 the kernel cmdline string, etc. Such information is dynamically
1909 provided by the bootloader and can't always be stored in a static
1910 DTB. To allow a device tree enabled kernel to be used with such
1911 bootloaders, this option allows zImage to extract the information
1912 from the ATAG list and store it at run time into the appended DTB.
1915 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1916 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1918 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1919 bool "Use bootloader kernel arguments if available"
1921 Uses the command-line options passed by the boot loader instead of
1922 the device tree bootargs property. If the boot loader doesn't provide
1923 any, the device tree bootargs property will be used.
1925 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1926 bool "Extend with bootloader kernel arguments"
1928 The command-line arguments provided by the boot loader will be
1929 appended to the the device tree bootargs property.
1934 string "Default kernel command string"
1937 On some architectures (EBSA110 and CATS), there is currently no way
1938 for the boot loader to pass arguments to the kernel. For these
1939 architectures, you should supply some command-line options at build
1940 time by entering them here. As a minimum, you should specify the
1941 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1944 prompt "Kernel command line type" if CMDLINE != ""
1945 default CMDLINE_FROM_BOOTLOADER
1948 config CMDLINE_FROM_BOOTLOADER
1949 bool "Use bootloader kernel arguments if available"
1951 Uses the command-line options passed by the boot loader. If
1952 the boot loader doesn't provide any, the default kernel command
1953 string provided in CMDLINE will be used.
1955 config CMDLINE_EXTEND
1956 bool "Extend bootloader kernel arguments"
1958 The command-line arguments provided by the boot loader will be
1959 appended to the default kernel command string.
1961 config CMDLINE_FORCE
1962 bool "Always use the default kernel command string"
1964 Always use the default kernel command string, even if the boot
1965 loader passes other arguments to the kernel.
1966 This is useful if you cannot or don't want to change the
1967 command-line options your boot loader passes to the kernel.
1971 bool "Kernel Execute-In-Place from ROM"
1972 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1974 Execute-In-Place allows the kernel to run from non-volatile storage
1975 directly addressable by the CPU, such as NOR flash. This saves RAM
1976 space since the text section of the kernel is not loaded from flash
1977 to RAM. Read-write sections, such as the data section and stack,
1978 are still copied to RAM. The XIP kernel is not compressed since
1979 it has to run directly from flash, so it will take more space to
1980 store it. The flash address used to link the kernel object files,
1981 and for storing it, is configuration dependent. Therefore, if you
1982 say Y here, you must know the proper physical address where to
1983 store the kernel image depending on your own flash memory usage.
1985 Also note that the make target becomes "make xipImage" rather than
1986 "make zImage" or "make Image". The final kernel binary to put in
1987 ROM memory will be arch/arm/boot/xipImage.
1991 config XIP_PHYS_ADDR
1992 hex "XIP Kernel Physical Location"
1993 depends on XIP_KERNEL
1994 default "0x00080000"
1996 This is the physical address in your flash memory the kernel will
1997 be linked for and stored to. This address is dependent on your
2001 bool "Kexec system call (EXPERIMENTAL)"
2002 depends on (!SMP || PM_SLEEP_SMP)
2006 kexec is a system call that implements the ability to shutdown your
2007 current kernel, and to start another kernel. It is like a reboot
2008 but it is independent of the system firmware. And like a reboot
2009 you can start any kernel with it, not just Linux.
2011 It is an ongoing process to be certain the hardware in a machine
2012 is properly shutdown, so do not be surprised if this code does not
2013 initially work for you.
2016 bool "Export atags in procfs"
2017 depends on ATAGS && KEXEC
2020 Should the atags used to boot the kernel be exported in an "atags"
2021 file in procfs. Useful with kexec.
2024 bool "Build kdump crash kernel (EXPERIMENTAL)"
2026 Generate crash dump after being started by kexec. This should
2027 be normally only set in special crash dump kernels which are
2028 loaded in the main kernel with kexec-tools into a specially
2029 reserved region and then later executed after a crash by
2030 kdump/kexec. The crash dump kernel must be compiled to a
2031 memory address not used by the main kernel
2033 For more details see Documentation/kdump/kdump.txt
2035 config AUTO_ZRELADDR
2036 bool "Auto calculation of the decompressed kernel image address"
2038 ZRELADDR is the physical address where the decompressed kernel
2039 image will be placed. If AUTO_ZRELADDR is selected, the address
2040 will be determined at run-time by masking the current IP with
2041 0xf8000000. This assumes the zImage being placed in the first 128MB
2042 from start of memory.
2046 menu "CPU Power Management"
2048 source "drivers/cpufreq/Kconfig"
2050 source "drivers/cpuidle/Kconfig"
2054 menu "Floating point emulation"
2056 comment "At least one emulation must be selected"
2059 bool "NWFPE math emulation"
2060 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2062 Say Y to include the NWFPE floating point emulator in the kernel.
2063 This is necessary to run most binaries. Linux does not currently
2064 support floating point hardware so you need to say Y here even if
2065 your machine has an FPA or floating point co-processor podule.
2067 You may say N here if you are going to load the Acorn FPEmulator
2068 early in the bootup.
2071 bool "Support extended precision"
2072 depends on FPE_NWFPE
2074 Say Y to include 80-bit support in the kernel floating-point
2075 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2076 Note that gcc does not generate 80-bit operations by default,
2077 so in most cases this option only enlarges the size of the
2078 floating point emulator without any good reason.
2080 You almost surely want to say N here.
2083 bool "FastFPE math emulation (EXPERIMENTAL)"
2084 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2086 Say Y here to include the FAST floating point emulator in the kernel.
2087 This is an experimental much faster emulator which now also has full
2088 precision for the mantissa. It does not support any exceptions.
2089 It is very simple, and approximately 3-6 times faster than NWFPE.
2091 It should be sufficient for most programs. It may be not suitable
2092 for scientific calculations, but you have to check this for yourself.
2093 If you do not feel you need a faster FP emulation you should better
2097 bool "VFP-format floating point maths"
2098 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2100 Say Y to include VFP support code in the kernel. This is needed
2101 if your hardware includes a VFP unit.
2103 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2104 release notes and additional status information.
2106 Say N if your target does not have VFP hardware.
2114 bool "Advanced SIMD (NEON) Extension support"
2115 depends on VFPv3 && CPU_V7
2117 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2120 config KERNEL_MODE_NEON
2121 bool "Support for NEON in kernel mode"
2122 depends on NEON && AEABI
2124 Say Y to include support for NEON in kernel mode.
2128 menu "Userspace binary formats"
2130 source "fs/Kconfig.binfmt"
2134 menu "Power management options"
2136 source "kernel/power/Kconfig"
2138 config ARCH_SUSPEND_POSSIBLE
2139 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2140 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2143 config ARM_CPU_SUSPEND
2146 config ARCH_HIBERNATION_POSSIBLE
2149 default y if ARCH_SUSPEND_POSSIBLE
2153 source "net/Kconfig"
2155 source "drivers/Kconfig"
2157 source "drivers/firmware/Kconfig"
2161 source "arch/arm/Kconfig.debug"
2163 source "security/Kconfig"
2165 source "crypto/Kconfig"
2167 source "arch/arm/crypto/Kconfig"
2170 source "lib/Kconfig"
2172 source "arch/arm/kvm/Kconfig"