4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_KERNEL_THREAD
16 select GENERIC_KERNEL_EXECVE
17 select GENERIC_PCI_IOMAP
18 select GENERIC_SMP_IDLE_THREAD
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_TRACEHOOK
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_CONTIGUOUS if MMU
32 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36 select HAVE_GENERIC_DMA_COHERENT
37 select HAVE_GENERIC_HARDIRQS
38 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_KERNEL_GZIP
42 select HAVE_KERNEL_LZMA
43 select HAVE_KERNEL_LZO
45 select HAVE_KPROBES if !XIP_KERNEL
46 select HAVE_KRETPROBES if (HAVE_KPROBES)
48 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
49 select HAVE_PERF_EVENTS
50 select HAVE_REGS_AND_STACK_ACCESS_API
51 select HAVE_SYSCALL_TRACEPOINTS
54 select PERF_USE_VMALLOC
56 select SYS_SUPPORTS_APM_EMULATION
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select MODULES_USE_ELF_REL
60 The ARM series is a line of low-power-consumption RISC chip designs
61 licensed by ARM Ltd and targeted at embedded applications and
62 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
63 manufactured, but legacy ARM-based PC hardware remains popular in
64 Europe. There is an ARM Linux project with a web page at
65 <http://www.arm.linux.org.uk/>.
67 config ARM_HAS_SG_CHAIN
70 config NEED_SG_DMA_LENGTH
73 config ARM_DMA_USE_IOMMU
75 select ARM_HAS_SG_CHAIN
76 select NEED_SG_DMA_LENGTH
84 config SYS_SUPPORTS_APM_EMULATION
92 select GENERIC_ALLOCATOR
103 The Extended Industry Standard Architecture (EISA) bus was
104 developed as an open alternative to the IBM MicroChannel bus.
106 The EISA bus provided some of the features of the IBM MicroChannel
107 bus while maintaining backward compatibility with cards made for
108 the older ISA bus. The EISA bus saw limited use between 1988 and
109 1995 when it was made obsolete by the PCI bus.
111 Say Y here if you are building a kernel for an EISA-based machine.
118 config STACKTRACE_SUPPORT
122 config HAVE_LATENCYTOP_SUPPORT
127 config LOCKDEP_SUPPORT
131 config TRACE_IRQFLAGS_SUPPORT
135 config RWSEM_GENERIC_SPINLOCK
139 config RWSEM_XCHGADD_ALGORITHM
142 config ARCH_HAS_ILOG2_U32
145 config ARCH_HAS_ILOG2_U64
148 config ARCH_HAS_CPUFREQ
151 Internal node to signify that the ARCH has CPUFREQ support
152 and that the relevant menu configurations are displayed for
155 config GENERIC_HWEIGHT
159 config GENERIC_CALIBRATE_DELAY
163 config ARCH_MAY_HAVE_PC_FDC
169 config NEED_DMA_MAP_STATE
172 config ARCH_HAS_DMA_SET_COHERENT_MASK
175 config GENERIC_ISA_DMA
181 config NEED_RET_TO_USER
189 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
190 default DRAM_BASE if REMAP_VECTORS_TO_RAM
193 The base address of exception vectors.
195 config ARM_PATCH_PHYS_VIRT
196 bool "Patch physical to virtual translations at runtime" if EMBEDDED
198 depends on !XIP_KERNEL && MMU
199 depends on !ARCH_REALVIEW || !SPARSEMEM
201 Patch phys-to-virt and virt-to-phys translation functions at
202 boot and module load time according to the position of the
203 kernel in system memory.
205 This can only be used with non-XIP MMU kernels where the base
206 of physical memory is at a 16MB boundary.
208 Only disable this option if you know that you do not require
209 this feature (eg, building a kernel for a single machine) and
210 you need to shrink the kernel to the minimal size.
212 config NEED_MACH_GPIO_H
215 Select this when mach/gpio.h is required to provide special
216 definitions for this platform. The need for mach/gpio.h should
217 be avoided when possible.
219 config NEED_MACH_IO_H
222 Select this when mach/io.h is required to provide special
223 definitions for this platform. The need for mach/io.h should
224 be avoided when possible.
226 config NEED_MACH_MEMORY_H
229 Select this when mach/memory.h is required to provide special
230 definitions for this platform. The need for mach/memory.h should
231 be avoided when possible.
234 hex "Physical address of main memory" if MMU
235 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
236 default DRAM_BASE if !MMU
238 Please provide the physical address corresponding to the
239 location of main memory in your system.
245 source "init/Kconfig"
247 source "kernel/Kconfig.freezer"
252 bool "MMU-based Paged Memory Management Support"
255 Select if you want MMU-based virtualised addressing space
256 support by paged memory management. If unsure, say 'Y'.
259 # The "ARM system type" choice list is ordered alphabetically by option
260 # text. Please add new entries in the option alphabetic order.
263 prompt "ARM system type"
264 default ARCH_MULTIPLATFORM
266 config ARCH_MULTIPLATFORM
267 bool "Allow multiple platforms to be selected"
269 select ARM_PATCH_PHYS_VIRT
272 select MULTI_IRQ_HANDLER
276 config ARCH_INTEGRATOR
277 bool "ARM Ltd. Integrator family"
278 select ARCH_HAS_CPUFREQ
281 select COMMON_CLK_VERSATILE
282 select GENERIC_CLOCKEVENTS
285 select MULTI_IRQ_HANDLER
286 select NEED_MACH_MEMORY_H
287 select PLAT_VERSATILE
289 select VERSATILE_FPGA_IRQ
291 Support for ARM's Integrator platform.
294 bool "ARM Ltd. RealView family"
295 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select ARM_TIMER_SP804
299 select COMMON_CLK_VERSATILE
300 select GENERIC_CLOCKEVENTS
301 select GPIO_PL061 if GPIOLIB
303 select NEED_MACH_MEMORY_H
304 select PLAT_VERSATILE
305 select PLAT_VERSATILE_CLCD
307 This enables support for ARM Ltd RealView boards.
309 config ARCH_VERSATILE
310 bool "ARM Ltd. Versatile family"
311 select ARCH_WANT_OPTIONAL_GPIOLIB
313 select ARM_TIMER_SP804
316 select GENERIC_CLOCKEVENTS
317 select HAVE_MACH_CLKDEV
319 select PLAT_VERSATILE
320 select PLAT_VERSATILE_CLCD
321 select PLAT_VERSATILE_CLOCK
322 select VERSATILE_FPGA_IRQ
324 This enables support for ARM Ltd Versatile board.
328 select ARCH_REQUIRE_GPIOLIB
332 select NEED_MACH_GPIO_H
333 select NEED_MACH_IO_H if PCCARD
335 select PINCTRL_AT91 if USE_OF
337 This enables support for systems based on Atmel
338 AT91RM9200 and AT91SAM9* processors.
341 bool "Broadcom BCM2835 family"
342 select ARCH_WANT_OPTIONAL_GPIOLIB
344 select ARM_ERRATA_411920
345 select ARM_TIMER_SP804
349 select GENERIC_CLOCKEVENTS
350 select MULTI_IRQ_HANDLER
354 This enables support for the Broadcom BCM2835 SoC. This SoC is
355 use in the Raspberry Pi, and Roku 2 devices.
358 bool "Cavium Networks CNS3XXX family"
361 select GENERIC_CLOCKEVENTS
362 select MIGHT_HAVE_CACHE_L2X0
363 select MIGHT_HAVE_PCI
364 select PCI_DOMAINS if PCI
366 Support for Cavium Networks CNS3XXX platform.
369 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
370 select ARCH_REQUIRE_GPIOLIB
374 select GENERIC_CLOCKEVENTS
375 select NEED_MACH_MEMORY_H
377 Support for Cirrus Logic 711x/721x/731x based boards.
380 bool "Cortina Systems Gemini"
381 select ARCH_REQUIRE_GPIOLIB
382 select ARCH_USES_GETTIMEOFFSET
385 Support for the Cortina Systems Gemini family SoCs
389 select ARCH_REQUIRE_GPIOLIB
391 select GENERIC_CLOCKEVENTS
392 select GENERIC_IRQ_CHIP
393 select MIGHT_HAVE_CACHE_L2X0
399 Support for CSR SiRFprimaII/Marco/Polo platforms
403 select ARCH_USES_GETTIMEOFFSET
406 select NEED_MACH_IO_H
407 select NEED_MACH_MEMORY_H
410 This is an evaluation board for the StrongARM processor available
411 from Digital. It has limited hardware on-board, including an
412 Ethernet interface, two PCMCIA sockets, two serial ports and a
417 select ARCH_HAS_HOLES_MEMORYMODEL
418 select ARCH_REQUIRE_GPIOLIB
419 select ARCH_USES_GETTIMEOFFSET
424 select NEED_MACH_MEMORY_H
426 This enables support for the Cirrus EP93xx series of CPUs.
428 config ARCH_FOOTBRIDGE
432 select GENERIC_CLOCKEVENTS
434 select NEED_MACH_IO_H if !MMU
435 select NEED_MACH_MEMORY_H
437 Support for systems based on the DC21285 companion chip
438 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
441 bool "Freescale MXS-based"
442 select ARCH_REQUIRE_GPIOLIB
446 select GENERIC_CLOCKEVENTS
447 select HAVE_CLK_PREPARE
448 select MULTI_IRQ_HANDLER
453 Support for Freescale MXS-based family of processors
456 bool "Hilscher NetX based"
460 select GENERIC_CLOCKEVENTS
462 This enables support for systems based on the Hilscher NetX Soc
465 bool "Hynix HMS720x-based"
466 select ARCH_USES_GETTIMEOFFSET
470 This enables support for systems based on the Hynix HMS720x
475 select ARCH_SUPPORTS_MSI
477 select NEED_MACH_MEMORY_H
478 select NEED_RET_TO_USER
483 Support for Intel's IOP13XX (XScale) family of processors.
488 select ARCH_REQUIRE_GPIOLIB
490 select NEED_MACH_GPIO_H
491 select NEED_RET_TO_USER
495 Support for Intel's 80219 and IOP32X (XScale) family of
501 select ARCH_REQUIRE_GPIOLIB
503 select NEED_MACH_GPIO_H
504 select NEED_RET_TO_USER
508 Support for Intel's IOP33X (XScale) family of processors.
513 select ARCH_HAS_DMA_SET_COHERENT_MASK
514 select ARCH_REQUIRE_GPIOLIB
517 select DMABOUNCE if PCI
518 select GENERIC_CLOCKEVENTS
519 select MIGHT_HAVE_PCI
520 select NEED_MACH_IO_H
522 Support for Intel's IXP4XX (XScale) family of processors.
526 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
529 select MIGHT_HAVE_PCI
530 select PLAT_ORION_LEGACY
531 select USB_ARCH_HAS_EHCI
533 Support for the Marvell Dove SoC 88AP510
536 bool "Marvell Kirkwood"
537 select ARCH_REQUIRE_GPIOLIB
539 select GENERIC_CLOCKEVENTS
541 select PLAT_ORION_LEGACY
543 Support for the following Marvell Kirkwood series SoCs:
544 88F6180, 88F6192 and 88F6281.
547 bool "Marvell MV78xx0"
548 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
552 select PLAT_ORION_LEGACY
554 Support for the following Marvell MV78xx0 series SoCs:
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
564 select PLAT_ORION_LEGACY
566 Support for the following Marvell Orion 5x series SoCs:
567 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
568 Orion-2 (5281), Orion-1-90 (6183).
571 bool "Marvell PXA168/910/MMP2"
573 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_ALLOCATOR
576 select GENERIC_CLOCKEVENTS
579 select NEED_MACH_GPIO_H
583 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
586 bool "Micrel/Kendin KS8695"
587 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_CLOCKEVENTS
591 select NEED_MACH_MEMORY_H
593 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
594 System-on-Chip devices.
597 bool "Nuvoton W90X900 CPU"
598 select ARCH_REQUIRE_GPIOLIB
602 select GENERIC_CLOCKEVENTS
604 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
605 At present, the w90x900 has been renamed nuc900, regarding
606 the ARM series product line, you can login the following
607 link address to know more.
609 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
610 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
614 select ARCH_REQUIRE_GPIOLIB
619 select GENERIC_CLOCKEVENTS
622 select USB_ARCH_HAS_OHCI
625 Support for the NXP LPC32XX family of processors
629 select ARCH_HAS_CPUFREQ
633 select GENERIC_CLOCKEVENTS
637 select MIGHT_HAVE_CACHE_L2X0
640 This enables support for NVIDIA Tegra based systems (Tegra APX,
641 Tegra 6xx and Tegra 2 series).
644 bool "PXA2xx/PXA3xx-based"
646 select ARCH_HAS_CPUFREQ
648 select ARCH_REQUIRE_GPIOLIB
649 select ARM_CPU_SUSPEND if PM
653 select GENERIC_CLOCKEVENTS
656 select MULTI_IRQ_HANDLER
657 select NEED_MACH_GPIO_H
661 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
665 select ARCH_REQUIRE_GPIOLIB
667 select GENERIC_CLOCKEVENTS
670 Support for Qualcomm MSM/QSD based systems. This runs on the
671 apps processor of the MSM/QSD and depends on a shared memory
672 interface to the modem processor which runs the baseband
673 stack and controls some vital subsystems
674 (clock and power control, etc).
677 bool "Renesas SH-Mobile / R-Mobile"
679 select GENERIC_CLOCKEVENTS
681 select HAVE_MACH_CLKDEV
683 select MIGHT_HAVE_CACHE_L2X0
684 select MULTI_IRQ_HANDLER
685 select NEED_MACH_MEMORY_H
687 select PM_GENERIC_DOMAINS if PM
690 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
695 select ARCH_MAY_HAVE_PC_FDC
696 select ARCH_SPARSEMEM_ENABLE
697 select ARCH_USES_GETTIMEOFFSET
700 select HAVE_PATA_PLATFORM
702 select NEED_MACH_IO_H
703 select NEED_MACH_MEMORY_H
706 On the Acorn Risc-PC, Linux can support the internal IDE disk and
707 CD-ROM interface, serial and parallel port, and the floppy drive.
711 select ARCH_HAS_CPUFREQ
713 select ARCH_REQUIRE_GPIOLIB
714 select ARCH_SPARSEMEM_ENABLE
719 select GENERIC_CLOCKEVENTS
722 select NEED_MACH_GPIO_H
723 select NEED_MACH_MEMORY_H
726 Support for StrongARM 11x0 based boards.
729 bool "Samsung S3C24XX SoCs"
730 select ARCH_HAS_CPUFREQ
731 select ARCH_USES_GETTIMEOFFSET
735 select HAVE_S3C2410_I2C if I2C
736 select HAVE_S3C2410_WATCHDOG if WATCHDOG
737 select HAVE_S3C_RTC if RTC_CLASS
738 select NEED_MACH_GPIO_H
739 select NEED_MACH_IO_H
741 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
742 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
743 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
744 Samsung SMDK2410 development board (and derivatives).
747 bool "Samsung S3C64XX"
748 select ARCH_HAS_CPUFREQ
749 select ARCH_REQUIRE_GPIOLIB
750 select ARCH_USES_GETTIMEOFFSET
755 select HAVE_S3C2410_I2C if I2C
756 select HAVE_S3C2410_WATCHDOG if WATCHDOG
758 select NEED_MACH_GPIO_H
762 select S3C_GPIO_TRACK
763 select SAMSUNG_CLKSRC
764 select SAMSUNG_GPIOLIB_4BIT
765 select SAMSUNG_IRQ_VIC_TIMER
766 select USB_ARCH_HAS_OHCI
768 Samsung S3C64XX series based systems
771 bool "Samsung S5P6440 S5P6450"
775 select GENERIC_CLOCKEVENTS
778 select HAVE_S3C2410_I2C if I2C
779 select HAVE_S3C2410_WATCHDOG if WATCHDOG
780 select HAVE_S3C_RTC if RTC_CLASS
781 select NEED_MACH_GPIO_H
783 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
787 bool "Samsung S5PC100"
788 select ARCH_USES_GETTIMEOFFSET
793 select HAVE_S3C2410_I2C if I2C
794 select HAVE_S3C2410_WATCHDOG if WATCHDOG
795 select HAVE_S3C_RTC if RTC_CLASS
796 select NEED_MACH_GPIO_H
798 Samsung S5PC100 series based systems
801 bool "Samsung S5PV210/S5PC110"
802 select ARCH_HAS_CPUFREQ
803 select ARCH_HAS_HOLES_MEMORYMODEL
804 select ARCH_SPARSEMEM_ENABLE
808 select GENERIC_CLOCKEVENTS
811 select HAVE_S3C2410_I2C if I2C
812 select HAVE_S3C2410_WATCHDOG if WATCHDOG
813 select HAVE_S3C_RTC if RTC_CLASS
814 select NEED_MACH_GPIO_H
815 select NEED_MACH_MEMORY_H
817 Samsung S5PV210/S5PC110 series based systems
820 bool "Samsung EXYNOS"
821 select ARCH_HAS_CPUFREQ
822 select ARCH_HAS_HOLES_MEMORYMODEL
823 select ARCH_SPARSEMEM_ENABLE
826 select GENERIC_CLOCKEVENTS
829 select HAVE_S3C2410_I2C if I2C
830 select HAVE_S3C2410_WATCHDOG if WATCHDOG
831 select HAVE_S3C_RTC if RTC_CLASS
832 select NEED_MACH_GPIO_H
833 select NEED_MACH_MEMORY_H
835 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
839 select ARCH_USES_GETTIMEOFFSET
843 select NEED_MACH_MEMORY_H
847 Support for the StrongARM based Digital DNARD machine, also known
848 as "Shark" (<http://www.shark-linux.de/shark.html>).
851 bool "ST-Ericsson U300 Series"
853 select ARCH_REQUIRE_GPIOLIB
855 select ARM_PATCH_PHYS_VIRT
861 select GENERIC_CLOCKEVENTS
866 Support for ST-Ericsson U300 series mobile platforms.
869 bool "ST-Ericsson U8500 Series"
871 select ARCH_HAS_CPUFREQ
872 select ARCH_REQUIRE_GPIOLIB
876 select GENERIC_CLOCKEVENTS
878 select MIGHT_HAVE_CACHE_L2X0
881 Support for ST-Ericsson's Ux500 architecture
884 bool "STMicroelectronics Nomadik"
885 select ARCH_REQUIRE_GPIOLIB
890 select GENERIC_CLOCKEVENTS
891 select MIGHT_HAVE_CACHE_L2X0
893 select PINCTRL_STN8815
896 Support for the Nomadik platform by ST-Ericsson
900 select ARCH_REQUIRE_GPIOLIB
905 select GENERIC_CLOCKEVENTS
908 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
912 select ARCH_HAS_HOLES_MEMORYMODEL
913 select ARCH_REQUIRE_GPIOLIB
915 select GENERIC_ALLOCATOR
916 select GENERIC_CLOCKEVENTS
917 select GENERIC_IRQ_CHIP
919 select NEED_MACH_GPIO_H
922 Support for TI's DaVinci platform.
927 select ARCH_HAS_CPUFREQ
928 select ARCH_HAS_HOLES_MEMORYMODEL
929 select ARCH_REQUIRE_GPIOLIB
931 select GENERIC_CLOCKEVENTS
934 Support for TI's OMAP platform (OMAP1/2/3/4).
936 config ARCH_VT8500_SINGLE
937 bool "VIA/WonderMedia 85xx"
938 select ARCH_HAS_CPUFREQ
939 select ARCH_REQUIRE_GPIOLIB
943 select GENERIC_CLOCKEVENTS
946 select MULTI_IRQ_HANDLER
950 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
953 bool "Xilinx Zynq ARM Cortex A9 Platform"
957 select GENERIC_CLOCKEVENTS
959 select MIGHT_HAVE_CACHE_L2X0
962 Support for Xilinx Zynq ARM Cortex A9 Platform
965 menu "Multiple platform selection"
966 depends on ARCH_MULTIPLATFORM
968 comment "CPU Core family selection"
971 bool "ARMv4 based platforms (FA526, StrongARM)"
972 depends on !ARCH_MULTI_V6_V7
973 select ARCH_MULTI_V4_V5
975 config ARCH_MULTI_V4T
976 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
977 depends on !ARCH_MULTI_V6_V7
978 select ARCH_MULTI_V4_V5
981 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
982 depends on !ARCH_MULTI_V6_V7
983 select ARCH_MULTI_V4_V5
985 config ARCH_MULTI_V4_V5
989 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
990 select ARCH_MULTI_V6_V7
994 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
996 select ARCH_MULTI_V6_V7
1000 config ARCH_MULTI_V6_V7
1003 config ARCH_MULTI_CPU_AUTO
1004 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1005 select ARCH_MULTI_V5
1010 # This is sorted alphabetically by mach-* pathname. However, plat-*
1011 # Kconfigs may be included either alphabetically (according to the
1012 # plat- suffix) or along side the corresponding mach-* source.
1014 source "arch/arm/mach-mvebu/Kconfig"
1016 source "arch/arm/mach-at91/Kconfig"
1018 source "arch/arm/mach-clps711x/Kconfig"
1020 source "arch/arm/mach-cns3xxx/Kconfig"
1022 source "arch/arm/mach-davinci/Kconfig"
1024 source "arch/arm/mach-dove/Kconfig"
1026 source "arch/arm/mach-ep93xx/Kconfig"
1028 source "arch/arm/mach-footbridge/Kconfig"
1030 source "arch/arm/mach-gemini/Kconfig"
1032 source "arch/arm/mach-h720x/Kconfig"
1034 source "arch/arm/mach-highbank/Kconfig"
1036 source "arch/arm/mach-integrator/Kconfig"
1038 source "arch/arm/mach-iop32x/Kconfig"
1040 source "arch/arm/mach-iop33x/Kconfig"
1042 source "arch/arm/mach-iop13xx/Kconfig"
1044 source "arch/arm/mach-ixp4xx/Kconfig"
1046 source "arch/arm/mach-kirkwood/Kconfig"
1048 source "arch/arm/mach-ks8695/Kconfig"
1050 source "arch/arm/mach-msm/Kconfig"
1052 source "arch/arm/mach-mv78xx0/Kconfig"
1054 source "arch/arm/mach-imx/Kconfig"
1056 source "arch/arm/mach-mxs/Kconfig"
1058 source "arch/arm/mach-netx/Kconfig"
1060 source "arch/arm/mach-nomadik/Kconfig"
1062 source "arch/arm/plat-omap/Kconfig"
1064 source "arch/arm/mach-omap1/Kconfig"
1066 source "arch/arm/mach-omap2/Kconfig"
1068 source "arch/arm/mach-orion5x/Kconfig"
1070 source "arch/arm/mach-picoxcell/Kconfig"
1072 source "arch/arm/mach-pxa/Kconfig"
1073 source "arch/arm/plat-pxa/Kconfig"
1075 source "arch/arm/mach-mmp/Kconfig"
1077 source "arch/arm/mach-realview/Kconfig"
1079 source "arch/arm/mach-sa1100/Kconfig"
1081 source "arch/arm/plat-samsung/Kconfig"
1082 source "arch/arm/plat-s3c24xx/Kconfig"
1084 source "arch/arm/mach-socfpga/Kconfig"
1086 source "arch/arm/plat-spear/Kconfig"
1088 source "arch/arm/mach-s3c24xx/Kconfig"
1090 source "arch/arm/mach-s3c2412/Kconfig"
1091 source "arch/arm/mach-s3c2440/Kconfig"
1095 source "arch/arm/mach-s3c64xx/Kconfig"
1098 source "arch/arm/mach-s5p64x0/Kconfig"
1100 source "arch/arm/mach-s5pc100/Kconfig"
1102 source "arch/arm/mach-s5pv210/Kconfig"
1104 source "arch/arm/mach-exynos/Kconfig"
1106 source "arch/arm/mach-shmobile/Kconfig"
1108 source "arch/arm/mach-prima2/Kconfig"
1110 source "arch/arm/mach-tegra/Kconfig"
1112 source "arch/arm/mach-u300/Kconfig"
1114 source "arch/arm/mach-ux500/Kconfig"
1116 source "arch/arm/mach-versatile/Kconfig"
1118 source "arch/arm/mach-vexpress/Kconfig"
1119 source "arch/arm/plat-versatile/Kconfig"
1121 source "arch/arm/mach-vt8500/Kconfig"
1123 source "arch/arm/mach-w90x900/Kconfig"
1125 # Definitions to make life easier
1131 select GENERIC_CLOCKEVENTS
1137 select GENERIC_IRQ_CHIP
1140 config PLAT_ORION_LEGACY
1147 config PLAT_VERSATILE
1150 config ARM_TIMER_SP804
1153 select HAVE_SCHED_CLOCK
1155 source arch/arm/mm/Kconfig
1159 default 16 if ARCH_EP93XX
1163 bool "Enable iWMMXt support"
1164 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1165 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1167 Enable support for iWMMXt context switching at run time if
1168 running on a CPU that supports it.
1172 depends on CPU_XSCALE
1175 config MULTI_IRQ_HANDLER
1178 Allow each machine to specify it's own IRQ handler at run time.
1181 source "arch/arm/Kconfig-nommu"
1184 config ARM_ERRATA_326103
1185 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1188 Executing a SWP instruction to read-only memory does not set bit 11
1189 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1190 treat the access as a read, preventing a COW from occurring and
1191 causing the faulting task to livelock.
1193 config ARM_ERRATA_411920
1194 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1195 depends on CPU_V6 || CPU_V6K
1197 Invalidation of the Instruction Cache operation can
1198 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1199 It does not affect the MPCore. This option enables the ARM Ltd.
1200 recommended workaround.
1202 config ARM_ERRATA_430973
1203 bool "ARM errata: Stale prediction on replaced interworking branch"
1206 This option enables the workaround for the 430973 Cortex-A8
1207 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1208 interworking branch is replaced with another code sequence at the
1209 same virtual address, whether due to self-modifying code or virtual
1210 to physical address re-mapping, Cortex-A8 does not recover from the
1211 stale interworking branch prediction. This results in Cortex-A8
1212 executing the new code sequence in the incorrect ARM or Thumb state.
1213 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1214 and also flushes the branch target cache at every context switch.
1215 Note that setting specific bits in the ACTLR register may not be
1216 available in non-secure mode.
1218 config ARM_ERRATA_458693
1219 bool "ARM errata: Processor deadlock when a false hazard is created"
1222 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1223 erratum. For very specific sequences of memory operations, it is
1224 possible for a hazard condition intended for a cache line to instead
1225 be incorrectly associated with a different cache line. This false
1226 hazard might then cause a processor deadlock. The workaround enables
1227 the L1 caching of the NEON accesses and disables the PLD instruction
1228 in the ACTLR register. Note that setting specific bits in the ACTLR
1229 register may not be available in non-secure mode.
1231 config ARM_ERRATA_460075
1232 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1235 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1236 erratum. Any asynchronous access to the L2 cache may encounter a
1237 situation in which recent store transactions to the L2 cache are lost
1238 and overwritten with stale memory contents from external memory. The
1239 workaround disables the write-allocate mode for the L2 cache via the
1240 ACTLR register. Note that setting specific bits in the ACTLR register
1241 may not be available in non-secure mode.
1243 config ARM_ERRATA_742230
1244 bool "ARM errata: DMB operation may be faulty"
1245 depends on CPU_V7 && SMP
1247 This option enables the workaround for the 742230 Cortex-A9
1248 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1249 between two write operations may not ensure the correct visibility
1250 ordering of the two writes. This workaround sets a specific bit in
1251 the diagnostic register of the Cortex-A9 which causes the DMB
1252 instruction to behave as a DSB, ensuring the correct behaviour of
1255 config ARM_ERRATA_742231
1256 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1257 depends on CPU_V7 && SMP
1259 This option enables the workaround for the 742231 Cortex-A9
1260 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1261 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1262 accessing some data located in the same cache line, may get corrupted
1263 data due to bad handling of the address hazard when the line gets
1264 replaced from one of the CPUs at the same time as another CPU is
1265 accessing it. This workaround sets specific bits in the diagnostic
1266 register of the Cortex-A9 which reduces the linefill issuing
1267 capabilities of the processor.
1269 config PL310_ERRATA_588369
1270 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1271 depends on CACHE_L2X0
1273 The PL310 L2 cache controller implements three types of Clean &
1274 Invalidate maintenance operations: by Physical Address
1275 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1276 They are architecturally defined to behave as the execution of a
1277 clean operation followed immediately by an invalidate operation,
1278 both performing to the same memory location. This functionality
1279 is not correctly implemented in PL310 as clean lines are not
1280 invalidated as a result of these operations.
1282 config ARM_ERRATA_720789
1283 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1286 This option enables the workaround for the 720789 Cortex-A9 (prior to
1287 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1288 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1289 As a consequence of this erratum, some TLB entries which should be
1290 invalidated are not, resulting in an incoherency in the system page
1291 tables. The workaround changes the TLB flushing routines to invalidate
1292 entries regardless of the ASID.
1294 config PL310_ERRATA_727915
1295 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1296 depends on CACHE_L2X0
1298 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1299 operation (offset 0x7FC). This operation runs in background so that
1300 PL310 can handle normal accesses while it is in progress. Under very
1301 rare circumstances, due to this erratum, write data can be lost when
1302 PL310 treats a cacheable write transaction during a Clean &
1303 Invalidate by Way operation.
1305 config ARM_ERRATA_743622
1306 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1309 This option enables the workaround for the 743622 Cortex-A9
1310 (r2p*) erratum. Under very rare conditions, a faulty
1311 optimisation in the Cortex-A9 Store Buffer may lead to data
1312 corruption. This workaround sets a specific bit in the diagnostic
1313 register of the Cortex-A9 which disables the Store Buffer
1314 optimisation, preventing the defect from occurring. This has no
1315 visible impact on the overall performance or power consumption of the
1318 config ARM_ERRATA_751472
1319 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1322 This option enables the workaround for the 751472 Cortex-A9 (prior
1323 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1324 completion of a following broadcasted operation if the second
1325 operation is received by a CPU before the ICIALLUIS has completed,
1326 potentially leading to corrupted entries in the cache or TLB.
1328 config PL310_ERRATA_753970
1329 bool "PL310 errata: cache sync operation may be faulty"
1330 depends on CACHE_PL310
1332 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1334 Under some condition the effect of cache sync operation on
1335 the store buffer still remains when the operation completes.
1336 This means that the store buffer is always asked to drain and
1337 this prevents it from merging any further writes. The workaround
1338 is to replace the normal offset of cache sync operation (0x730)
1339 by another offset targeting an unmapped PL310 register 0x740.
1340 This has the same effect as the cache sync operation: store buffer
1341 drain and waiting for all buffers empty.
1343 config ARM_ERRATA_754322
1344 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1347 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1348 r3p*) erratum. A speculative memory access may cause a page table walk
1349 which starts prior to an ASID switch but completes afterwards. This
1350 can populate the micro-TLB with a stale entry which may be hit with
1351 the new ASID. This workaround places two dsb instructions in the mm
1352 switching code so that no page table walks can cross the ASID switch.
1354 config ARM_ERRATA_754327
1355 bool "ARM errata: no automatic Store Buffer drain"
1356 depends on CPU_V7 && SMP
1358 This option enables the workaround for the 754327 Cortex-A9 (prior to
1359 r2p0) erratum. The Store Buffer does not have any automatic draining
1360 mechanism and therefore a livelock may occur if an external agent
1361 continuously polls a memory location waiting to observe an update.
1362 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1363 written polling loops from denying visibility of updates to memory.
1365 config ARM_ERRATA_364296
1366 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1367 depends on CPU_V6 && !SMP
1369 This options enables the workaround for the 364296 ARM1136
1370 r0p2 erratum (possible cache data corruption with
1371 hit-under-miss enabled). It sets the undocumented bit 31 in
1372 the auxiliary control register and the FI bit in the control
1373 register, thus disabling hit-under-miss without putting the
1374 processor into full low interrupt latency mode. ARM11MPCore
1377 config ARM_ERRATA_764369
1378 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1379 depends on CPU_V7 && SMP
1381 This option enables the workaround for erratum 764369
1382 affecting Cortex-A9 MPCore with two or more processors (all
1383 current revisions). Under certain timing circumstances, a data
1384 cache line maintenance operation by MVA targeting an Inner
1385 Shareable memory region may fail to proceed up to either the
1386 Point of Coherency or to the Point of Unification of the
1387 system. This workaround adds a DSB instruction before the
1388 relevant cache maintenance functions and sets a specific bit
1389 in the diagnostic control register of the SCU.
1391 config PL310_ERRATA_769419
1392 bool "PL310 errata: no automatic Store Buffer drain"
1393 depends on CACHE_L2X0
1395 On revisions of the PL310 prior to r3p2, the Store Buffer does
1396 not automatically drain. This can cause normal, non-cacheable
1397 writes to be retained when the memory system is idle, leading
1398 to suboptimal I/O performance for drivers using coherent DMA.
1399 This option adds a write barrier to the cpu_idle loop so that,
1400 on systems with an outer cache, the store buffer is drained
1403 config ARM_ERRATA_775420
1404 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1407 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1408 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1409 operation aborts with MMU exception, it might cause the processor
1410 to deadlock. This workaround puts DSB before executing ISB if
1411 an abort may occur on cache maintenance.
1415 source "arch/arm/common/Kconfig"
1425 Find out whether you have ISA slots on your motherboard. ISA is the
1426 name of a bus system, i.e. the way the CPU talks to the other stuff
1427 inside your box. Other bus systems are PCI, EISA, MicroChannel
1428 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1429 newer boards don't support it. If you have ISA, say Y, otherwise N.
1431 # Select ISA DMA controller support
1436 # Select ISA DMA interface
1441 bool "PCI support" if MIGHT_HAVE_PCI
1443 Find out whether you have a PCI motherboard. PCI is the name of a
1444 bus system, i.e. the way the CPU talks to the other stuff inside
1445 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1446 VESA. If you have PCI, say Y, otherwise N.
1452 config PCI_NANOENGINE
1453 bool "BSE nanoEngine PCI support"
1454 depends on SA1100_NANOENGINE
1456 Enable PCI on the BSE nanoEngine board.
1461 # Select the host bridge type
1462 config PCI_HOST_VIA82C505
1464 depends on PCI && ARCH_SHARK
1467 config PCI_HOST_ITE8152
1469 depends on PCI && MACH_ARMCORE
1473 source "drivers/pci/Kconfig"
1475 source "drivers/pcmcia/Kconfig"
1479 menu "Kernel Features"
1484 This option should be selected by machines which have an SMP-
1487 The only effect of this option is to make the SMP-related
1488 options available to the user for configuration.
1491 bool "Symmetric Multi-Processing"
1492 depends on CPU_V6K || CPU_V7
1493 depends on GENERIC_CLOCKEVENTS
1496 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1497 select USE_GENERIC_SMP_HELPERS
1499 This enables support for systems with more than one CPU. If you have
1500 a system with only one CPU, like most personal computers, say N. If
1501 you have a system with more than one CPU, say Y.
1503 If you say N here, the kernel will run on single and multiprocessor
1504 machines, but will use only one CPU of a multiprocessor machine. If
1505 you say Y here, the kernel will run on many, but not all, single
1506 processor machines. On a single processor machine, the kernel will
1507 run faster if you say N here.
1509 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1510 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1511 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1513 If you don't know what to do here, say N.
1516 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1517 depends on EXPERIMENTAL
1518 depends on SMP && !XIP_KERNEL
1521 SMP kernels contain instructions which fail on non-SMP processors.
1522 Enabling this option allows the kernel to modify itself to make
1523 these instructions safe. Disabling it allows about 1K of space
1526 If you don't know what to do here, say Y.
1528 config ARM_CPU_TOPOLOGY
1529 bool "Support cpu topology definition"
1530 depends on SMP && CPU_V7
1533 Support ARM cpu topology definition. The MPIDR register defines
1534 affinity between processors which is then used to describe the cpu
1535 topology of an ARM System.
1538 bool "Multi-core scheduler support"
1539 depends on ARM_CPU_TOPOLOGY
1541 Multi-core scheduler support improves the CPU scheduler's decision
1542 making when dealing with multi-core CPU chips at a cost of slightly
1543 increased overhead in some places. If unsure say N here.
1546 bool "SMT scheduler support"
1547 depends on ARM_CPU_TOPOLOGY
1549 Improves the CPU scheduler's decision making when dealing with
1550 MultiThreading at a cost of slightly increased overhead in some
1551 places. If unsure say N here.
1556 This option enables support for the ARM system coherency unit
1558 config ARM_ARCH_TIMER
1559 bool "Architected timer support"
1562 This option enables support for the ARM architected timer
1568 This options enables support for the ARM timer and watchdog unit
1571 prompt "Memory split"
1574 Select the desired split between kernel and user memory.
1576 If you are not absolutely sure what you are doing, leave this
1580 bool "3G/1G user/kernel split"
1582 bool "2G/2G user/kernel split"
1584 bool "1G/3G user/kernel split"
1589 default 0x40000000 if VMSPLIT_1G
1590 default 0x80000000 if VMSPLIT_2G
1594 int "Maximum number of CPUs (2-32)"
1600 bool "Support for hot-pluggable CPUs"
1601 depends on SMP && HOTPLUG
1603 Say Y here to experiment with turning CPUs off and on. CPUs
1604 can be controlled through /sys/devices/system/cpu.
1607 bool "Use local timer interrupts"
1610 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1612 Enable support for local timers on SMP platforms, rather then the
1613 legacy IPI broadcast method. Local timers allows the system
1614 accounting to be spread across the timer interval, preventing a
1615 "thundering herd" at every timer tick.
1619 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1620 default 355 if ARCH_U8500
1621 default 264 if MACH_H4700
1622 default 512 if SOC_OMAP5
1623 default 288 if ARCH_VT8500
1626 Maximum number of GPIOs in the system.
1628 If unsure, leave the default value.
1630 source kernel/Kconfig.preempt
1634 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1635 ARCH_S5PV210 || ARCH_EXYNOS4
1636 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1637 default AT91_TIMER_HZ if ARCH_AT91
1638 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1641 config THUMB2_KERNEL
1642 bool "Compile the kernel in Thumb-2 mode"
1643 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1645 select ARM_ASM_UNIFIED
1648 By enabling this option, the kernel will be compiled in
1649 Thumb-2 mode. A compiler/assembler that understand the unified
1650 ARM-Thumb syntax is needed.
1654 config THUMB2_AVOID_R_ARM_THM_JUMP11
1655 bool "Work around buggy Thumb-2 short branch relocations in gas"
1656 depends on THUMB2_KERNEL && MODULES
1659 Various binutils versions can resolve Thumb-2 branches to
1660 locally-defined, preemptible global symbols as short-range "b.n"
1661 branch instructions.
1663 This is a problem, because there's no guarantee the final
1664 destination of the symbol, or any candidate locations for a
1665 trampoline, are within range of the branch. For this reason, the
1666 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1667 relocation in modules at all, and it makes little sense to add
1670 The symptom is that the kernel fails with an "unsupported
1671 relocation" error when loading some modules.
1673 Until fixed tools are available, passing
1674 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1675 code which hits this problem, at the cost of a bit of extra runtime
1676 stack usage in some cases.
1678 The problem is described in more detail at:
1679 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1681 Only Thumb-2 kernels are affected.
1683 Unless you are sure your tools don't have this problem, say Y.
1685 config ARM_ASM_UNIFIED
1689 bool "Use the ARM EABI to compile the kernel"
1691 This option allows for the kernel to be compiled using the latest
1692 ARM ABI (aka EABI). This is only useful if you are using a user
1693 space environment that is also compiled with EABI.
1695 Since there are major incompatibilities between the legacy ABI and
1696 EABI, especially with regard to structure member alignment, this
1697 option also changes the kernel syscall calling convention to
1698 disambiguate both ABIs and allow for backward compatibility support
1699 (selected with CONFIG_OABI_COMPAT).
1701 To use this you need GCC version 4.0.0 or later.
1704 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1705 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1708 This option preserves the old syscall interface along with the
1709 new (ARM EABI) one. It also provides a compatibility layer to
1710 intercept syscalls that have structure arguments which layout
1711 in memory differs between the legacy ABI and the new ARM EABI
1712 (only for non "thumb" binaries). This option adds a tiny
1713 overhead to all syscalls and produces a slightly larger kernel.
1714 If you know you'll be using only pure EABI user space then you
1715 can say N here. If this option is not selected and you attempt
1716 to execute a legacy ABI binary then the result will be
1717 UNPREDICTABLE (in fact it can be predicted that it won't work
1718 at all). If in doubt say Y.
1720 config ARCH_HAS_HOLES_MEMORYMODEL
1723 config ARCH_SPARSEMEM_ENABLE
1726 config ARCH_SPARSEMEM_DEFAULT
1727 def_bool ARCH_SPARSEMEM_ENABLE
1729 config ARCH_SELECT_MEMORY_MODEL
1730 def_bool ARCH_SPARSEMEM_ENABLE
1732 config HAVE_ARCH_PFN_VALID
1733 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1736 bool "High Memory Support"
1739 The address space of ARM processors is only 4 Gigabytes large
1740 and it has to accommodate user address space, kernel address
1741 space as well as some memory mapped IO. That means that, if you
1742 have a large amount of physical memory and/or IO, not all of the
1743 memory can be "permanently mapped" by the kernel. The physical
1744 memory that is not permanently mapped is called "high memory".
1746 Depending on the selected kernel/user memory split, minimum
1747 vmalloc space and actual amount of RAM, you may not need this
1748 option which should result in a slightly faster kernel.
1753 bool "Allocate 2nd-level pagetables from highmem"
1756 config HW_PERF_EVENTS
1757 bool "Enable hardware performance counter support for perf events"
1758 depends on PERF_EVENTS
1761 Enable hardware performance counter support for perf events. If
1762 disabled, perf events will use software events only.
1766 config FORCE_MAX_ZONEORDER
1767 int "Maximum zone order" if ARCH_SHMOBILE
1768 range 11 64 if ARCH_SHMOBILE
1769 default "12" if SOC_AM33XX
1770 default "9" if SA1111
1773 The kernel memory allocator divides physically contiguous memory
1774 blocks into "zones", where each zone is a power of two number of
1775 pages. This option selects the largest power of two that the kernel
1776 keeps in the memory allocator. If you need to allocate very large
1777 blocks of physically contiguous memory, then you may need to
1778 increase this value.
1780 This config option is actually maximum order plus one. For example,
1781 a value of 11 means that the largest free memory block is 2^10 pages.
1783 config ALIGNMENT_TRAP
1785 depends on CPU_CP15_MMU
1786 default y if !ARCH_EBSA110
1787 select HAVE_PROC_CPU if PROC_FS
1789 ARM processors cannot fetch/store information which is not
1790 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1791 address divisible by 4. On 32-bit ARM processors, these non-aligned
1792 fetch/store instructions will be emulated in software if you say
1793 here, which has a severe performance impact. This is necessary for
1794 correct operation of some network protocols. With an IP-only
1795 configuration it is safe to say N, otherwise say Y.
1797 config UACCESS_WITH_MEMCPY
1798 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1800 default y if CPU_FEROCEON
1802 Implement faster copy_to_user and clear_user methods for CPU
1803 cores where a 8-word STM instruction give significantly higher
1804 memory write throughput than a sequence of individual 32bit stores.
1806 A possible side effect is a slight increase in scheduling latency
1807 between threads sharing the same address space if they invoke
1808 such copy operations with large buffers.
1810 However, if the CPU data cache is using a write-allocate mode,
1811 this option is unlikely to provide any performance gain.
1815 prompt "Enable seccomp to safely compute untrusted bytecode"
1817 This kernel feature is useful for number crunching applications
1818 that may need to compute untrusted bytecode during their
1819 execution. By using pipes or other transports made available to
1820 the process as file descriptors supporting the read/write
1821 syscalls, it's possible to isolate those applications in
1822 their own address space using seccomp. Once seccomp is
1823 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1824 and the task is only allowed to execute a few safe syscalls
1825 defined by each seccomp mode.
1827 config CC_STACKPROTECTOR
1828 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1829 depends on EXPERIMENTAL
1831 This option turns on the -fstack-protector GCC feature. This
1832 feature puts, at the beginning of functions, a canary value on
1833 the stack just before the return address, and validates
1834 the value just before actually returning. Stack based buffer
1835 overflows (that need to overwrite this return address) now also
1836 overwrite the canary, which gets detected and the attack is then
1837 neutralized via a kernel panic.
1838 This feature requires gcc version 4.2 or above.
1845 bool "Xen guest support on ARM (EXPERIMENTAL)"
1846 depends on EXPERIMENTAL && ARM && OF
1847 depends on CPU_V7 && !CPU_V6
1849 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1856 bool "Flattened Device Tree support"
1859 select OF_EARLY_FLATTREE
1861 Include support for flattened device tree machine descriptions.
1864 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1867 This is the traditional way of passing data to the kernel at boot
1868 time. If you are solely relying on the flattened device tree (or
1869 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1870 to remove ATAGS support from your kernel binary. If unsure,
1873 config DEPRECATED_PARAM_STRUCT
1874 bool "Provide old way to pass kernel parameters"
1877 This was deprecated in 2001 and announced to live on for 5 years.
1878 Some old boot loaders still use this way.
1880 # Compressed boot loader in ROM. Yes, we really want to ask about
1881 # TEXT and BSS so we preserve their values in the config files.
1882 config ZBOOT_ROM_TEXT
1883 hex "Compressed ROM boot loader base address"
1886 The physical address at which the ROM-able zImage is to be
1887 placed in the target. Platforms which normally make use of
1888 ROM-able zImage formats normally set this to a suitable
1889 value in their defconfig file.
1891 If ZBOOT_ROM is not enabled, this has no effect.
1893 config ZBOOT_ROM_BSS
1894 hex "Compressed ROM boot loader BSS address"
1897 The base address of an area of read/write memory in the target
1898 for the ROM-able zImage which must be available while the
1899 decompressor is running. It must be large enough to hold the
1900 entire decompressed kernel plus an additional 128 KiB.
1901 Platforms which normally make use of ROM-able zImage formats
1902 normally set this to a suitable value in their defconfig file.
1904 If ZBOOT_ROM is not enabled, this has no effect.
1907 bool "Compressed boot loader in ROM/flash"
1908 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1910 Say Y here if you intend to execute your compressed kernel image
1911 (zImage) directly from ROM or flash. If unsure, say N.
1914 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1915 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1916 default ZBOOT_ROM_NONE
1918 Include experimental SD/MMC loading code in the ROM-able zImage.
1919 With this enabled it is possible to write the ROM-able zImage
1920 kernel image to an MMC or SD card and boot the kernel straight
1921 from the reset vector. At reset the processor Mask ROM will load
1922 the first part of the ROM-able zImage which in turn loads the
1923 rest the kernel image to RAM.
1925 config ZBOOT_ROM_NONE
1926 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1928 Do not load image from SD or MMC
1930 config ZBOOT_ROM_MMCIF
1931 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1933 Load image from MMCIF hardware block.
1935 config ZBOOT_ROM_SH_MOBILE_SDHI
1936 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1938 Load image from SDHI hardware block
1942 config ARM_APPENDED_DTB
1943 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1944 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1946 With this option, the boot code will look for a device tree binary
1947 (DTB) appended to zImage
1948 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1950 This is meant as a backward compatibility convenience for those
1951 systems with a bootloader that can't be upgraded to accommodate
1952 the documented boot protocol using a device tree.
1954 Beware that there is very little in terms of protection against
1955 this option being confused by leftover garbage in memory that might
1956 look like a DTB header after a reboot if no actual DTB is appended
1957 to zImage. Do not leave this option active in a production kernel
1958 if you don't intend to always append a DTB. Proper passing of the
1959 location into r2 of a bootloader provided DTB is always preferable
1962 config ARM_ATAG_DTB_COMPAT
1963 bool "Supplement the appended DTB with traditional ATAG information"
1964 depends on ARM_APPENDED_DTB
1966 Some old bootloaders can't be updated to a DTB capable one, yet
1967 they provide ATAGs with memory configuration, the ramdisk address,
1968 the kernel cmdline string, etc. Such information is dynamically
1969 provided by the bootloader and can't always be stored in a static
1970 DTB. To allow a device tree enabled kernel to be used with such
1971 bootloaders, this option allows zImage to extract the information
1972 from the ATAG list and store it at run time into the appended DTB.
1975 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1976 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1978 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1979 bool "Use bootloader kernel arguments if available"
1981 Uses the command-line options passed by the boot loader instead of
1982 the device tree bootargs property. If the boot loader doesn't provide
1983 any, the device tree bootargs property will be used.
1985 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1986 bool "Extend with bootloader kernel arguments"
1988 The command-line arguments provided by the boot loader will be
1989 appended to the the device tree bootargs property.
1994 string "Default kernel command string"
1997 On some architectures (EBSA110 and CATS), there is currently no way
1998 for the boot loader to pass arguments to the kernel. For these
1999 architectures, you should supply some command-line options at build
2000 time by entering them here. As a minimum, you should specify the
2001 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2004 prompt "Kernel command line type" if CMDLINE != ""
2005 default CMDLINE_FROM_BOOTLOADER
2008 config CMDLINE_FROM_BOOTLOADER
2009 bool "Use bootloader kernel arguments if available"
2011 Uses the command-line options passed by the boot loader. If
2012 the boot loader doesn't provide any, the default kernel command
2013 string provided in CMDLINE will be used.
2015 config CMDLINE_EXTEND
2016 bool "Extend bootloader kernel arguments"
2018 The command-line arguments provided by the boot loader will be
2019 appended to the default kernel command string.
2021 config CMDLINE_FORCE
2022 bool "Always use the default kernel command string"
2024 Always use the default kernel command string, even if the boot
2025 loader passes other arguments to the kernel.
2026 This is useful if you cannot or don't want to change the
2027 command-line options your boot loader passes to the kernel.
2031 bool "Kernel Execute-In-Place from ROM"
2032 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2034 Execute-In-Place allows the kernel to run from non-volatile storage
2035 directly addressable by the CPU, such as NOR flash. This saves RAM
2036 space since the text section of the kernel is not loaded from flash
2037 to RAM. Read-write sections, such as the data section and stack,
2038 are still copied to RAM. The XIP kernel is not compressed since
2039 it has to run directly from flash, so it will take more space to
2040 store it. The flash address used to link the kernel object files,
2041 and for storing it, is configuration dependent. Therefore, if you
2042 say Y here, you must know the proper physical address where to
2043 store the kernel image depending on your own flash memory usage.
2045 Also note that the make target becomes "make xipImage" rather than
2046 "make zImage" or "make Image". The final kernel binary to put in
2047 ROM memory will be arch/arm/boot/xipImage.
2051 config XIP_PHYS_ADDR
2052 hex "XIP Kernel Physical Location"
2053 depends on XIP_KERNEL
2054 default "0x00080000"
2056 This is the physical address in your flash memory the kernel will
2057 be linked for and stored to. This address is dependent on your
2061 bool "Kexec system call (EXPERIMENTAL)"
2062 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2064 kexec is a system call that implements the ability to shutdown your
2065 current kernel, and to start another kernel. It is like a reboot
2066 but it is independent of the system firmware. And like a reboot
2067 you can start any kernel with it, not just Linux.
2069 It is an ongoing process to be certain the hardware in a machine
2070 is properly shutdown, so do not be surprised if this code does not
2071 initially work for you. It may help to enable device hotplugging
2075 bool "Export atags in procfs"
2076 depends on ATAGS && KEXEC
2079 Should the atags used to boot the kernel be exported in an "atags"
2080 file in procfs. Useful with kexec.
2083 bool "Build kdump crash kernel (EXPERIMENTAL)"
2084 depends on EXPERIMENTAL
2086 Generate crash dump after being started by kexec. This should
2087 be normally only set in special crash dump kernels which are
2088 loaded in the main kernel with kexec-tools into a specially
2089 reserved region and then later executed after a crash by
2090 kdump/kexec. The crash dump kernel must be compiled to a
2091 memory address not used by the main kernel
2093 For more details see Documentation/kdump/kdump.txt
2095 config AUTO_ZRELADDR
2096 bool "Auto calculation of the decompressed kernel image address"
2097 depends on !ZBOOT_ROM && !ARCH_U300
2099 ZRELADDR is the physical address where the decompressed kernel
2100 image will be placed. If AUTO_ZRELADDR is selected, the address
2101 will be determined at run-time by masking the current IP with
2102 0xf8000000. This assumes the zImage being placed in the first 128MB
2103 from start of memory.
2107 menu "CPU Power Management"
2111 source "drivers/cpufreq/Kconfig"
2114 tristate "CPUfreq driver for i.MX CPUs"
2115 depends on ARCH_MXC && CPU_FREQ
2116 select CPU_FREQ_TABLE
2118 This enables the CPUfreq driver for i.MX CPUs.
2120 config CPU_FREQ_SA1100
2123 config CPU_FREQ_SA1110
2126 config CPU_FREQ_INTEGRATOR
2127 tristate "CPUfreq driver for ARM Integrator CPUs"
2128 depends on ARCH_INTEGRATOR && CPU_FREQ
2131 This enables the CPUfreq driver for ARM Integrator CPUs.
2133 For details, take a look at <file:Documentation/cpu-freq>.
2139 depends on CPU_FREQ && ARCH_PXA && PXA25x
2141 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2142 select CPU_FREQ_TABLE
2147 Internal configuration node for common cpufreq on Samsung SoC
2149 config CPU_FREQ_S3C24XX
2150 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2151 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2154 This enables the CPUfreq driver for the Samsung S3C24XX family
2157 For details, take a look at <file:Documentation/cpu-freq>.
2161 config CPU_FREQ_S3C24XX_PLL
2162 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2163 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2165 Compile in support for changing the PLL frequency from the
2166 S3C24XX series CPUfreq driver. The PLL takes time to settle
2167 after a frequency change, so by default it is not enabled.
2169 This also means that the PLL tables for the selected CPU(s) will
2170 be built which may increase the size of the kernel image.
2172 config CPU_FREQ_S3C24XX_DEBUG
2173 bool "Debug CPUfreq Samsung driver core"
2174 depends on CPU_FREQ_S3C24XX
2176 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2178 config CPU_FREQ_S3C24XX_IODEBUG
2179 bool "Debug CPUfreq Samsung driver IO timing"
2180 depends on CPU_FREQ_S3C24XX
2182 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2184 config CPU_FREQ_S3C24XX_DEBUGFS
2185 bool "Export debugfs for CPUFreq"
2186 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2188 Export status information via debugfs.
2192 source "drivers/cpuidle/Kconfig"
2196 menu "Floating point emulation"
2198 comment "At least one emulation must be selected"
2201 bool "NWFPE math emulation"
2202 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2204 Say Y to include the NWFPE floating point emulator in the kernel.
2205 This is necessary to run most binaries. Linux does not currently
2206 support floating point hardware so you need to say Y here even if
2207 your machine has an FPA or floating point co-processor podule.
2209 You may say N here if you are going to load the Acorn FPEmulator
2210 early in the bootup.
2213 bool "Support extended precision"
2214 depends on FPE_NWFPE
2216 Say Y to include 80-bit support in the kernel floating-point
2217 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2218 Note that gcc does not generate 80-bit operations by default,
2219 so in most cases this option only enlarges the size of the
2220 floating point emulator without any good reason.
2222 You almost surely want to say N here.
2225 bool "FastFPE math emulation (EXPERIMENTAL)"
2226 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2228 Say Y here to include the FAST floating point emulator in the kernel.
2229 This is an experimental much faster emulator which now also has full
2230 precision for the mantissa. It does not support any exceptions.
2231 It is very simple, and approximately 3-6 times faster than NWFPE.
2233 It should be sufficient for most programs. It may be not suitable
2234 for scientific calculations, but you have to check this for yourself.
2235 If you do not feel you need a faster FP emulation you should better
2239 bool "VFP-format floating point maths"
2240 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2242 Say Y to include VFP support code in the kernel. This is needed
2243 if your hardware includes a VFP unit.
2245 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2246 release notes and additional status information.
2248 Say N if your target does not have VFP hardware.
2256 bool "Advanced SIMD (NEON) Extension support"
2257 depends on VFPv3 && CPU_V7
2259 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2264 menu "Userspace binary formats"
2266 source "fs/Kconfig.binfmt"
2269 tristate "RISC OS personality"
2272 Say Y here to include the kernel code necessary if you want to run
2273 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2274 experimental; if this sounds frightening, say N and sleep in peace.
2275 You can also say M here to compile this support as a module (which
2276 will be called arthur).
2280 menu "Power management options"
2282 source "kernel/power/Kconfig"
2284 config ARCH_SUSPEND_POSSIBLE
2285 depends on !ARCH_S5PC100
2286 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2287 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2290 config ARM_CPU_SUSPEND
2295 source "net/Kconfig"
2297 source "drivers/Kconfig"
2301 source "arch/arm/Kconfig.debug"
2303 source "security/Kconfig"
2305 source "crypto/Kconfig"
2307 source "lib/Kconfig"