5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NEED_MACH_MEMORY_H
217 Select this when mach/memory.h is required to provide special
218 definitions for this platform. The need for mach/memory.h should
219 be avoided when possible.
222 hex "Physical address of main memory"
223 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
228 source "init/Kconfig"
230 source "kernel/Kconfig.freezer"
235 bool "MMU-based Paged Memory Management Support"
238 Select if you want MMU-based virtualised addressing space
239 support by paged memory management. If unsure, say 'Y'.
242 # The "ARM system type" choice list is ordered alphabetically by option
243 # text. Please add new entries in the option alphabetic order.
246 prompt "ARM system type"
247 default ARCH_VERSATILE
249 config ARCH_INTEGRATOR
250 bool "ARM Ltd. Integrator family"
252 select ARCH_HAS_CPUFREQ
254 select HAVE_MACH_CLKDEV
256 select GENERIC_CLOCKEVENTS
257 select PLAT_VERSATILE
258 select PLAT_VERSATILE_FPGA_IRQ
259 select NEED_MACH_MEMORY_H
261 Support for ARM's Integrator platform.
264 bool "ARM Ltd. RealView family"
267 select HAVE_MACH_CLKDEV
269 select GENERIC_CLOCKEVENTS
270 select ARCH_WANT_OPTIONAL_GPIOLIB
271 select PLAT_VERSATILE
272 select PLAT_VERSATILE_CLCD
273 select ARM_TIMER_SP804
274 select GPIO_PL061 if GPIOLIB
275 select NEED_MACH_MEMORY_H
277 This enables support for ARM Ltd RealView boards.
279 config ARCH_VERSATILE
280 bool "ARM Ltd. Versatile family"
284 select HAVE_MACH_CLKDEV
286 select GENERIC_CLOCKEVENTS
287 select ARCH_WANT_OPTIONAL_GPIOLIB
288 select PLAT_VERSATILE
289 select PLAT_VERSATILE_CLCD
290 select PLAT_VERSATILE_FPGA_IRQ
291 select ARM_TIMER_SP804
293 This enables support for ARM Ltd Versatile board.
296 bool "ARM Ltd. Versatile Express family"
297 select ARCH_WANT_OPTIONAL_GPIOLIB
299 select ARM_TIMER_SP804
301 select HAVE_MACH_CLKDEV
302 select GENERIC_CLOCKEVENTS
304 select HAVE_PATA_PLATFORM
306 select PLAT_VERSATILE
307 select PLAT_VERSATILE_CLCD
309 This enables support for the ARM Ltd Versatile Express boards.
313 select ARCH_REQUIRE_GPIOLIB
317 This enables support for systems based on the Atmel AT91RM9200,
318 AT91SAM9 and AT91CAP9 processors.
321 bool "Broadcom BCMRING"
325 select ARM_TIMER_SP804
327 select GENERIC_CLOCKEVENTS
328 select ARCH_WANT_OPTIONAL_GPIOLIB
330 Support for Broadcom's BCMRing platform.
333 bool "Cirrus Logic CLPS711x/EP721x-based"
335 select ARCH_USES_GETTIMEOFFSET
336 select NEED_MACH_MEMORY_H
338 Support for Cirrus Logic 711x/721x based boards.
341 bool "Cavium Networks CNS3XXX family"
343 select GENERIC_CLOCKEVENTS
345 select MIGHT_HAVE_PCI
346 select PCI_DOMAINS if PCI
348 Support for Cavium Networks CNS3XXX platform.
351 bool "Cortina Systems Gemini"
353 select ARCH_REQUIRE_GPIOLIB
354 select ARCH_USES_GETTIMEOFFSET
356 Support for the Cortina Systems Gemini family SoCs
359 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
363 select GENERIC_CLOCKEVENTS
365 select GENERIC_IRQ_CHIP
369 Support for CSR SiRFSoC ARM Cortex A9 Platform
376 select ARCH_USES_GETTIMEOFFSET
377 select NEED_MACH_MEMORY_H
379 This is an evaluation board for the StrongARM processor available
380 from Digital. It has limited hardware on-board, including an
381 Ethernet interface, two PCMCIA sockets, two serial ports and a
390 select ARCH_REQUIRE_GPIOLIB
391 select ARCH_HAS_HOLES_MEMORYMODEL
392 select ARCH_USES_GETTIMEOFFSET
395 This enables support for the Cirrus EP93xx series of CPUs.
397 config ARCH_FOOTBRIDGE
401 select GENERIC_CLOCKEVENTS
402 select NEED_MACH_MEMORY_H
404 Support for systems based on the DC21285 companion chip
405 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
408 bool "Freescale MXC/iMX-based"
409 select GENERIC_CLOCKEVENTS
410 select ARCH_REQUIRE_GPIOLIB
413 select GENERIC_IRQ_CHIP
414 select HAVE_SCHED_CLOCK
416 Support for Freescale MXC/iMX-based family of processors
419 bool "Freescale MXS-based"
420 select GENERIC_CLOCKEVENTS
421 select ARCH_REQUIRE_GPIOLIB
425 Support for Freescale MXS-based family of processors
428 bool "Hilscher NetX based"
432 select GENERIC_CLOCKEVENTS
434 This enables support for systems based on the Hilscher NetX Soc
437 bool "Hynix HMS720x-based"
440 select ARCH_USES_GETTIMEOFFSET
442 This enables support for systems based on the Hynix HMS720x
450 select ARCH_SUPPORTS_MSI
452 select NEED_MACH_MEMORY_H
454 Support for Intel's IOP13XX (XScale) family of processors.
462 select ARCH_REQUIRE_GPIOLIB
464 Support for Intel's 80219 and IOP32X (XScale) family of
473 select ARCH_REQUIRE_GPIOLIB
475 Support for Intel's IOP33X (XScale) family of processors.
482 select ARCH_USES_GETTIMEOFFSET
483 select NEED_MACH_MEMORY_H
485 Support for Intel's IXP23xx (XScale) family of processors.
488 bool "IXP2400/2800-based"
492 select ARCH_USES_GETTIMEOFFSET
493 select NEED_MACH_MEMORY_H
495 Support for Intel's IXP2400/2800 (XScale) family of processors.
503 select GENERIC_CLOCKEVENTS
504 select HAVE_SCHED_CLOCK
505 select MIGHT_HAVE_PCI
506 select DMABOUNCE if PCI
508 Support for Intel's IXP4XX (XScale) family of processors.
514 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
518 Support for the Marvell Dove SoC 88AP510
521 bool "Marvell Kirkwood"
524 select ARCH_REQUIRE_GPIOLIB
525 select GENERIC_CLOCKEVENTS
528 Support for the following Marvell Kirkwood series SoCs:
529 88F6180, 88F6192 and 88F6281.
535 select ARCH_REQUIRE_GPIOLIB
538 select USB_ARCH_HAS_OHCI
541 select GENERIC_CLOCKEVENTS
543 Support for the NXP LPC32XX family of processors
546 bool "Marvell MV78xx0"
549 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
553 Support for the following Marvell MV78xx0 series SoCs:
561 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
565 Support for the following Marvell Orion 5x series SoCs:
566 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
567 Orion-2 (5281), Orion-1-90 (6183).
570 bool "Marvell PXA168/910/MMP2"
572 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
575 select HAVE_SCHED_CLOCK
580 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
583 bool "Micrel/Kendin KS8695"
585 select ARCH_REQUIRE_GPIOLIB
586 select ARCH_USES_GETTIMEOFFSET
587 select NEED_MACH_MEMORY_H
589 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
590 System-on-Chip devices.
593 bool "Nuvoton W90X900 CPU"
595 select ARCH_REQUIRE_GPIOLIB
598 select GENERIC_CLOCKEVENTS
600 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
601 At present, the w90x900 has been renamed nuc900, regarding
602 the ARM series product line, you can login the following
603 link address to know more.
605 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
606 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
609 bool "Nuvoton NUC93X CPU"
613 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
614 low-power and high performance MPEG-4/JPEG multimedia controller chip.
621 select GENERIC_CLOCKEVENTS
624 select HAVE_SCHED_CLOCK
625 select ARCH_HAS_CPUFREQ
627 This enables support for NVIDIA Tegra based systems (Tegra APX,
628 Tegra 6xx and Tegra 2 series).
631 bool "Philips Nexperia PNX4008 Mobile"
634 select ARCH_USES_GETTIMEOFFSET
636 This enables support for Philips PNX4008 mobile platform.
639 bool "PXA2xx/PXA3xx-based"
642 select ARCH_HAS_CPUFREQ
645 select ARCH_REQUIRE_GPIOLIB
646 select GENERIC_CLOCKEVENTS
647 select HAVE_SCHED_CLOCK
652 select MULTI_IRQ_HANDLER
654 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
659 select GENERIC_CLOCKEVENTS
660 select ARCH_REQUIRE_GPIOLIB
663 Support for Qualcomm MSM/QSD based systems. This runs on the
664 apps processor of the MSM/QSD and depends on a shared memory
665 interface to the modem processor which runs the baseband
666 stack and controls some vital subsystems
667 (clock and power control, etc).
670 bool "Renesas SH-Mobile / R-Mobile"
673 select HAVE_MACH_CLKDEV
674 select GENERIC_CLOCKEVENTS
677 select MULTI_IRQ_HANDLER
678 select PM_GENERIC_DOMAINS if PM
679 select NEED_MACH_MEMORY_H
681 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
688 select ARCH_MAY_HAVE_PC_FDC
689 select HAVE_PATA_PLATFORM
692 select ARCH_SPARSEMEM_ENABLE
693 select ARCH_USES_GETTIMEOFFSET
694 select NEED_MACH_MEMORY_H
696 On the Acorn Risc-PC, Linux can support the internal IDE disk and
697 CD-ROM interface, serial and parallel port, and the floppy drive.
704 select ARCH_SPARSEMEM_ENABLE
706 select ARCH_HAS_CPUFREQ
708 select GENERIC_CLOCKEVENTS
710 select HAVE_SCHED_CLOCK
712 select ARCH_REQUIRE_GPIOLIB
713 select NEED_MACH_MEMORY_H
715 Support for StrongARM 11x0 based boards.
718 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
720 select ARCH_HAS_CPUFREQ
723 select ARCH_USES_GETTIMEOFFSET
724 select HAVE_S3C2410_I2C if I2C
726 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
727 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
728 the Samsung SMDK2410 development board (and derivatives).
730 Note, the S3C2416 and the S3C2450 are so close that they even share
731 the same SoC ID code. This means that there is no separate machine
732 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
735 bool "Samsung S3C64XX"
742 select ARCH_USES_GETTIMEOFFSET
743 select ARCH_HAS_CPUFREQ
744 select ARCH_REQUIRE_GPIOLIB
745 select SAMSUNG_CLKSRC
746 select SAMSUNG_IRQ_VIC_TIMER
747 select SAMSUNG_IRQ_UART
748 select S3C_GPIO_TRACK
750 select USB_ARCH_HAS_OHCI
751 select SAMSUNG_GPIOLIB_4BIT
752 select HAVE_S3C2410_I2C if I2C
753 select HAVE_S3C2410_WATCHDOG if WATCHDOG
755 Samsung S3C64XX series based systems
758 bool "Samsung S5P6440 S5P6450"
764 select HAVE_S3C2410_WATCHDOG if WATCHDOG
765 select GENERIC_CLOCKEVENTS
766 select HAVE_SCHED_CLOCK
767 select HAVE_S3C2410_I2C if I2C
768 select HAVE_S3C_RTC if RTC_CLASS
770 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
774 bool "Samsung S5PC100"
779 select ARM_L1_CACHE_SHIFT_6
780 select ARCH_USES_GETTIMEOFFSET
781 select HAVE_S3C2410_I2C if I2C
782 select HAVE_S3C_RTC if RTC_CLASS
783 select HAVE_S3C2410_WATCHDOG if WATCHDOG
785 Samsung S5PC100 series based systems
788 bool "Samsung S5PV210/S5PC110"
790 select ARCH_SPARSEMEM_ENABLE
791 select ARCH_HAS_HOLES_MEMORYMODEL
796 select ARM_L1_CACHE_SHIFT_6
797 select ARCH_HAS_CPUFREQ
798 select GENERIC_CLOCKEVENTS
799 select HAVE_SCHED_CLOCK
800 select HAVE_S3C2410_I2C if I2C
801 select HAVE_S3C_RTC if RTC_CLASS
802 select HAVE_S3C2410_WATCHDOG if WATCHDOG
803 select NEED_MACH_MEMORY_H
805 Samsung S5PV210/S5PC110 series based systems
808 bool "Samsung EXYNOS4"
810 select ARCH_SPARSEMEM_ENABLE
811 select ARCH_HAS_HOLES_MEMORYMODEL
815 select ARCH_HAS_CPUFREQ
816 select GENERIC_CLOCKEVENTS
817 select HAVE_S3C_RTC if RTC_CLASS
818 select HAVE_S3C2410_I2C if I2C
819 select HAVE_S3C2410_WATCHDOG if WATCHDOG
820 select NEED_MACH_MEMORY_H
822 Samsung EXYNOS4 series based systems
831 select ARCH_USES_GETTIMEOFFSET
832 select NEED_MACH_MEMORY_H
834 Support for the StrongARM based Digital DNARD machine, also known
835 as "Shark" (<http://www.shark-linux.de/shark.html>).
838 bool "Telechips TCC ARM926-based systems"
843 select GENERIC_CLOCKEVENTS
845 Support for Telechips TCC ARM926-based systems.
848 bool "ST-Ericsson U300 Series"
852 select HAVE_SCHED_CLOCK
856 select GENERIC_CLOCKEVENTS
858 select HAVE_MACH_CLKDEV
860 select NEED_MACH_MEMORY_H
862 Support for ST-Ericsson U300 series mobile platforms.
865 bool "ST-Ericsson U8500 Series"
868 select GENERIC_CLOCKEVENTS
870 select ARCH_REQUIRE_GPIOLIB
871 select ARCH_HAS_CPUFREQ
873 Support for ST-Ericsson's Ux500 architecture
876 bool "STMicroelectronics Nomadik"
881 select GENERIC_CLOCKEVENTS
882 select ARCH_REQUIRE_GPIOLIB
884 Support for the Nomadik platform by ST-Ericsson
888 select GENERIC_CLOCKEVENTS
889 select ARCH_REQUIRE_GPIOLIB
893 select GENERIC_ALLOCATOR
894 select GENERIC_IRQ_CHIP
895 select ARCH_HAS_HOLES_MEMORYMODEL
897 Support for TI's DaVinci platform.
902 select ARCH_REQUIRE_GPIOLIB
903 select ARCH_HAS_CPUFREQ
905 select GENERIC_CLOCKEVENTS
906 select HAVE_SCHED_CLOCK
907 select ARCH_HAS_HOLES_MEMORYMODEL
909 Support for TI's OMAP platform (OMAP1/2/3/4).
914 select ARCH_REQUIRE_GPIOLIB
917 select GENERIC_CLOCKEVENTS
920 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
923 bool "VIA/WonderMedia 85xx"
926 select ARCH_HAS_CPUFREQ
927 select GENERIC_CLOCKEVENTS
928 select ARCH_REQUIRE_GPIOLIB
931 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
934 bool "Xilinx Zynq ARM Cortex A9 Platform"
937 select GENERIC_CLOCKEVENTS
944 Support for Xilinx Zynq ARM Cortex A9 Platform
948 # This is sorted alphabetically by mach-* pathname. However, plat-*
949 # Kconfigs may be included either alphabetically (according to the
950 # plat- suffix) or along side the corresponding mach-* source.
952 source "arch/arm/mach-at91/Kconfig"
954 source "arch/arm/mach-bcmring/Kconfig"
956 source "arch/arm/mach-clps711x/Kconfig"
958 source "arch/arm/mach-cns3xxx/Kconfig"
960 source "arch/arm/mach-davinci/Kconfig"
962 source "arch/arm/mach-dove/Kconfig"
964 source "arch/arm/mach-ep93xx/Kconfig"
966 source "arch/arm/mach-footbridge/Kconfig"
968 source "arch/arm/mach-gemini/Kconfig"
970 source "arch/arm/mach-h720x/Kconfig"
972 source "arch/arm/mach-integrator/Kconfig"
974 source "arch/arm/mach-iop32x/Kconfig"
976 source "arch/arm/mach-iop33x/Kconfig"
978 source "arch/arm/mach-iop13xx/Kconfig"
980 source "arch/arm/mach-ixp4xx/Kconfig"
982 source "arch/arm/mach-ixp2000/Kconfig"
984 source "arch/arm/mach-ixp23xx/Kconfig"
986 source "arch/arm/mach-kirkwood/Kconfig"
988 source "arch/arm/mach-ks8695/Kconfig"
990 source "arch/arm/mach-lpc32xx/Kconfig"
992 source "arch/arm/mach-msm/Kconfig"
994 source "arch/arm/mach-mv78xx0/Kconfig"
996 source "arch/arm/plat-mxc/Kconfig"
998 source "arch/arm/mach-mxs/Kconfig"
1000 source "arch/arm/mach-netx/Kconfig"
1002 source "arch/arm/mach-nomadik/Kconfig"
1003 source "arch/arm/plat-nomadik/Kconfig"
1005 source "arch/arm/mach-nuc93x/Kconfig"
1007 source "arch/arm/plat-omap/Kconfig"
1009 source "arch/arm/mach-omap1/Kconfig"
1011 source "arch/arm/mach-omap2/Kconfig"
1013 source "arch/arm/mach-orion5x/Kconfig"
1015 source "arch/arm/mach-pxa/Kconfig"
1016 source "arch/arm/plat-pxa/Kconfig"
1018 source "arch/arm/mach-mmp/Kconfig"
1020 source "arch/arm/mach-realview/Kconfig"
1022 source "arch/arm/mach-sa1100/Kconfig"
1024 source "arch/arm/plat-samsung/Kconfig"
1025 source "arch/arm/plat-s3c24xx/Kconfig"
1026 source "arch/arm/plat-s5p/Kconfig"
1028 source "arch/arm/plat-spear/Kconfig"
1030 source "arch/arm/plat-tcc/Kconfig"
1033 source "arch/arm/mach-s3c2410/Kconfig"
1034 source "arch/arm/mach-s3c2412/Kconfig"
1035 source "arch/arm/mach-s3c2416/Kconfig"
1036 source "arch/arm/mach-s3c2440/Kconfig"
1037 source "arch/arm/mach-s3c2443/Kconfig"
1041 source "arch/arm/mach-s3c64xx/Kconfig"
1044 source "arch/arm/mach-s5p64x0/Kconfig"
1046 source "arch/arm/mach-s5pc100/Kconfig"
1048 source "arch/arm/mach-s5pv210/Kconfig"
1050 source "arch/arm/mach-exynos4/Kconfig"
1052 source "arch/arm/mach-shmobile/Kconfig"
1054 source "arch/arm/mach-tegra/Kconfig"
1056 source "arch/arm/mach-u300/Kconfig"
1058 source "arch/arm/mach-ux500/Kconfig"
1060 source "arch/arm/mach-versatile/Kconfig"
1062 source "arch/arm/mach-vexpress/Kconfig"
1063 source "arch/arm/plat-versatile/Kconfig"
1065 source "arch/arm/mach-vt8500/Kconfig"
1067 source "arch/arm/mach-w90x900/Kconfig"
1069 # Definitions to make life easier
1075 select GENERIC_CLOCKEVENTS
1076 select HAVE_SCHED_CLOCK
1081 select GENERIC_IRQ_CHIP
1082 select HAVE_SCHED_CLOCK
1087 config PLAT_VERSATILE
1090 config ARM_TIMER_SP804
1094 source arch/arm/mm/Kconfig
1097 bool "Enable iWMMXt support"
1098 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1099 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1101 Enable support for iWMMXt context switching at run time if
1102 running on a CPU that supports it.
1104 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1107 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1111 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1112 (!ARCH_OMAP3 || OMAP3_EMU)
1116 config MULTI_IRQ_HANDLER
1119 Allow each machine to specify it's own IRQ handler at run time.
1122 source "arch/arm/Kconfig-nommu"
1125 config ARM_ERRATA_411920
1126 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1127 depends on CPU_V6 || CPU_V6K
1129 Invalidation of the Instruction Cache operation can
1130 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1131 It does not affect the MPCore. This option enables the ARM Ltd.
1132 recommended workaround.
1134 config ARM_ERRATA_430973
1135 bool "ARM errata: Stale prediction on replaced interworking branch"
1138 This option enables the workaround for the 430973 Cortex-A8
1139 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1140 interworking branch is replaced with another code sequence at the
1141 same virtual address, whether due to self-modifying code or virtual
1142 to physical address re-mapping, Cortex-A8 does not recover from the
1143 stale interworking branch prediction. This results in Cortex-A8
1144 executing the new code sequence in the incorrect ARM or Thumb state.
1145 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1146 and also flushes the branch target cache at every context switch.
1147 Note that setting specific bits in the ACTLR register may not be
1148 available in non-secure mode.
1150 config ARM_ERRATA_458693
1151 bool "ARM errata: Processor deadlock when a false hazard is created"
1154 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1155 erratum. For very specific sequences of memory operations, it is
1156 possible for a hazard condition intended for a cache line to instead
1157 be incorrectly associated with a different cache line. This false
1158 hazard might then cause a processor deadlock. The workaround enables
1159 the L1 caching of the NEON accesses and disables the PLD instruction
1160 in the ACTLR register. Note that setting specific bits in the ACTLR
1161 register may not be available in non-secure mode.
1163 config ARM_ERRATA_460075
1164 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1167 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1168 erratum. Any asynchronous access to the L2 cache may encounter a
1169 situation in which recent store transactions to the L2 cache are lost
1170 and overwritten with stale memory contents from external memory. The
1171 workaround disables the write-allocate mode for the L2 cache via the
1172 ACTLR register. Note that setting specific bits in the ACTLR register
1173 may not be available in non-secure mode.
1175 config ARM_ERRATA_742230
1176 bool "ARM errata: DMB operation may be faulty"
1177 depends on CPU_V7 && SMP
1179 This option enables the workaround for the 742230 Cortex-A9
1180 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1181 between two write operations may not ensure the correct visibility
1182 ordering of the two writes. This workaround sets a specific bit in
1183 the diagnostic register of the Cortex-A9 which causes the DMB
1184 instruction to behave as a DSB, ensuring the correct behaviour of
1187 config ARM_ERRATA_742231
1188 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1189 depends on CPU_V7 && SMP
1191 This option enables the workaround for the 742231 Cortex-A9
1192 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1193 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1194 accessing some data located in the same cache line, may get corrupted
1195 data due to bad handling of the address hazard when the line gets
1196 replaced from one of the CPUs at the same time as another CPU is
1197 accessing it. This workaround sets specific bits in the diagnostic
1198 register of the Cortex-A9 which reduces the linefill issuing
1199 capabilities of the processor.
1201 config PL310_ERRATA_588369
1202 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1203 depends on CACHE_L2X0
1205 The PL310 L2 cache controller implements three types of Clean &
1206 Invalidate maintenance operations: by Physical Address
1207 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1208 They are architecturally defined to behave as the execution of a
1209 clean operation followed immediately by an invalidate operation,
1210 both performing to the same memory location. This functionality
1211 is not correctly implemented in PL310 as clean lines are not
1212 invalidated as a result of these operations.
1214 config ARM_ERRATA_720789
1215 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1216 depends on CPU_V7 && SMP
1218 This option enables the workaround for the 720789 Cortex-A9 (prior to
1219 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1220 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1221 As a consequence of this erratum, some TLB entries which should be
1222 invalidated are not, resulting in an incoherency in the system page
1223 tables. The workaround changes the TLB flushing routines to invalidate
1224 entries regardless of the ASID.
1226 config PL310_ERRATA_727915
1227 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1228 depends on CACHE_L2X0
1230 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1231 operation (offset 0x7FC). This operation runs in background so that
1232 PL310 can handle normal accesses while it is in progress. Under very
1233 rare circumstances, due to this erratum, write data can be lost when
1234 PL310 treats a cacheable write transaction during a Clean &
1235 Invalidate by Way operation.
1237 config ARM_ERRATA_743622
1238 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1241 This option enables the workaround for the 743622 Cortex-A9
1242 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1243 optimisation in the Cortex-A9 Store Buffer may lead to data
1244 corruption. This workaround sets a specific bit in the diagnostic
1245 register of the Cortex-A9 which disables the Store Buffer
1246 optimisation, preventing the defect from occurring. This has no
1247 visible impact on the overall performance or power consumption of the
1250 config ARM_ERRATA_751472
1251 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1252 depends on CPU_V7 && SMP
1254 This option enables the workaround for the 751472 Cortex-A9 (prior
1255 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1256 completion of a following broadcasted operation if the second
1257 operation is received by a CPU before the ICIALLUIS has completed,
1258 potentially leading to corrupted entries in the cache or TLB.
1260 config ARM_ERRATA_753970
1261 bool "ARM errata: cache sync operation may be faulty"
1262 depends on CACHE_PL310
1264 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1266 Under some condition the effect of cache sync operation on
1267 the store buffer still remains when the operation completes.
1268 This means that the store buffer is always asked to drain and
1269 this prevents it from merging any further writes. The workaround
1270 is to replace the normal offset of cache sync operation (0x730)
1271 by another offset targeting an unmapped PL310 register 0x740.
1272 This has the same effect as the cache sync operation: store buffer
1273 drain and waiting for all buffers empty.
1275 config ARM_ERRATA_754322
1276 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1279 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1280 r3p*) erratum. A speculative memory access may cause a page table walk
1281 which starts prior to an ASID switch but completes afterwards. This
1282 can populate the micro-TLB with a stale entry which may be hit with
1283 the new ASID. This workaround places two dsb instructions in the mm
1284 switching code so that no page table walks can cross the ASID switch.
1286 config ARM_ERRATA_754327
1287 bool "ARM errata: no automatic Store Buffer drain"
1288 depends on CPU_V7 && SMP
1290 This option enables the workaround for the 754327 Cortex-A9 (prior to
1291 r2p0) erratum. The Store Buffer does not have any automatic draining
1292 mechanism and therefore a livelock may occur if an external agent
1293 continuously polls a memory location waiting to observe an update.
1294 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1295 written polling loops from denying visibility of updates to memory.
1297 config ARM_ERRATA_364296
1298 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1299 depends on CPU_V6 && !SMP
1301 This options enables the workaround for the 364296 ARM1136
1302 r0p2 erratum (possible cache data corruption with
1303 hit-under-miss enabled). It sets the undocumented bit 31 in
1304 the auxiliary control register and the FI bit in the control
1305 register, thus disabling hit-under-miss without putting the
1306 processor into full low interrupt latency mode. ARM11MPCore
1309 config ARM_ERRATA_764369
1310 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1311 depends on CPU_V7 && SMP
1313 This option enables the workaround for erratum 764369
1314 affecting Cortex-A9 MPCore with two or more processors (all
1315 current revisions). Under certain timing circumstances, a data
1316 cache line maintenance operation by MVA targeting an Inner
1317 Shareable memory region may fail to proceed up to either the
1318 Point of Coherency or to the Point of Unification of the
1319 system. This workaround adds a DSB instruction before the
1320 relevant cache maintenance functions and sets a specific bit
1321 in the diagnostic control register of the SCU.
1325 source "arch/arm/common/Kconfig"
1335 Find out whether you have ISA slots on your motherboard. ISA is the
1336 name of a bus system, i.e. the way the CPU talks to the other stuff
1337 inside your box. Other bus systems are PCI, EISA, MicroChannel
1338 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1339 newer boards don't support it. If you have ISA, say Y, otherwise N.
1341 # Select ISA DMA controller support
1346 # Select ISA DMA interface
1351 bool "PCI support" if MIGHT_HAVE_PCI
1353 Find out whether you have a PCI motherboard. PCI is the name of a
1354 bus system, i.e. the way the CPU talks to the other stuff inside
1355 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1356 VESA. If you have PCI, say Y, otherwise N.
1362 config PCI_NANOENGINE
1363 bool "BSE nanoEngine PCI support"
1364 depends on SA1100_NANOENGINE
1366 Enable PCI on the BSE nanoEngine board.
1371 # Select the host bridge type
1372 config PCI_HOST_VIA82C505
1374 depends on PCI && ARCH_SHARK
1377 config PCI_HOST_ITE8152
1379 depends on PCI && MACH_ARMCORE
1383 source "drivers/pci/Kconfig"
1385 source "drivers/pcmcia/Kconfig"
1389 menu "Kernel Features"
1391 source "kernel/time/Kconfig"
1394 bool "Symmetric Multi-Processing"
1395 depends on CPU_V6K || CPU_V7
1396 depends on GENERIC_CLOCKEVENTS
1397 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1398 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1399 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1400 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1401 select USE_GENERIC_SMP_HELPERS
1402 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1404 This enables support for systems with more than one CPU. If you have
1405 a system with only one CPU, like most personal computers, say N. If
1406 you have a system with more than one CPU, say Y.
1408 If you say N here, the kernel will run on single and multiprocessor
1409 machines, but will use only one CPU of a multiprocessor machine. If
1410 you say Y here, the kernel will run on many, but not all, single
1411 processor machines. On a single processor machine, the kernel will
1412 run faster if you say N here.
1414 See also <file:Documentation/i386/IO-APIC.txt>,
1415 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1416 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1418 If you don't know what to do here, say N.
1421 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1422 depends on EXPERIMENTAL
1423 depends on SMP && !XIP_KERNEL
1426 SMP kernels contain instructions which fail on non-SMP processors.
1427 Enabling this option allows the kernel to modify itself to make
1428 these instructions safe. Disabling it allows about 1K of space
1431 If you don't know what to do here, say Y.
1436 This option enables support for the ARM system coherency unit
1443 This options enables support for the ARM timer and watchdog unit
1446 prompt "Memory split"
1449 Select the desired split between kernel and user memory.
1451 If you are not absolutely sure what you are doing, leave this
1455 bool "3G/1G user/kernel split"
1457 bool "2G/2G user/kernel split"
1459 bool "1G/3G user/kernel split"
1464 default 0x40000000 if VMSPLIT_1G
1465 default 0x80000000 if VMSPLIT_2G
1469 int "Maximum number of CPUs (2-32)"
1475 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1476 depends on SMP && HOTPLUG && EXPERIMENTAL
1478 Say Y here to experiment with turning CPUs off and on. CPUs
1479 can be controlled through /sys/devices/system/cpu.
1482 bool "Use local timer interrupts"
1485 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1487 Enable support for local timers on SMP platforms, rather then the
1488 legacy IPI broadcast method. Local timers allows the system
1489 accounting to be spread across the timer interval, preventing a
1490 "thundering herd" at every timer tick.
1492 source kernel/Kconfig.preempt
1496 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1497 ARCH_S5PV210 || ARCH_EXYNOS4
1498 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1499 default AT91_TIMER_HZ if ARCH_AT91
1500 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1503 config THUMB2_KERNEL
1504 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1505 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1507 select ARM_ASM_UNIFIED
1509 By enabling this option, the kernel will be compiled in
1510 Thumb-2 mode. A compiler/assembler that understand the unified
1511 ARM-Thumb syntax is needed.
1515 config THUMB2_AVOID_R_ARM_THM_JUMP11
1516 bool "Work around buggy Thumb-2 short branch relocations in gas"
1517 depends on THUMB2_KERNEL && MODULES
1520 Various binutils versions can resolve Thumb-2 branches to
1521 locally-defined, preemptible global symbols as short-range "b.n"
1522 branch instructions.
1524 This is a problem, because there's no guarantee the final
1525 destination of the symbol, or any candidate locations for a
1526 trampoline, are within range of the branch. For this reason, the
1527 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1528 relocation in modules at all, and it makes little sense to add
1531 The symptom is that the kernel fails with an "unsupported
1532 relocation" error when loading some modules.
1534 Until fixed tools are available, passing
1535 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1536 code which hits this problem, at the cost of a bit of extra runtime
1537 stack usage in some cases.
1539 The problem is described in more detail at:
1540 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1542 Only Thumb-2 kernels are affected.
1544 Unless you are sure your tools don't have this problem, say Y.
1546 config ARM_ASM_UNIFIED
1550 bool "Use the ARM EABI to compile the kernel"
1552 This option allows for the kernel to be compiled using the latest
1553 ARM ABI (aka EABI). This is only useful if you are using a user
1554 space environment that is also compiled with EABI.
1556 Since there are major incompatibilities between the legacy ABI and
1557 EABI, especially with regard to structure member alignment, this
1558 option also changes the kernel syscall calling convention to
1559 disambiguate both ABIs and allow for backward compatibility support
1560 (selected with CONFIG_OABI_COMPAT).
1562 To use this you need GCC version 4.0.0 or later.
1565 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1566 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1569 This option preserves the old syscall interface along with the
1570 new (ARM EABI) one. It also provides a compatibility layer to
1571 intercept syscalls that have structure arguments which layout
1572 in memory differs between the legacy ABI and the new ARM EABI
1573 (only for non "thumb" binaries). This option adds a tiny
1574 overhead to all syscalls and produces a slightly larger kernel.
1575 If you know you'll be using only pure EABI user space then you
1576 can say N here. If this option is not selected and you attempt
1577 to execute a legacy ABI binary then the result will be
1578 UNPREDICTABLE (in fact it can be predicted that it won't work
1579 at all). If in doubt say Y.
1581 config ARCH_HAS_HOLES_MEMORYMODEL
1584 config ARCH_SPARSEMEM_ENABLE
1587 config ARCH_SPARSEMEM_DEFAULT
1588 def_bool ARCH_SPARSEMEM_ENABLE
1590 config ARCH_SELECT_MEMORY_MODEL
1591 def_bool ARCH_SPARSEMEM_ENABLE
1593 config HAVE_ARCH_PFN_VALID
1594 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1597 bool "High Memory Support"
1600 The address space of ARM processors is only 4 Gigabytes large
1601 and it has to accommodate user address space, kernel address
1602 space as well as some memory mapped IO. That means that, if you
1603 have a large amount of physical memory and/or IO, not all of the
1604 memory can be "permanently mapped" by the kernel. The physical
1605 memory that is not permanently mapped is called "high memory".
1607 Depending on the selected kernel/user memory split, minimum
1608 vmalloc space and actual amount of RAM, you may not need this
1609 option which should result in a slightly faster kernel.
1614 bool "Allocate 2nd-level pagetables from highmem"
1617 config HW_PERF_EVENTS
1618 bool "Enable hardware performance counter support for perf events"
1619 depends on PERF_EVENTS && CPU_HAS_PMU
1622 Enable hardware performance counter support for perf events. If
1623 disabled, perf events will use software events only.
1627 config FORCE_MAX_ZONEORDER
1628 int "Maximum zone order" if ARCH_SHMOBILE
1629 range 11 64 if ARCH_SHMOBILE
1630 default "9" if SA1111
1633 The kernel memory allocator divides physically contiguous memory
1634 blocks into "zones", where each zone is a power of two number of
1635 pages. This option selects the largest power of two that the kernel
1636 keeps in the memory allocator. If you need to allocate very large
1637 blocks of physically contiguous memory, then you may need to
1638 increase this value.
1640 This config option is actually maximum order plus one. For example,
1641 a value of 11 means that the largest free memory block is 2^10 pages.
1644 bool "Timer and CPU usage LEDs"
1645 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1646 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1647 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1648 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1649 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1650 ARCH_AT91 || ARCH_DAVINCI || \
1651 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1653 If you say Y here, the LEDs on your machine will be used
1654 to provide useful information about your current system status.
1656 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1657 be able to select which LEDs are active using the options below. If
1658 you are compiling a kernel for the EBSA-110 or the LART however, the
1659 red LED will simply flash regularly to indicate that the system is
1660 still functional. It is safe to say Y here if you have a CATS
1661 system, but the driver will do nothing.
1664 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1665 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1666 || MACH_OMAP_PERSEUS2
1668 depends on !GENERIC_CLOCKEVENTS
1669 default y if ARCH_EBSA110
1671 If you say Y here, one of the system LEDs (the green one on the
1672 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1673 will flash regularly to indicate that the system is still
1674 operational. This is mainly useful to kernel hackers who are
1675 debugging unstable kernels.
1677 The LART uses the same LED for both Timer LED and CPU usage LED
1678 functions. You may choose to use both, but the Timer LED function
1679 will overrule the CPU usage LED.
1682 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1684 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1685 || MACH_OMAP_PERSEUS2
1688 If you say Y here, the red LED will be used to give a good real
1689 time indication of CPU usage, by lighting whenever the idle task
1690 is not currently executing.
1692 The LART uses the same LED for both Timer LED and CPU usage LED
1693 functions. You may choose to use both, but the Timer LED function
1694 will overrule the CPU usage LED.
1696 config ALIGNMENT_TRAP
1698 depends on CPU_CP15_MMU
1699 default y if !ARCH_EBSA110
1700 select HAVE_PROC_CPU if PROC_FS
1702 ARM processors cannot fetch/store information which is not
1703 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1704 address divisible by 4. On 32-bit ARM processors, these non-aligned
1705 fetch/store instructions will be emulated in software if you say
1706 here, which has a severe performance impact. This is necessary for
1707 correct operation of some network protocols. With an IP-only
1708 configuration it is safe to say N, otherwise say Y.
1710 config UACCESS_WITH_MEMCPY
1711 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1712 depends on MMU && EXPERIMENTAL
1713 default y if CPU_FEROCEON
1715 Implement faster copy_to_user and clear_user methods for CPU
1716 cores where a 8-word STM instruction give significantly higher
1717 memory write throughput than a sequence of individual 32bit stores.
1719 A possible side effect is a slight increase in scheduling latency
1720 between threads sharing the same address space if they invoke
1721 such copy operations with large buffers.
1723 However, if the CPU data cache is using a write-allocate mode,
1724 this option is unlikely to provide any performance gain.
1728 prompt "Enable seccomp to safely compute untrusted bytecode"
1730 This kernel feature is useful for number crunching applications
1731 that may need to compute untrusted bytecode during their
1732 execution. By using pipes or other transports made available to
1733 the process as file descriptors supporting the read/write
1734 syscalls, it's possible to isolate those applications in
1735 their own address space using seccomp. Once seccomp is
1736 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1737 and the task is only allowed to execute a few safe syscalls
1738 defined by each seccomp mode.
1740 config CC_STACKPROTECTOR
1741 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1742 depends on EXPERIMENTAL
1744 This option turns on the -fstack-protector GCC feature. This
1745 feature puts, at the beginning of functions, a canary value on
1746 the stack just before the return address, and validates
1747 the value just before actually returning. Stack based buffer
1748 overflows (that need to overwrite this return address) now also
1749 overwrite the canary, which gets detected and the attack is then
1750 neutralized via a kernel panic.
1751 This feature requires gcc version 4.2 or above.
1753 config DEPRECATED_PARAM_STRUCT
1754 bool "Provide old way to pass kernel parameters"
1756 This was deprecated in 2001 and announced to live on for 5 years.
1757 Some old boot loaders still use this way.
1764 bool "Flattened Device Tree support"
1766 select OF_EARLY_FLATTREE
1769 Include support for flattened device tree machine descriptions.
1771 # Compressed boot loader in ROM. Yes, we really want to ask about
1772 # TEXT and BSS so we preserve their values in the config files.
1773 config ZBOOT_ROM_TEXT
1774 hex "Compressed ROM boot loader base address"
1777 The physical address at which the ROM-able zImage is to be
1778 placed in the target. Platforms which normally make use of
1779 ROM-able zImage formats normally set this to a suitable
1780 value in their defconfig file.
1782 If ZBOOT_ROM is not enabled, this has no effect.
1784 config ZBOOT_ROM_BSS
1785 hex "Compressed ROM boot loader BSS address"
1788 The base address of an area of read/write memory in the target
1789 for the ROM-able zImage which must be available while the
1790 decompressor is running. It must be large enough to hold the
1791 entire decompressed kernel plus an additional 128 KiB.
1792 Platforms which normally make use of ROM-able zImage formats
1793 normally set this to a suitable value in their defconfig file.
1795 If ZBOOT_ROM is not enabled, this has no effect.
1798 bool "Compressed boot loader in ROM/flash"
1799 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1801 Say Y here if you intend to execute your compressed kernel image
1802 (zImage) directly from ROM or flash. If unsure, say N.
1805 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1806 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1807 default ZBOOT_ROM_NONE
1809 Include experimental SD/MMC loading code in the ROM-able zImage.
1810 With this enabled it is possible to write the the ROM-able zImage
1811 kernel image to an MMC or SD card and boot the kernel straight
1812 from the reset vector. At reset the processor Mask ROM will load
1813 the first part of the the ROM-able zImage which in turn loads the
1814 rest the kernel image to RAM.
1816 config ZBOOT_ROM_NONE
1817 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1819 Do not load image from SD or MMC
1821 config ZBOOT_ROM_MMCIF
1822 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1824 Load image from MMCIF hardware block.
1826 config ZBOOT_ROM_SH_MOBILE_SDHI
1827 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1829 Load image from SDHI hardware block
1834 string "Default kernel command string"
1837 On some architectures (EBSA110 and CATS), there is currently no way
1838 for the boot loader to pass arguments to the kernel. For these
1839 architectures, you should supply some command-line options at build
1840 time by entering them here. As a minimum, you should specify the
1841 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1844 prompt "Kernel command line type" if CMDLINE != ""
1845 default CMDLINE_FROM_BOOTLOADER
1847 config CMDLINE_FROM_BOOTLOADER
1848 bool "Use bootloader kernel arguments if available"
1850 Uses the command-line options passed by the boot loader. If
1851 the boot loader doesn't provide any, the default kernel command
1852 string provided in CMDLINE will be used.
1854 config CMDLINE_EXTEND
1855 bool "Extend bootloader kernel arguments"
1857 The command-line arguments provided by the boot loader will be
1858 appended to the default kernel command string.
1860 config CMDLINE_FORCE
1861 bool "Always use the default kernel command string"
1863 Always use the default kernel command string, even if the boot
1864 loader passes other arguments to the kernel.
1865 This is useful if you cannot or don't want to change the
1866 command-line options your boot loader passes to the kernel.
1870 bool "Kernel Execute-In-Place from ROM"
1871 depends on !ZBOOT_ROM
1873 Execute-In-Place allows the kernel to run from non-volatile storage
1874 directly addressable by the CPU, such as NOR flash. This saves RAM
1875 space since the text section of the kernel is not loaded from flash
1876 to RAM. Read-write sections, such as the data section and stack,
1877 are still copied to RAM. The XIP kernel is not compressed since
1878 it has to run directly from flash, so it will take more space to
1879 store it. The flash address used to link the kernel object files,
1880 and for storing it, is configuration dependent. Therefore, if you
1881 say Y here, you must know the proper physical address where to
1882 store the kernel image depending on your own flash memory usage.
1884 Also note that the make target becomes "make xipImage" rather than
1885 "make zImage" or "make Image". The final kernel binary to put in
1886 ROM memory will be arch/arm/boot/xipImage.
1890 config XIP_PHYS_ADDR
1891 hex "XIP Kernel Physical Location"
1892 depends on XIP_KERNEL
1893 default "0x00080000"
1895 This is the physical address in your flash memory the kernel will
1896 be linked for and stored to. This address is dependent on your
1900 bool "Kexec system call (EXPERIMENTAL)"
1901 depends on EXPERIMENTAL
1903 kexec is a system call that implements the ability to shutdown your
1904 current kernel, and to start another kernel. It is like a reboot
1905 but it is independent of the system firmware. And like a reboot
1906 you can start any kernel with it, not just Linux.
1908 It is an ongoing process to be certain the hardware in a machine
1909 is properly shutdown, so do not be surprised if this code does not
1910 initially work for you. It may help to enable device hotplugging
1914 bool "Export atags in procfs"
1918 Should the atags used to boot the kernel be exported in an "atags"
1919 file in procfs. Useful with kexec.
1922 bool "Build kdump crash kernel (EXPERIMENTAL)"
1923 depends on EXPERIMENTAL
1925 Generate crash dump after being started by kexec. This should
1926 be normally only set in special crash dump kernels which are
1927 loaded in the main kernel with kexec-tools into a specially
1928 reserved region and then later executed after a crash by
1929 kdump/kexec. The crash dump kernel must be compiled to a
1930 memory address not used by the main kernel
1932 For more details see Documentation/kdump/kdump.txt
1934 config AUTO_ZRELADDR
1935 bool "Auto calculation of the decompressed kernel image address"
1936 depends on !ZBOOT_ROM && !ARCH_U300
1938 ZRELADDR is the physical address where the decompressed kernel
1939 image will be placed. If AUTO_ZRELADDR is selected, the address
1940 will be determined at run-time by masking the current IP with
1941 0xf8000000. This assumes the zImage being placed in the first 128MB
1942 from start of memory.
1946 menu "CPU Power Management"
1950 source "drivers/cpufreq/Kconfig"
1953 tristate "CPUfreq driver for i.MX CPUs"
1954 depends on ARCH_MXC && CPU_FREQ
1956 This enables the CPUfreq driver for i.MX CPUs.
1958 config CPU_FREQ_SA1100
1961 config CPU_FREQ_SA1110
1964 config CPU_FREQ_INTEGRATOR
1965 tristate "CPUfreq driver for ARM Integrator CPUs"
1966 depends on ARCH_INTEGRATOR && CPU_FREQ
1969 This enables the CPUfreq driver for ARM Integrator CPUs.
1971 For details, take a look at <file:Documentation/cpu-freq>.
1977 depends on CPU_FREQ && ARCH_PXA && PXA25x
1979 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1984 Internal configuration node for common cpufreq on Samsung SoC
1986 config CPU_FREQ_S3C24XX
1987 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1988 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1991 This enables the CPUfreq driver for the Samsung S3C24XX family
1994 For details, take a look at <file:Documentation/cpu-freq>.
1998 config CPU_FREQ_S3C24XX_PLL
1999 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2000 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2002 Compile in support for changing the PLL frequency from the
2003 S3C24XX series CPUfreq driver. The PLL takes time to settle
2004 after a frequency change, so by default it is not enabled.
2006 This also means that the PLL tables for the selected CPU(s) will
2007 be built which may increase the size of the kernel image.
2009 config CPU_FREQ_S3C24XX_DEBUG
2010 bool "Debug CPUfreq Samsung driver core"
2011 depends on CPU_FREQ_S3C24XX
2013 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2015 config CPU_FREQ_S3C24XX_IODEBUG
2016 bool "Debug CPUfreq Samsung driver IO timing"
2017 depends on CPU_FREQ_S3C24XX
2019 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2021 config CPU_FREQ_S3C24XX_DEBUGFS
2022 bool "Export debugfs for CPUFreq"
2023 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2025 Export status information via debugfs.
2029 source "drivers/cpuidle/Kconfig"
2033 menu "Floating point emulation"
2035 comment "At least one emulation must be selected"
2038 bool "NWFPE math emulation"
2039 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2041 Say Y to include the NWFPE floating point emulator in the kernel.
2042 This is necessary to run most binaries. Linux does not currently
2043 support floating point hardware so you need to say Y here even if
2044 your machine has an FPA or floating point co-processor podule.
2046 You may say N here if you are going to load the Acorn FPEmulator
2047 early in the bootup.
2050 bool "Support extended precision"
2051 depends on FPE_NWFPE
2053 Say Y to include 80-bit support in the kernel floating-point
2054 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2055 Note that gcc does not generate 80-bit operations by default,
2056 so in most cases this option only enlarges the size of the
2057 floating point emulator without any good reason.
2059 You almost surely want to say N here.
2062 bool "FastFPE math emulation (EXPERIMENTAL)"
2063 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2065 Say Y here to include the FAST floating point emulator in the kernel.
2066 This is an experimental much faster emulator which now also has full
2067 precision for the mantissa. It does not support any exceptions.
2068 It is very simple, and approximately 3-6 times faster than NWFPE.
2070 It should be sufficient for most programs. It may be not suitable
2071 for scientific calculations, but you have to check this for yourself.
2072 If you do not feel you need a faster FP emulation you should better
2076 bool "VFP-format floating point maths"
2077 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2079 Say Y to include VFP support code in the kernel. This is needed
2080 if your hardware includes a VFP unit.
2082 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2083 release notes and additional status information.
2085 Say N if your target does not have VFP hardware.
2093 bool "Advanced SIMD (NEON) Extension support"
2094 depends on VFPv3 && CPU_V7
2096 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2101 menu "Userspace binary formats"
2103 source "fs/Kconfig.binfmt"
2106 tristate "RISC OS personality"
2109 Say Y here to include the kernel code necessary if you want to run
2110 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2111 experimental; if this sounds frightening, say N and sleep in peace.
2112 You can also say M here to compile this support as a module (which
2113 will be called arthur).
2117 menu "Power management options"
2119 source "kernel/power/Kconfig"
2121 config ARCH_SUSPEND_POSSIBLE
2122 depends on !ARCH_S5PC100
2123 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2124 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2129 source "net/Kconfig"
2131 source "drivers/Kconfig"
2135 source "arch/arm/Kconfig.debug"
2137 source "security/Kconfig"
2139 source "crypto/Kconfig"
2141 source "lib/Kconfig"