4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_PCI_IOMAP
16 select GENERIC_SMP_IDLE_THREAD
17 select GENERIC_STRNCPY_FROM_USER
18 select GENERIC_STRNLEN_USER
19 select HARDIRQS_SW_RESEND
21 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
23 select HAVE_ARCH_SECCOMP_FILTER
24 select HAVE_ARCH_TRACEHOOK
26 select HAVE_C_RECORDMCOUNT
27 select HAVE_DEBUG_KMEMLEAK
28 select HAVE_DMA_API_DEBUG
30 select HAVE_DMA_CONTIGUOUS if MMU
31 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
32 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
33 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
34 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
35 select HAVE_GENERIC_DMA_COHERENT
36 select HAVE_GENERIC_HARDIRQS
37 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
38 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
53 select PERF_USE_VMALLOC
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
58 select CLONE_BACKWARDS
60 The ARM series is a line of low-power-consumption RISC chip designs
61 licensed by ARM Ltd and targeted at embedded applications and
62 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
63 manufactured, but legacy ARM-based PC hardware remains popular in
64 Europe. There is an ARM Linux project with a web page at
65 <http://www.arm.linux.org.uk/>.
67 config ARM_HAS_SG_CHAIN
70 config NEED_SG_DMA_LENGTH
73 config ARM_DMA_USE_IOMMU
75 select ARM_HAS_SG_CHAIN
76 select NEED_SG_DMA_LENGTH
84 config SYS_SUPPORTS_APM_EMULATION
92 select GENERIC_ALLOCATOR
103 The Extended Industry Standard Architecture (EISA) bus was
104 developed as an open alternative to the IBM MicroChannel bus.
106 The EISA bus provided some of the features of the IBM MicroChannel
107 bus while maintaining backward compatibility with cards made for
108 the older ISA bus. The EISA bus saw limited use between 1988 and
109 1995 when it was made obsolete by the PCI bus.
111 Say Y here if you are building a kernel for an EISA-based machine.
118 config STACKTRACE_SUPPORT
122 config HAVE_LATENCYTOP_SUPPORT
127 config LOCKDEP_SUPPORT
131 config TRACE_IRQFLAGS_SUPPORT
135 config RWSEM_GENERIC_SPINLOCK
139 config RWSEM_XCHGADD_ALGORITHM
142 config ARCH_HAS_ILOG2_U32
145 config ARCH_HAS_ILOG2_U64
148 config ARCH_HAS_CPUFREQ
151 Internal node to signify that the ARCH has CPUFREQ support
152 and that the relevant menu configurations are displayed for
155 config GENERIC_HWEIGHT
159 config GENERIC_CALIBRATE_DELAY
163 config ARCH_MAY_HAVE_PC_FDC
169 config NEED_DMA_MAP_STATE
172 config ARCH_HAS_DMA_SET_COHERENT_MASK
175 config GENERIC_ISA_DMA
181 config NEED_RET_TO_USER
189 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
190 default DRAM_BASE if REMAP_VECTORS_TO_RAM
193 The base address of exception vectors.
195 config ARM_PATCH_PHYS_VIRT
196 bool "Patch physical to virtual translations at runtime" if EMBEDDED
198 depends on !XIP_KERNEL && MMU
199 depends on !ARCH_REALVIEW || !SPARSEMEM
201 Patch phys-to-virt and virt-to-phys translation functions at
202 boot and module load time according to the position of the
203 kernel in system memory.
205 This can only be used with non-XIP MMU kernels where the base
206 of physical memory is at a 16MB boundary.
208 Only disable this option if you know that you do not require
209 this feature (eg, building a kernel for a single machine) and
210 you need to shrink the kernel to the minimal size.
212 config NEED_MACH_GPIO_H
215 Select this when mach/gpio.h is required to provide special
216 definitions for this platform. The need for mach/gpio.h should
217 be avoided when possible.
219 config NEED_MACH_IO_H
222 Select this when mach/io.h is required to provide special
223 definitions for this platform. The need for mach/io.h should
224 be avoided when possible.
226 config NEED_MACH_MEMORY_H
229 Select this when mach/memory.h is required to provide special
230 definitions for this platform. The need for mach/memory.h should
231 be avoided when possible.
234 hex "Physical address of main memory" if MMU
235 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
236 default DRAM_BASE if !MMU
238 Please provide the physical address corresponding to the
239 location of main memory in your system.
245 source "init/Kconfig"
247 source "kernel/Kconfig.freezer"
252 bool "MMU-based Paged Memory Management Support"
255 Select if you want MMU-based virtualised addressing space
256 support by paged memory management. If unsure, say 'Y'.
259 # The "ARM system type" choice list is ordered alphabetically by option
260 # text. Please add new entries in the option alphabetic order.
263 prompt "ARM system type"
264 default ARCH_MULTIPLATFORM
266 config ARCH_MULTIPLATFORM
267 bool "Allow multiple platforms to be selected"
269 select ARM_PATCH_PHYS_VIRT
272 select MULTI_IRQ_HANDLER
276 config ARCH_INTEGRATOR
277 bool "ARM Ltd. Integrator family"
278 select ARCH_HAS_CPUFREQ
281 select COMMON_CLK_VERSATILE
282 select GENERIC_CLOCKEVENTS
285 select MULTI_IRQ_HANDLER
286 select NEED_MACH_MEMORY_H
287 select PLAT_VERSATILE
289 select VERSATILE_FPGA_IRQ
291 Support for ARM's Integrator platform.
294 bool "ARM Ltd. RealView family"
295 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select ARM_TIMER_SP804
299 select COMMON_CLK_VERSATILE
300 select GENERIC_CLOCKEVENTS
301 select GPIO_PL061 if GPIOLIB
303 select NEED_MACH_MEMORY_H
304 select PLAT_VERSATILE
305 select PLAT_VERSATILE_CLCD
307 This enables support for ARM Ltd RealView boards.
309 config ARCH_VERSATILE
310 bool "ARM Ltd. Versatile family"
311 select ARCH_WANT_OPTIONAL_GPIOLIB
313 select ARM_TIMER_SP804
316 select GENERIC_CLOCKEVENTS
317 select HAVE_MACH_CLKDEV
319 select PLAT_VERSATILE
320 select PLAT_VERSATILE_CLCD
321 select PLAT_VERSATILE_CLOCK
322 select VERSATILE_FPGA_IRQ
324 This enables support for ARM Ltd Versatile board.
328 select ARCH_REQUIRE_GPIOLIB
332 select NEED_MACH_GPIO_H
333 select NEED_MACH_IO_H if PCCARD
335 select PINCTRL_AT91 if USE_OF
337 This enables support for systems based on Atmel
338 AT91RM9200 and AT91SAM9* processors.
341 bool "Broadcom BCM2835 family"
342 select ARCH_REQUIRE_GPIOLIB
344 select ARM_ERRATA_411920
345 select ARM_TIMER_SP804
349 select GENERIC_CLOCKEVENTS
351 select MULTI_IRQ_HANDLER
353 select PINCTRL_BCM2835
357 This enables support for the Broadcom BCM2835 SoC. This SoC is
358 use in the Raspberry Pi, and Roku 2 devices.
361 bool "Cavium Networks CNS3XXX family"
364 select GENERIC_CLOCKEVENTS
365 select MIGHT_HAVE_CACHE_L2X0
366 select MIGHT_HAVE_PCI
367 select PCI_DOMAINS if PCI
369 Support for Cavium Networks CNS3XXX platform.
372 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
373 select ARCH_REQUIRE_GPIOLIB
378 select GENERIC_CLOCKEVENTS
379 select MULTI_IRQ_HANDLER
380 select NEED_MACH_MEMORY_H
383 Support for Cirrus Logic 711x/721x/731x based boards.
386 bool "Cortina Systems Gemini"
387 select ARCH_REQUIRE_GPIOLIB
388 select ARCH_USES_GETTIMEOFFSET
391 Support for the Cortina Systems Gemini family SoCs
395 select ARCH_REQUIRE_GPIOLIB
397 select GENERIC_CLOCKEVENTS
398 select GENERIC_IRQ_CHIP
399 select MIGHT_HAVE_CACHE_L2X0
405 Support for CSR SiRFprimaII/Marco/Polo platforms
409 select ARCH_USES_GETTIMEOFFSET
412 select NEED_MACH_IO_H
413 select NEED_MACH_MEMORY_H
416 This is an evaluation board for the StrongARM processor available
417 from Digital. It has limited hardware on-board, including an
418 Ethernet interface, two PCMCIA sockets, two serial ports and a
423 select ARCH_HAS_HOLES_MEMORYMODEL
424 select ARCH_REQUIRE_GPIOLIB
425 select ARCH_USES_GETTIMEOFFSET
430 select NEED_MACH_MEMORY_H
432 This enables support for the Cirrus EP93xx series of CPUs.
434 config ARCH_FOOTBRIDGE
438 select GENERIC_CLOCKEVENTS
440 select NEED_MACH_IO_H if !MMU
441 select NEED_MACH_MEMORY_H
443 Support for systems based on the DC21285 companion chip
444 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
447 bool "Freescale MXS-based"
448 select ARCH_REQUIRE_GPIOLIB
452 select GENERIC_CLOCKEVENTS
453 select HAVE_CLK_PREPARE
454 select MULTI_IRQ_HANDLER
459 Support for Freescale MXS-based family of processors
462 bool "Hilscher NetX based"
466 select GENERIC_CLOCKEVENTS
468 This enables support for systems based on the Hilscher NetX Soc
471 bool "Hynix HMS720x-based"
472 select ARCH_USES_GETTIMEOFFSET
476 This enables support for systems based on the Hynix HMS720x
481 select ARCH_SUPPORTS_MSI
483 select NEED_MACH_MEMORY_H
484 select NEED_RET_TO_USER
489 Support for Intel's IOP13XX (XScale) family of processors.
494 select ARCH_REQUIRE_GPIOLIB
496 select NEED_MACH_GPIO_H
497 select NEED_RET_TO_USER
501 Support for Intel's 80219 and IOP32X (XScale) family of
507 select ARCH_REQUIRE_GPIOLIB
509 select NEED_MACH_GPIO_H
510 select NEED_RET_TO_USER
514 Support for Intel's IOP33X (XScale) family of processors.
519 select ARCH_HAS_DMA_SET_COHERENT_MASK
520 select ARCH_REQUIRE_GPIOLIB
523 select DMABOUNCE if PCI
524 select GENERIC_CLOCKEVENTS
525 select MIGHT_HAVE_PCI
526 select NEED_MACH_IO_H
528 Support for Intel's IXP4XX (XScale) family of processors.
532 select ARCH_REQUIRE_GPIOLIB
533 select COMMON_CLK_DOVE
535 select GENERIC_CLOCKEVENTS
536 select MIGHT_HAVE_PCI
539 select PLAT_ORION_LEGACY
540 select USB_ARCH_HAS_EHCI
542 Support for the Marvell Dove SoC 88AP510
545 bool "Marvell Kirkwood"
546 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
552 select PINCTRL_KIRKWOOD
553 select PLAT_ORION_LEGACY
555 Support for the following Marvell Kirkwood series SoCs:
556 88F6180, 88F6192 and 88F6281.
559 bool "Marvell MV78xx0"
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
564 select PLAT_ORION_LEGACY
566 Support for the following Marvell MV78xx0 series SoCs:
572 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
576 select PLAT_ORION_LEGACY
578 Support for the following Marvell Orion 5x series SoCs:
579 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
580 Orion-2 (5281), Orion-1-90 (6183).
583 bool "Marvell PXA168/910/MMP2"
585 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_ALLOCATOR
588 select GENERIC_CLOCKEVENTS
591 select NEED_MACH_GPIO_H
596 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
599 bool "Micrel/Kendin KS8695"
600 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
604 select NEED_MACH_MEMORY_H
606 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
607 System-on-Chip devices.
610 bool "Nuvoton W90X900 CPU"
611 select ARCH_REQUIRE_GPIOLIB
615 select GENERIC_CLOCKEVENTS
617 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
618 At present, the w90x900 has been renamed nuc900, regarding
619 the ARM series product line, you can login the following
620 link address to know more.
622 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
623 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
627 select ARCH_REQUIRE_GPIOLIB
632 select GENERIC_CLOCKEVENTS
635 select USB_ARCH_HAS_OHCI
638 Support for the NXP LPC32XX family of processors
642 select ARCH_HAS_CPUFREQ
646 select GENERIC_CLOCKEVENTS
650 select MIGHT_HAVE_CACHE_L2X0
654 This enables support for NVIDIA Tegra based systems (Tegra APX,
655 Tegra 6xx and Tegra 2 series).
658 bool "PXA2xx/PXA3xx-based"
660 select ARCH_HAS_CPUFREQ
662 select ARCH_REQUIRE_GPIOLIB
663 select ARM_CPU_SUSPEND if PM
667 select GENERIC_CLOCKEVENTS
670 select MULTI_IRQ_HANDLER
671 select NEED_MACH_GPIO_H
675 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
679 select ARCH_REQUIRE_GPIOLIB
681 select GENERIC_CLOCKEVENTS
684 Support for Qualcomm MSM/QSD based systems. This runs on the
685 apps processor of the MSM/QSD and depends on a shared memory
686 interface to the modem processor which runs the baseband
687 stack and controls some vital subsystems
688 (clock and power control, etc).
691 bool "Renesas SH-Mobile / R-Mobile"
693 select GENERIC_CLOCKEVENTS
695 select HAVE_MACH_CLKDEV
697 select MIGHT_HAVE_CACHE_L2X0
698 select MULTI_IRQ_HANDLER
699 select NEED_MACH_MEMORY_H
701 select PM_GENERIC_DOMAINS if PM
704 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
709 select ARCH_MAY_HAVE_PC_FDC
710 select ARCH_SPARSEMEM_ENABLE
711 select ARCH_USES_GETTIMEOFFSET
714 select HAVE_PATA_PLATFORM
716 select NEED_MACH_IO_H
717 select NEED_MACH_MEMORY_H
720 On the Acorn Risc-PC, Linux can support the internal IDE disk and
721 CD-ROM interface, serial and parallel port, and the floppy drive.
725 select ARCH_HAS_CPUFREQ
727 select ARCH_REQUIRE_GPIOLIB
728 select ARCH_SPARSEMEM_ENABLE
733 select GENERIC_CLOCKEVENTS
736 select NEED_MACH_GPIO_H
737 select NEED_MACH_MEMORY_H
740 Support for StrongARM 11x0 based boards.
743 bool "Samsung S3C24XX SoCs"
744 select ARCH_HAS_CPUFREQ
745 select ARCH_USES_GETTIMEOFFSET
749 select HAVE_S3C2410_I2C if I2C
750 select HAVE_S3C2410_WATCHDOG if WATCHDOG
751 select HAVE_S3C_RTC if RTC_CLASS
752 select NEED_MACH_GPIO_H
753 select NEED_MACH_IO_H
755 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
756 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
757 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
758 Samsung SMDK2410 development board (and derivatives).
761 bool "Samsung S3C64XX"
762 select ARCH_HAS_CPUFREQ
763 select ARCH_REQUIRE_GPIOLIB
764 select ARCH_USES_GETTIMEOFFSET
769 select HAVE_S3C2410_I2C if I2C
770 select HAVE_S3C2410_WATCHDOG if WATCHDOG
772 select NEED_MACH_GPIO_H
776 select S3C_GPIO_TRACK
777 select SAMSUNG_CLKSRC
778 select SAMSUNG_GPIOLIB_4BIT
779 select SAMSUNG_IRQ_VIC_TIMER
780 select USB_ARCH_HAS_OHCI
782 Samsung S3C64XX series based systems
785 bool "Samsung S5P6440 S5P6450"
789 select GENERIC_CLOCKEVENTS
792 select HAVE_S3C2410_I2C if I2C
793 select HAVE_S3C2410_WATCHDOG if WATCHDOG
794 select HAVE_S3C_RTC if RTC_CLASS
795 select NEED_MACH_GPIO_H
797 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
801 bool "Samsung S5PC100"
802 select ARCH_USES_GETTIMEOFFSET
807 select HAVE_S3C2410_I2C if I2C
808 select HAVE_S3C2410_WATCHDOG if WATCHDOG
809 select HAVE_S3C_RTC if RTC_CLASS
810 select NEED_MACH_GPIO_H
812 Samsung S5PC100 series based systems
815 bool "Samsung S5PV210/S5PC110"
816 select ARCH_HAS_CPUFREQ
817 select ARCH_HAS_HOLES_MEMORYMODEL
818 select ARCH_SPARSEMEM_ENABLE
822 select GENERIC_CLOCKEVENTS
825 select HAVE_S3C2410_I2C if I2C
826 select HAVE_S3C2410_WATCHDOG if WATCHDOG
827 select HAVE_S3C_RTC if RTC_CLASS
828 select NEED_MACH_GPIO_H
829 select NEED_MACH_MEMORY_H
831 Samsung S5PV210/S5PC110 series based systems
834 bool "Samsung EXYNOS"
835 select ARCH_HAS_CPUFREQ
836 select ARCH_HAS_HOLES_MEMORYMODEL
837 select ARCH_SPARSEMEM_ENABLE
840 select GENERIC_CLOCKEVENTS
843 select HAVE_S3C2410_I2C if I2C
844 select HAVE_S3C2410_WATCHDOG if WATCHDOG
845 select HAVE_S3C_RTC if RTC_CLASS
846 select NEED_MACH_GPIO_H
847 select NEED_MACH_MEMORY_H
849 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
853 select ARCH_USES_GETTIMEOFFSET
857 select NEED_MACH_MEMORY_H
861 Support for the StrongARM based Digital DNARD machine, also known
862 as "Shark" (<http://www.shark-linux.de/shark.html>).
865 bool "ST-Ericsson U300 Series"
867 select ARCH_REQUIRE_GPIOLIB
869 select ARM_PATCH_PHYS_VIRT
875 select GENERIC_CLOCKEVENTS
880 Support for ST-Ericsson U300 series mobile platforms.
883 bool "ST-Ericsson U8500 Series"
885 select ARCH_HAS_CPUFREQ
886 select ARCH_REQUIRE_GPIOLIB
890 select GENERIC_CLOCKEVENTS
892 select MIGHT_HAVE_CACHE_L2X0
895 Support for ST-Ericsson's Ux500 architecture
898 bool "STMicroelectronics Nomadik"
899 select ARCH_REQUIRE_GPIOLIB
904 select GENERIC_CLOCKEVENTS
905 select MIGHT_HAVE_CACHE_L2X0
907 select PINCTRL_STN8815
910 Support for the Nomadik platform by ST-Ericsson
914 select ARCH_HAS_CPUFREQ
915 select ARCH_REQUIRE_GPIOLIB
920 select GENERIC_CLOCKEVENTS
923 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
927 select ARCH_HAS_HOLES_MEMORYMODEL
928 select ARCH_REQUIRE_GPIOLIB
930 select GENERIC_ALLOCATOR
931 select GENERIC_CLOCKEVENTS
932 select GENERIC_IRQ_CHIP
934 select NEED_MACH_GPIO_H
938 Support for TI's DaVinci platform.
943 select ARCH_HAS_CPUFREQ
944 select ARCH_HAS_HOLES_MEMORYMODEL
946 select ARCH_REQUIRE_GPIOLIB
949 select GENERIC_CLOCKEVENTS
950 select GENERIC_IRQ_CHIP
954 select NEED_MACH_IO_H if PCCARD
955 select NEED_MACH_MEMORY_H
957 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
959 config ARCH_VT8500_SINGLE
960 bool "VIA/WonderMedia 85xx"
961 select ARCH_HAS_CPUFREQ
962 select ARCH_REQUIRE_GPIOLIB
966 select GENERIC_CLOCKEVENTS
969 select MULTI_IRQ_HANDLER
973 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
977 menu "Multiple platform selection"
978 depends on ARCH_MULTIPLATFORM
980 comment "CPU Core family selection"
983 bool "ARMv4 based platforms (FA526, StrongARM)"
984 depends on !ARCH_MULTI_V6_V7
985 select ARCH_MULTI_V4_V5
987 config ARCH_MULTI_V4T
988 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
989 depends on !ARCH_MULTI_V6_V7
990 select ARCH_MULTI_V4_V5
993 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
994 depends on !ARCH_MULTI_V6_V7
995 select ARCH_MULTI_V4_V5
997 config ARCH_MULTI_V4_V5
1000 config ARCH_MULTI_V6
1001 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
1002 select ARCH_MULTI_V6_V7
1005 config ARCH_MULTI_V7
1006 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1008 select ARCH_MULTI_V6_V7
1009 select ARCH_VEXPRESS
1012 config ARCH_MULTI_V6_V7
1015 config ARCH_MULTI_CPU_AUTO
1016 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1017 select ARCH_MULTI_V5
1022 # This is sorted alphabetically by mach-* pathname. However, plat-*
1023 # Kconfigs may be included either alphabetically (according to the
1024 # plat- suffix) or along side the corresponding mach-* source.
1026 source "arch/arm/mach-mvebu/Kconfig"
1028 source "arch/arm/mach-at91/Kconfig"
1030 source "arch/arm/mach-bcm/Kconfig"
1032 source "arch/arm/mach-clps711x/Kconfig"
1034 source "arch/arm/mach-cns3xxx/Kconfig"
1036 source "arch/arm/mach-davinci/Kconfig"
1038 source "arch/arm/mach-dove/Kconfig"
1040 source "arch/arm/mach-ep93xx/Kconfig"
1042 source "arch/arm/mach-footbridge/Kconfig"
1044 source "arch/arm/mach-gemini/Kconfig"
1046 source "arch/arm/mach-h720x/Kconfig"
1048 source "arch/arm/mach-highbank/Kconfig"
1050 source "arch/arm/mach-integrator/Kconfig"
1052 source "arch/arm/mach-iop32x/Kconfig"
1054 source "arch/arm/mach-iop33x/Kconfig"
1056 source "arch/arm/mach-iop13xx/Kconfig"
1058 source "arch/arm/mach-ixp4xx/Kconfig"
1060 source "arch/arm/mach-kirkwood/Kconfig"
1062 source "arch/arm/mach-ks8695/Kconfig"
1064 source "arch/arm/mach-msm/Kconfig"
1066 source "arch/arm/mach-mv78xx0/Kconfig"
1068 source "arch/arm/mach-imx/Kconfig"
1070 source "arch/arm/mach-mxs/Kconfig"
1072 source "arch/arm/mach-netx/Kconfig"
1074 source "arch/arm/mach-nomadik/Kconfig"
1076 source "arch/arm/plat-omap/Kconfig"
1078 source "arch/arm/mach-omap1/Kconfig"
1080 source "arch/arm/mach-omap2/Kconfig"
1082 source "arch/arm/mach-orion5x/Kconfig"
1084 source "arch/arm/mach-picoxcell/Kconfig"
1086 source "arch/arm/mach-pxa/Kconfig"
1087 source "arch/arm/plat-pxa/Kconfig"
1089 source "arch/arm/mach-mmp/Kconfig"
1091 source "arch/arm/mach-realview/Kconfig"
1093 source "arch/arm/mach-sa1100/Kconfig"
1095 source "arch/arm/plat-samsung/Kconfig"
1096 source "arch/arm/plat-s3c24xx/Kconfig"
1098 source "arch/arm/mach-socfpga/Kconfig"
1100 source "arch/arm/plat-spear/Kconfig"
1102 source "arch/arm/mach-s3c24xx/Kconfig"
1104 source "arch/arm/mach-s3c2412/Kconfig"
1105 source "arch/arm/mach-s3c2440/Kconfig"
1109 source "arch/arm/mach-s3c64xx/Kconfig"
1112 source "arch/arm/mach-s5p64x0/Kconfig"
1114 source "arch/arm/mach-s5pc100/Kconfig"
1116 source "arch/arm/mach-s5pv210/Kconfig"
1118 source "arch/arm/mach-exynos/Kconfig"
1120 source "arch/arm/mach-shmobile/Kconfig"
1122 source "arch/arm/mach-sunxi/Kconfig"
1124 source "arch/arm/mach-prima2/Kconfig"
1126 source "arch/arm/mach-tegra/Kconfig"
1128 source "arch/arm/mach-u300/Kconfig"
1130 source "arch/arm/mach-ux500/Kconfig"
1132 source "arch/arm/mach-versatile/Kconfig"
1134 source "arch/arm/mach-vexpress/Kconfig"
1135 source "arch/arm/plat-versatile/Kconfig"
1137 source "arch/arm/mach-vt8500/Kconfig"
1139 source "arch/arm/mach-w90x900/Kconfig"
1141 source "arch/arm/mach-zynq/Kconfig"
1143 # Definitions to make life easier
1149 select GENERIC_CLOCKEVENTS
1155 select GENERIC_IRQ_CHIP
1158 config PLAT_ORION_LEGACY
1165 config PLAT_VERSATILE
1168 config ARM_TIMER_SP804
1171 select HAVE_SCHED_CLOCK
1173 source arch/arm/mm/Kconfig
1177 default 16 if ARCH_EP93XX
1181 bool "Enable iWMMXt support"
1182 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1183 default y if PXA27x || PXA3xx || ARCH_MMP
1185 Enable support for iWMMXt context switching at run time if
1186 running on a CPU that supports it.
1190 depends on CPU_XSCALE
1193 config MULTI_IRQ_HANDLER
1196 Allow each machine to specify it's own IRQ handler at run time.
1199 source "arch/arm/Kconfig-nommu"
1202 config ARM_ERRATA_326103
1203 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1206 Executing a SWP instruction to read-only memory does not set bit 11
1207 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1208 treat the access as a read, preventing a COW from occurring and
1209 causing the faulting task to livelock.
1211 config ARM_ERRATA_411920
1212 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1213 depends on CPU_V6 || CPU_V6K
1215 Invalidation of the Instruction Cache operation can
1216 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1217 It does not affect the MPCore. This option enables the ARM Ltd.
1218 recommended workaround.
1220 config ARM_ERRATA_430973
1221 bool "ARM errata: Stale prediction on replaced interworking branch"
1224 This option enables the workaround for the 430973 Cortex-A8
1225 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1226 interworking branch is replaced with another code sequence at the
1227 same virtual address, whether due to self-modifying code or virtual
1228 to physical address re-mapping, Cortex-A8 does not recover from the
1229 stale interworking branch prediction. This results in Cortex-A8
1230 executing the new code sequence in the incorrect ARM or Thumb state.
1231 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1232 and also flushes the branch target cache at every context switch.
1233 Note that setting specific bits in the ACTLR register may not be
1234 available in non-secure mode.
1236 config ARM_ERRATA_458693
1237 bool "ARM errata: Processor deadlock when a false hazard is created"
1239 depends on !ARCH_MULTIPLATFORM
1241 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1242 erratum. For very specific sequences of memory operations, it is
1243 possible for a hazard condition intended for a cache line to instead
1244 be incorrectly associated with a different cache line. This false
1245 hazard might then cause a processor deadlock. The workaround enables
1246 the L1 caching of the NEON accesses and disables the PLD instruction
1247 in the ACTLR register. Note that setting specific bits in the ACTLR
1248 register may not be available in non-secure mode.
1250 config ARM_ERRATA_460075
1251 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1253 depends on !ARCH_MULTIPLATFORM
1255 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1256 erratum. Any asynchronous access to the L2 cache may encounter a
1257 situation in which recent store transactions to the L2 cache are lost
1258 and overwritten with stale memory contents from external memory. The
1259 workaround disables the write-allocate mode for the L2 cache via the
1260 ACTLR register. Note that setting specific bits in the ACTLR register
1261 may not be available in non-secure mode.
1263 config ARM_ERRATA_742230
1264 bool "ARM errata: DMB operation may be faulty"
1265 depends on CPU_V7 && SMP
1266 depends on !ARCH_MULTIPLATFORM
1268 This option enables the workaround for the 742230 Cortex-A9
1269 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1270 between two write operations may not ensure the correct visibility
1271 ordering of the two writes. This workaround sets a specific bit in
1272 the diagnostic register of the Cortex-A9 which causes the DMB
1273 instruction to behave as a DSB, ensuring the correct behaviour of
1276 config ARM_ERRATA_742231
1277 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1278 depends on CPU_V7 && SMP
1279 depends on !ARCH_MULTIPLATFORM
1281 This option enables the workaround for the 742231 Cortex-A9
1282 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1283 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1284 accessing some data located in the same cache line, may get corrupted
1285 data due to bad handling of the address hazard when the line gets
1286 replaced from one of the CPUs at the same time as another CPU is
1287 accessing it. This workaround sets specific bits in the diagnostic
1288 register of the Cortex-A9 which reduces the linefill issuing
1289 capabilities of the processor.
1291 config PL310_ERRATA_588369
1292 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1293 depends on CACHE_L2X0
1295 The PL310 L2 cache controller implements three types of Clean &
1296 Invalidate maintenance operations: by Physical Address
1297 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1298 They are architecturally defined to behave as the execution of a
1299 clean operation followed immediately by an invalidate operation,
1300 both performing to the same memory location. This functionality
1301 is not correctly implemented in PL310 as clean lines are not
1302 invalidated as a result of these operations.
1304 config ARM_ERRATA_720789
1305 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1308 This option enables the workaround for the 720789 Cortex-A9 (prior to
1309 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1310 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1311 As a consequence of this erratum, some TLB entries which should be
1312 invalidated are not, resulting in an incoherency in the system page
1313 tables. The workaround changes the TLB flushing routines to invalidate
1314 entries regardless of the ASID.
1316 config PL310_ERRATA_727915
1317 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1318 depends on CACHE_L2X0
1320 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1321 operation (offset 0x7FC). This operation runs in background so that
1322 PL310 can handle normal accesses while it is in progress. Under very
1323 rare circumstances, due to this erratum, write data can be lost when
1324 PL310 treats a cacheable write transaction during a Clean &
1325 Invalidate by Way operation.
1327 config ARM_ERRATA_743622
1328 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1330 depends on !ARCH_MULTIPLATFORM
1332 This option enables the workaround for the 743622 Cortex-A9
1333 (r2p*) erratum. Under very rare conditions, a faulty
1334 optimisation in the Cortex-A9 Store Buffer may lead to data
1335 corruption. This workaround sets a specific bit in the diagnostic
1336 register of the Cortex-A9 which disables the Store Buffer
1337 optimisation, preventing the defect from occurring. This has no
1338 visible impact on the overall performance or power consumption of the
1341 config ARM_ERRATA_751472
1342 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1344 depends on !ARCH_MULTIPLATFORM
1346 This option enables the workaround for the 751472 Cortex-A9 (prior
1347 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1348 completion of a following broadcasted operation if the second
1349 operation is received by a CPU before the ICIALLUIS has completed,
1350 potentially leading to corrupted entries in the cache or TLB.
1352 config PL310_ERRATA_753970
1353 bool "PL310 errata: cache sync operation may be faulty"
1354 depends on CACHE_PL310
1356 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1358 Under some condition the effect of cache sync operation on
1359 the store buffer still remains when the operation completes.
1360 This means that the store buffer is always asked to drain and
1361 this prevents it from merging any further writes. The workaround
1362 is to replace the normal offset of cache sync operation (0x730)
1363 by another offset targeting an unmapped PL310 register 0x740.
1364 This has the same effect as the cache sync operation: store buffer
1365 drain and waiting for all buffers empty.
1367 config ARM_ERRATA_754322
1368 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1371 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1372 r3p*) erratum. A speculative memory access may cause a page table walk
1373 which starts prior to an ASID switch but completes afterwards. This
1374 can populate the micro-TLB with a stale entry which may be hit with
1375 the new ASID. This workaround places two dsb instructions in the mm
1376 switching code so that no page table walks can cross the ASID switch.
1378 config ARM_ERRATA_754327
1379 bool "ARM errata: no automatic Store Buffer drain"
1380 depends on CPU_V7 && SMP
1382 This option enables the workaround for the 754327 Cortex-A9 (prior to
1383 r2p0) erratum. The Store Buffer does not have any automatic draining
1384 mechanism and therefore a livelock may occur if an external agent
1385 continuously polls a memory location waiting to observe an update.
1386 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1387 written polling loops from denying visibility of updates to memory.
1389 config ARM_ERRATA_364296
1390 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1391 depends on CPU_V6 && !SMP
1393 This options enables the workaround for the 364296 ARM1136
1394 r0p2 erratum (possible cache data corruption with
1395 hit-under-miss enabled). It sets the undocumented bit 31 in
1396 the auxiliary control register and the FI bit in the control
1397 register, thus disabling hit-under-miss without putting the
1398 processor into full low interrupt latency mode. ARM11MPCore
1401 config ARM_ERRATA_764369
1402 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1403 depends on CPU_V7 && SMP
1405 This option enables the workaround for erratum 764369
1406 affecting Cortex-A9 MPCore with two or more processors (all
1407 current revisions). Under certain timing circumstances, a data
1408 cache line maintenance operation by MVA targeting an Inner
1409 Shareable memory region may fail to proceed up to either the
1410 Point of Coherency or to the Point of Unification of the
1411 system. This workaround adds a DSB instruction before the
1412 relevant cache maintenance functions and sets a specific bit
1413 in the diagnostic control register of the SCU.
1415 config PL310_ERRATA_769419
1416 bool "PL310 errata: no automatic Store Buffer drain"
1417 depends on CACHE_L2X0
1419 On revisions of the PL310 prior to r3p2, the Store Buffer does
1420 not automatically drain. This can cause normal, non-cacheable
1421 writes to be retained when the memory system is idle, leading
1422 to suboptimal I/O performance for drivers using coherent DMA.
1423 This option adds a write barrier to the cpu_idle loop so that,
1424 on systems with an outer cache, the store buffer is drained
1427 config ARM_ERRATA_775420
1428 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1431 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1432 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1433 operation aborts with MMU exception, it might cause the processor
1434 to deadlock. This workaround puts DSB before executing ISB if
1435 an abort may occur on cache maintenance.
1439 source "arch/arm/common/Kconfig"
1449 Find out whether you have ISA slots on your motherboard. ISA is the
1450 name of a bus system, i.e. the way the CPU talks to the other stuff
1451 inside your box. Other bus systems are PCI, EISA, MicroChannel
1452 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1453 newer boards don't support it. If you have ISA, say Y, otherwise N.
1455 # Select ISA DMA controller support
1460 # Select ISA DMA interface
1465 bool "PCI support" if MIGHT_HAVE_PCI
1467 Find out whether you have a PCI motherboard. PCI is the name of a
1468 bus system, i.e. the way the CPU talks to the other stuff inside
1469 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1470 VESA. If you have PCI, say Y, otherwise N.
1476 config PCI_NANOENGINE
1477 bool "BSE nanoEngine PCI support"
1478 depends on SA1100_NANOENGINE
1480 Enable PCI on the BSE nanoEngine board.
1485 # Select the host bridge type
1486 config PCI_HOST_VIA82C505
1488 depends on PCI && ARCH_SHARK
1491 config PCI_HOST_ITE8152
1493 depends on PCI && MACH_ARMCORE
1497 source "drivers/pci/Kconfig"
1499 source "drivers/pcmcia/Kconfig"
1503 menu "Kernel Features"
1508 This option should be selected by machines which have an SMP-
1511 The only effect of this option is to make the SMP-related
1512 options available to the user for configuration.
1515 bool "Symmetric Multi-Processing"
1516 depends on CPU_V6K || CPU_V7
1517 depends on GENERIC_CLOCKEVENTS
1520 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1521 select USE_GENERIC_SMP_HELPERS
1523 This enables support for systems with more than one CPU. If you have
1524 a system with only one CPU, like most personal computers, say N. If
1525 you have a system with more than one CPU, say Y.
1527 If you say N here, the kernel will run on single and multiprocessor
1528 machines, but will use only one CPU of a multiprocessor machine. If
1529 you say Y here, the kernel will run on many, but not all, single
1530 processor machines. On a single processor machine, the kernel will
1531 run faster if you say N here.
1533 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1534 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1535 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1537 If you don't know what to do here, say N.
1540 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1541 depends on EXPERIMENTAL
1542 depends on SMP && !XIP_KERNEL
1545 SMP kernels contain instructions which fail on non-SMP processors.
1546 Enabling this option allows the kernel to modify itself to make
1547 these instructions safe. Disabling it allows about 1K of space
1550 If you don't know what to do here, say Y.
1552 config ARM_CPU_TOPOLOGY
1553 bool "Support cpu topology definition"
1554 depends on SMP && CPU_V7
1557 Support ARM cpu topology definition. The MPIDR register defines
1558 affinity between processors which is then used to describe the cpu
1559 topology of an ARM System.
1562 bool "Multi-core scheduler support"
1563 depends on ARM_CPU_TOPOLOGY
1565 Multi-core scheduler support improves the CPU scheduler's decision
1566 making when dealing with multi-core CPU chips at a cost of slightly
1567 increased overhead in some places. If unsure say N here.
1570 bool "SMT scheduler support"
1571 depends on ARM_CPU_TOPOLOGY
1573 Improves the CPU scheduler's decision making when dealing with
1574 MultiThreading at a cost of slightly increased overhead in some
1575 places. If unsure say N here.
1580 This option enables support for the ARM system coherency unit
1582 config ARM_ARCH_TIMER
1583 bool "Architected timer support"
1586 This option enables support for the ARM architected timer
1592 This options enables support for the ARM timer and watchdog unit
1595 prompt "Memory split"
1598 Select the desired split between kernel and user memory.
1600 If you are not absolutely sure what you are doing, leave this
1604 bool "3G/1G user/kernel split"
1606 bool "2G/2G user/kernel split"
1608 bool "1G/3G user/kernel split"
1613 default 0x40000000 if VMSPLIT_1G
1614 default 0x80000000 if VMSPLIT_2G
1618 int "Maximum number of CPUs (2-32)"
1624 bool "Support for hot-pluggable CPUs"
1625 depends on SMP && HOTPLUG
1627 Say Y here to experiment with turning CPUs off and on. CPUs
1628 can be controlled through /sys/devices/system/cpu.
1631 bool "Use local timer interrupts"
1634 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1636 Enable support for local timers on SMP platforms, rather then the
1637 legacy IPI broadcast method. Local timers allows the system
1638 accounting to be spread across the timer interval, preventing a
1639 "thundering herd" at every timer tick.
1643 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1644 default 355 if ARCH_U8500
1645 default 264 if MACH_H4700
1646 default 512 if SOC_OMAP5
1647 default 288 if ARCH_VT8500
1650 Maximum number of GPIOs in the system.
1652 If unsure, leave the default value.
1654 source kernel/Kconfig.preempt
1658 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1659 ARCH_S5PV210 || ARCH_EXYNOS4
1660 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1661 default AT91_TIMER_HZ if ARCH_AT91
1662 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1665 config THUMB2_KERNEL
1666 bool "Compile the kernel in Thumb-2 mode"
1667 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1669 select ARM_ASM_UNIFIED
1672 By enabling this option, the kernel will be compiled in
1673 Thumb-2 mode. A compiler/assembler that understand the unified
1674 ARM-Thumb syntax is needed.
1678 config THUMB2_AVOID_R_ARM_THM_JUMP11
1679 bool "Work around buggy Thumb-2 short branch relocations in gas"
1680 depends on THUMB2_KERNEL && MODULES
1683 Various binutils versions can resolve Thumb-2 branches to
1684 locally-defined, preemptible global symbols as short-range "b.n"
1685 branch instructions.
1687 This is a problem, because there's no guarantee the final
1688 destination of the symbol, or any candidate locations for a
1689 trampoline, are within range of the branch. For this reason, the
1690 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1691 relocation in modules at all, and it makes little sense to add
1694 The symptom is that the kernel fails with an "unsupported
1695 relocation" error when loading some modules.
1697 Until fixed tools are available, passing
1698 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1699 code which hits this problem, at the cost of a bit of extra runtime
1700 stack usage in some cases.
1702 The problem is described in more detail at:
1703 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1705 Only Thumb-2 kernels are affected.
1707 Unless you are sure your tools don't have this problem, say Y.
1709 config ARM_ASM_UNIFIED
1713 bool "Use the ARM EABI to compile the kernel"
1715 This option allows for the kernel to be compiled using the latest
1716 ARM ABI (aka EABI). This is only useful if you are using a user
1717 space environment that is also compiled with EABI.
1719 Since there are major incompatibilities between the legacy ABI and
1720 EABI, especially with regard to structure member alignment, this
1721 option also changes the kernel syscall calling convention to
1722 disambiguate both ABIs and allow for backward compatibility support
1723 (selected with CONFIG_OABI_COMPAT).
1725 To use this you need GCC version 4.0.0 or later.
1728 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1729 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1732 This option preserves the old syscall interface along with the
1733 new (ARM EABI) one. It also provides a compatibility layer to
1734 intercept syscalls that have structure arguments which layout
1735 in memory differs between the legacy ABI and the new ARM EABI
1736 (only for non "thumb" binaries). This option adds a tiny
1737 overhead to all syscalls and produces a slightly larger kernel.
1738 If you know you'll be using only pure EABI user space then you
1739 can say N here. If this option is not selected and you attempt
1740 to execute a legacy ABI binary then the result will be
1741 UNPREDICTABLE (in fact it can be predicted that it won't work
1742 at all). If in doubt say Y.
1744 config ARCH_HAS_HOLES_MEMORYMODEL
1747 config ARCH_SPARSEMEM_ENABLE
1750 config ARCH_SPARSEMEM_DEFAULT
1751 def_bool ARCH_SPARSEMEM_ENABLE
1753 config ARCH_SELECT_MEMORY_MODEL
1754 def_bool ARCH_SPARSEMEM_ENABLE
1756 config HAVE_ARCH_PFN_VALID
1757 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1760 bool "High Memory Support"
1763 The address space of ARM processors is only 4 Gigabytes large
1764 and it has to accommodate user address space, kernel address
1765 space as well as some memory mapped IO. That means that, if you
1766 have a large amount of physical memory and/or IO, not all of the
1767 memory can be "permanently mapped" by the kernel. The physical
1768 memory that is not permanently mapped is called "high memory".
1770 Depending on the selected kernel/user memory split, minimum
1771 vmalloc space and actual amount of RAM, you may not need this
1772 option which should result in a slightly faster kernel.
1777 bool "Allocate 2nd-level pagetables from highmem"
1780 config HW_PERF_EVENTS
1781 bool "Enable hardware performance counter support for perf events"
1782 depends on PERF_EVENTS
1785 Enable hardware performance counter support for perf events. If
1786 disabled, perf events will use software events only.
1790 config FORCE_MAX_ZONEORDER
1791 int "Maximum zone order" if ARCH_SHMOBILE
1792 range 11 64 if ARCH_SHMOBILE
1793 default "12" if SOC_AM33XX
1794 default "9" if SA1111
1797 The kernel memory allocator divides physically contiguous memory
1798 blocks into "zones", where each zone is a power of two number of
1799 pages. This option selects the largest power of two that the kernel
1800 keeps in the memory allocator. If you need to allocate very large
1801 blocks of physically contiguous memory, then you may need to
1802 increase this value.
1804 This config option is actually maximum order plus one. For example,
1805 a value of 11 means that the largest free memory block is 2^10 pages.
1807 config ALIGNMENT_TRAP
1809 depends on CPU_CP15_MMU
1810 default y if !ARCH_EBSA110
1811 select HAVE_PROC_CPU if PROC_FS
1813 ARM processors cannot fetch/store information which is not
1814 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1815 address divisible by 4. On 32-bit ARM processors, these non-aligned
1816 fetch/store instructions will be emulated in software if you say
1817 here, which has a severe performance impact. This is necessary for
1818 correct operation of some network protocols. With an IP-only
1819 configuration it is safe to say N, otherwise say Y.
1821 config UACCESS_WITH_MEMCPY
1822 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1824 default y if CPU_FEROCEON
1826 Implement faster copy_to_user and clear_user methods for CPU
1827 cores where a 8-word STM instruction give significantly higher
1828 memory write throughput than a sequence of individual 32bit stores.
1830 A possible side effect is a slight increase in scheduling latency
1831 between threads sharing the same address space if they invoke
1832 such copy operations with large buffers.
1834 However, if the CPU data cache is using a write-allocate mode,
1835 this option is unlikely to provide any performance gain.
1839 prompt "Enable seccomp to safely compute untrusted bytecode"
1841 This kernel feature is useful for number crunching applications
1842 that may need to compute untrusted bytecode during their
1843 execution. By using pipes or other transports made available to
1844 the process as file descriptors supporting the read/write
1845 syscalls, it's possible to isolate those applications in
1846 their own address space using seccomp. Once seccomp is
1847 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1848 and the task is only allowed to execute a few safe syscalls
1849 defined by each seccomp mode.
1851 config CC_STACKPROTECTOR
1852 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1853 depends on EXPERIMENTAL
1855 This option turns on the -fstack-protector GCC feature. This
1856 feature puts, at the beginning of functions, a canary value on
1857 the stack just before the return address, and validates
1858 the value just before actually returning. Stack based buffer
1859 overflows (that need to overwrite this return address) now also
1860 overwrite the canary, which gets detected and the attack is then
1861 neutralized via a kernel panic.
1862 This feature requires gcc version 4.2 or above.
1869 bool "Xen guest support on ARM (EXPERIMENTAL)"
1870 depends on EXPERIMENTAL && ARM && OF
1871 depends on CPU_V7 && !CPU_V6
1873 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1880 bool "Flattened Device Tree support"
1883 select OF_EARLY_FLATTREE
1885 Include support for flattened device tree machine descriptions.
1888 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1891 This is the traditional way of passing data to the kernel at boot
1892 time. If you are solely relying on the flattened device tree (or
1893 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1894 to remove ATAGS support from your kernel binary. If unsure,
1897 config DEPRECATED_PARAM_STRUCT
1898 bool "Provide old way to pass kernel parameters"
1901 This was deprecated in 2001 and announced to live on for 5 years.
1902 Some old boot loaders still use this way.
1904 # Compressed boot loader in ROM. Yes, we really want to ask about
1905 # TEXT and BSS so we preserve their values in the config files.
1906 config ZBOOT_ROM_TEXT
1907 hex "Compressed ROM boot loader base address"
1910 The physical address at which the ROM-able zImage is to be
1911 placed in the target. Platforms which normally make use of
1912 ROM-able zImage formats normally set this to a suitable
1913 value in their defconfig file.
1915 If ZBOOT_ROM is not enabled, this has no effect.
1917 config ZBOOT_ROM_BSS
1918 hex "Compressed ROM boot loader BSS address"
1921 The base address of an area of read/write memory in the target
1922 for the ROM-able zImage which must be available while the
1923 decompressor is running. It must be large enough to hold the
1924 entire decompressed kernel plus an additional 128 KiB.
1925 Platforms which normally make use of ROM-able zImage formats
1926 normally set this to a suitable value in their defconfig file.
1928 If ZBOOT_ROM is not enabled, this has no effect.
1931 bool "Compressed boot loader in ROM/flash"
1932 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1934 Say Y here if you intend to execute your compressed kernel image
1935 (zImage) directly from ROM or flash. If unsure, say N.
1938 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1939 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1940 default ZBOOT_ROM_NONE
1942 Include experimental SD/MMC loading code in the ROM-able zImage.
1943 With this enabled it is possible to write the ROM-able zImage
1944 kernel image to an MMC or SD card and boot the kernel straight
1945 from the reset vector. At reset the processor Mask ROM will load
1946 the first part of the ROM-able zImage which in turn loads the
1947 rest the kernel image to RAM.
1949 config ZBOOT_ROM_NONE
1950 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1952 Do not load image from SD or MMC
1954 config ZBOOT_ROM_MMCIF
1955 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1957 Load image from MMCIF hardware block.
1959 config ZBOOT_ROM_SH_MOBILE_SDHI
1960 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1962 Load image from SDHI hardware block
1966 config ARM_APPENDED_DTB
1967 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1968 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1970 With this option, the boot code will look for a device tree binary
1971 (DTB) appended to zImage
1972 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1974 This is meant as a backward compatibility convenience for those
1975 systems with a bootloader that can't be upgraded to accommodate
1976 the documented boot protocol using a device tree.
1978 Beware that there is very little in terms of protection against
1979 this option being confused by leftover garbage in memory that might
1980 look like a DTB header after a reboot if no actual DTB is appended
1981 to zImage. Do not leave this option active in a production kernel
1982 if you don't intend to always append a DTB. Proper passing of the
1983 location into r2 of a bootloader provided DTB is always preferable
1986 config ARM_ATAG_DTB_COMPAT
1987 bool "Supplement the appended DTB with traditional ATAG information"
1988 depends on ARM_APPENDED_DTB
1990 Some old bootloaders can't be updated to a DTB capable one, yet
1991 they provide ATAGs with memory configuration, the ramdisk address,
1992 the kernel cmdline string, etc. Such information is dynamically
1993 provided by the bootloader and can't always be stored in a static
1994 DTB. To allow a device tree enabled kernel to be used with such
1995 bootloaders, this option allows zImage to extract the information
1996 from the ATAG list and store it at run time into the appended DTB.
1999 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2000 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2002 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2003 bool "Use bootloader kernel arguments if available"
2005 Uses the command-line options passed by the boot loader instead of
2006 the device tree bootargs property. If the boot loader doesn't provide
2007 any, the device tree bootargs property will be used.
2009 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2010 bool "Extend with bootloader kernel arguments"
2012 The command-line arguments provided by the boot loader will be
2013 appended to the the device tree bootargs property.
2018 string "Default kernel command string"
2021 On some architectures (EBSA110 and CATS), there is currently no way
2022 for the boot loader to pass arguments to the kernel. For these
2023 architectures, you should supply some command-line options at build
2024 time by entering them here. As a minimum, you should specify the
2025 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2028 prompt "Kernel command line type" if CMDLINE != ""
2029 default CMDLINE_FROM_BOOTLOADER
2032 config CMDLINE_FROM_BOOTLOADER
2033 bool "Use bootloader kernel arguments if available"
2035 Uses the command-line options passed by the boot loader. If
2036 the boot loader doesn't provide any, the default kernel command
2037 string provided in CMDLINE will be used.
2039 config CMDLINE_EXTEND
2040 bool "Extend bootloader kernel arguments"
2042 The command-line arguments provided by the boot loader will be
2043 appended to the default kernel command string.
2045 config CMDLINE_FORCE
2046 bool "Always use the default kernel command string"
2048 Always use the default kernel command string, even if the boot
2049 loader passes other arguments to the kernel.
2050 This is useful if you cannot or don't want to change the
2051 command-line options your boot loader passes to the kernel.
2055 bool "Kernel Execute-In-Place from ROM"
2056 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2058 Execute-In-Place allows the kernel to run from non-volatile storage
2059 directly addressable by the CPU, such as NOR flash. This saves RAM
2060 space since the text section of the kernel is not loaded from flash
2061 to RAM. Read-write sections, such as the data section and stack,
2062 are still copied to RAM. The XIP kernel is not compressed since
2063 it has to run directly from flash, so it will take more space to
2064 store it. The flash address used to link the kernel object files,
2065 and for storing it, is configuration dependent. Therefore, if you
2066 say Y here, you must know the proper physical address where to
2067 store the kernel image depending on your own flash memory usage.
2069 Also note that the make target becomes "make xipImage" rather than
2070 "make zImage" or "make Image". The final kernel binary to put in
2071 ROM memory will be arch/arm/boot/xipImage.
2075 config XIP_PHYS_ADDR
2076 hex "XIP Kernel Physical Location"
2077 depends on XIP_KERNEL
2078 default "0x00080000"
2080 This is the physical address in your flash memory the kernel will
2081 be linked for and stored to. This address is dependent on your
2085 bool "Kexec system call (EXPERIMENTAL)"
2086 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2088 kexec is a system call that implements the ability to shutdown your
2089 current kernel, and to start another kernel. It is like a reboot
2090 but it is independent of the system firmware. And like a reboot
2091 you can start any kernel with it, not just Linux.
2093 It is an ongoing process to be certain the hardware in a machine
2094 is properly shutdown, so do not be surprised if this code does not
2095 initially work for you. It may help to enable device hotplugging
2099 bool "Export atags in procfs"
2100 depends on ATAGS && KEXEC
2103 Should the atags used to boot the kernel be exported in an "atags"
2104 file in procfs. Useful with kexec.
2107 bool "Build kdump crash kernel (EXPERIMENTAL)"
2108 depends on EXPERIMENTAL
2110 Generate crash dump after being started by kexec. This should
2111 be normally only set in special crash dump kernels which are
2112 loaded in the main kernel with kexec-tools into a specially
2113 reserved region and then later executed after a crash by
2114 kdump/kexec. The crash dump kernel must be compiled to a
2115 memory address not used by the main kernel
2117 For more details see Documentation/kdump/kdump.txt
2119 config AUTO_ZRELADDR
2120 bool "Auto calculation of the decompressed kernel image address"
2121 depends on !ZBOOT_ROM && !ARCH_U300
2123 ZRELADDR is the physical address where the decompressed kernel
2124 image will be placed. If AUTO_ZRELADDR is selected, the address
2125 will be determined at run-time by masking the current IP with
2126 0xf8000000. This assumes the zImage being placed in the first 128MB
2127 from start of memory.
2131 menu "CPU Power Management"
2135 source "drivers/cpufreq/Kconfig"
2138 tristate "CPUfreq driver for i.MX CPUs"
2139 depends on ARCH_MXC && CPU_FREQ
2140 select CPU_FREQ_TABLE
2142 This enables the CPUfreq driver for i.MX CPUs.
2144 config CPU_FREQ_SA1100
2147 config CPU_FREQ_SA1110
2150 config CPU_FREQ_INTEGRATOR
2151 tristate "CPUfreq driver for ARM Integrator CPUs"
2152 depends on ARCH_INTEGRATOR && CPU_FREQ
2155 This enables the CPUfreq driver for ARM Integrator CPUs.
2157 For details, take a look at <file:Documentation/cpu-freq>.
2163 depends on CPU_FREQ && ARCH_PXA && PXA25x
2165 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2166 select CPU_FREQ_TABLE
2171 Internal configuration node for common cpufreq on Samsung SoC
2173 config CPU_FREQ_S3C24XX
2174 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2175 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2178 This enables the CPUfreq driver for the Samsung S3C24XX family
2181 For details, take a look at <file:Documentation/cpu-freq>.
2185 config CPU_FREQ_S3C24XX_PLL
2186 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2187 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2189 Compile in support for changing the PLL frequency from the
2190 S3C24XX series CPUfreq driver. The PLL takes time to settle
2191 after a frequency change, so by default it is not enabled.
2193 This also means that the PLL tables for the selected CPU(s) will
2194 be built which may increase the size of the kernel image.
2196 config CPU_FREQ_S3C24XX_DEBUG
2197 bool "Debug CPUfreq Samsung driver core"
2198 depends on CPU_FREQ_S3C24XX
2200 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2202 config CPU_FREQ_S3C24XX_IODEBUG
2203 bool "Debug CPUfreq Samsung driver IO timing"
2204 depends on CPU_FREQ_S3C24XX
2206 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2208 config CPU_FREQ_S3C24XX_DEBUGFS
2209 bool "Export debugfs for CPUFreq"
2210 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2212 Export status information via debugfs.
2216 source "drivers/cpuidle/Kconfig"
2220 menu "Floating point emulation"
2222 comment "At least one emulation must be selected"
2225 bool "NWFPE math emulation"
2226 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2228 Say Y to include the NWFPE floating point emulator in the kernel.
2229 This is necessary to run most binaries. Linux does not currently
2230 support floating point hardware so you need to say Y here even if
2231 your machine has an FPA or floating point co-processor podule.
2233 You may say N here if you are going to load the Acorn FPEmulator
2234 early in the bootup.
2237 bool "Support extended precision"
2238 depends on FPE_NWFPE
2240 Say Y to include 80-bit support in the kernel floating-point
2241 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2242 Note that gcc does not generate 80-bit operations by default,
2243 so in most cases this option only enlarges the size of the
2244 floating point emulator without any good reason.
2246 You almost surely want to say N here.
2249 bool "FastFPE math emulation (EXPERIMENTAL)"
2250 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2252 Say Y here to include the FAST floating point emulator in the kernel.
2253 This is an experimental much faster emulator which now also has full
2254 precision for the mantissa. It does not support any exceptions.
2255 It is very simple, and approximately 3-6 times faster than NWFPE.
2257 It should be sufficient for most programs. It may be not suitable
2258 for scientific calculations, but you have to check this for yourself.
2259 If you do not feel you need a faster FP emulation you should better
2263 bool "VFP-format floating point maths"
2264 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2266 Say Y to include VFP support code in the kernel. This is needed
2267 if your hardware includes a VFP unit.
2269 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2270 release notes and additional status information.
2272 Say N if your target does not have VFP hardware.
2280 bool "Advanced SIMD (NEON) Extension support"
2281 depends on VFPv3 && CPU_V7
2283 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2288 menu "Userspace binary formats"
2290 source "fs/Kconfig.binfmt"
2293 tristate "RISC OS personality"
2296 Say Y here to include the kernel code necessary if you want to run
2297 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2298 experimental; if this sounds frightening, say N and sleep in peace.
2299 You can also say M here to compile this support as a module (which
2300 will be called arthur).
2304 menu "Power management options"
2306 source "kernel/power/Kconfig"
2308 config ARCH_SUSPEND_POSSIBLE
2309 depends on !ARCH_S5PC100
2310 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2311 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2314 config ARM_CPU_SUSPEND
2319 source "net/Kconfig"
2321 source "drivers/Kconfig"
2325 source "arch/arm/Kconfig.debug"
2327 source "security/Kconfig"
2329 source "crypto/Kconfig"
2331 source "lib/Kconfig"