4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_WANT_IPC_PARSE_VERSION
10 select BUILDTIME_EXTABLE_SORT if MMU
11 select CLONE_BACKWARDS
12 select CPU_PM if (SUSPEND || CPU_IDLE)
13 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
14 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
15 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
16 select GENERIC_IDLE_POLL_SETUP
17 select GENERIC_IRQ_PROBE
18 select GENERIC_IRQ_SHOW
19 select GENERIC_PCI_IOMAP
20 select GENERIC_SCHED_CLOCK
21 select GENERIC_SMP_IDLE_THREAD
22 select GENERIC_STRNCPY_FROM_USER
23 select GENERIC_STRNLEN_USER
24 select HARDIRQS_SW_RESEND
25 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
27 select HAVE_ARCH_SECCOMP_FILTER
28 select HAVE_ARCH_TRACEHOOK
30 select HAVE_CONTEXT_TRACKING
31 select HAVE_C_RECORDMCOUNT
32 select HAVE_DEBUG_KMEMLEAK
33 select HAVE_DMA_API_DEBUG
35 select HAVE_DMA_CONTIGUOUS if MMU
36 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
37 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
38 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
39 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
40 select HAVE_GENERIC_DMA_COHERENT
41 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
42 select HAVE_IDE if PCI || ISA || PCMCIA
43 select HAVE_IRQ_TIME_ACCOUNTING
44 select HAVE_KERNEL_GZIP
45 select HAVE_KERNEL_LZ4
46 select HAVE_KERNEL_LZMA
47 select HAVE_KERNEL_LZO
49 select HAVE_KPROBES if !XIP_KERNEL
50 select HAVE_KRETPROBES if (HAVE_KPROBES)
52 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
53 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
54 select HAVE_PERF_EVENTS
56 select HAVE_PERF_USER_STACK_DUMP
57 select HAVE_REGS_AND_STACK_ACCESS_API
58 select HAVE_SYSCALL_TRACEPOINTS
60 select IRQ_FORCED_THREADING
62 select MODULES_USE_ELF_REL
64 select OLD_SIGSUSPEND3
65 select PERF_USE_VMALLOC
67 select SYS_SUPPORTS_APM_EMULATION
68 # Above selects are sorted alphabetically; please add new ones
69 # according to that. Thanks.
71 The ARM series is a line of low-power-consumption RISC chip designs
72 licensed by ARM Ltd and targeted at embedded applications and
73 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
74 manufactured, but legacy ARM-based PC hardware remains popular in
75 Europe. There is an ARM Linux project with a web page at
76 <http://www.arm.linux.org.uk/>.
78 config ARM_HAS_SG_CHAIN
81 config NEED_SG_DMA_LENGTH
84 config ARM_DMA_USE_IOMMU
86 select ARM_HAS_SG_CHAIN
87 select NEED_SG_DMA_LENGTH
91 config ARM_DMA_IOMMU_ALIGNMENT
92 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
96 DMA mapping framework by default aligns all buffers to the smallest
97 PAGE_SIZE order which is greater than or equal to the requested buffer
98 size. This works well for buffers up to a few hundreds kilobytes, but
99 for larger buffers it just a waste of address space. Drivers which has
100 relatively small addressing window (like 64Mib) might run out of
101 virtual space with just a few allocations.
103 With this parameter you can specify the maximum PAGE_SIZE order for
104 DMA IOMMU buffers. Larger buffers will be aligned only to this
105 specified order. The order is expressed as a power of two multiplied
113 config MIGHT_HAVE_PCI
116 config SYS_SUPPORTS_APM_EMULATION
121 select GENERIC_ALLOCATOR
132 The Extended Industry Standard Architecture (EISA) bus was
133 developed as an open alternative to the IBM MicroChannel bus.
135 The EISA bus provided some of the features of the IBM MicroChannel
136 bus while maintaining backward compatibility with cards made for
137 the older ISA bus. The EISA bus saw limited use between 1988 and
138 1995 when it was made obsolete by the PCI bus.
140 Say Y here if you are building a kernel for an EISA-based machine.
147 config STACKTRACE_SUPPORT
151 config HAVE_LATENCYTOP_SUPPORT
156 config LOCKDEP_SUPPORT
160 config TRACE_IRQFLAGS_SUPPORT
164 config RWSEM_GENERIC_SPINLOCK
168 config RWSEM_XCHGADD_ALGORITHM
171 config ARCH_HAS_ILOG2_U32
174 config ARCH_HAS_ILOG2_U64
177 config ARCH_HAS_CPUFREQ
180 Internal node to signify that the ARCH has CPUFREQ support
181 and that the relevant menu configurations are displayed for
184 config ARCH_HAS_BANDGAP
187 config GENERIC_HWEIGHT
191 config GENERIC_CALIBRATE_DELAY
195 config ARCH_MAY_HAVE_PC_FDC
201 config NEED_DMA_MAP_STATE
204 config ARCH_HAS_DMA_SET_COHERENT_MASK
207 config GENERIC_ISA_DMA
213 config NEED_RET_TO_USER
221 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
222 default DRAM_BASE if REMAP_VECTORS_TO_RAM
225 The base address of exception vectors. This must be two pages
228 config ARM_PATCH_PHYS_VIRT
229 bool "Patch physical to virtual translations at runtime" if EMBEDDED
231 depends on !XIP_KERNEL && MMU
232 depends on !ARCH_REALVIEW || !SPARSEMEM
234 Patch phys-to-virt and virt-to-phys translation functions at
235 boot and module load time according to the position of the
236 kernel in system memory.
238 This can only be used with non-XIP MMU kernels where the base
239 of physical memory is at a 16MB boundary.
241 Only disable this option if you know that you do not require
242 this feature (eg, building a kernel for a single machine) and
243 you need to shrink the kernel to the minimal size.
245 config NEED_MACH_GPIO_H
248 Select this when mach/gpio.h is required to provide special
249 definitions for this platform. The need for mach/gpio.h should
250 be avoided when possible.
252 config NEED_MACH_IO_H
255 Select this when mach/io.h is required to provide special
256 definitions for this platform. The need for mach/io.h should
257 be avoided when possible.
259 config NEED_MACH_MEMORY_H
262 Select this when mach/memory.h is required to provide special
263 definitions for this platform. The need for mach/memory.h should
264 be avoided when possible.
267 hex "Physical address of main memory" if MMU
268 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
269 default DRAM_BASE if !MMU
271 Please provide the physical address corresponding to the
272 location of main memory in your system.
278 source "init/Kconfig"
280 source "kernel/Kconfig.freezer"
285 bool "MMU-based Paged Memory Management Support"
288 Select if you want MMU-based virtualised addressing space
289 support by paged memory management. If unsure, say 'Y'.
292 # The "ARM system type" choice list is ordered alphabetically by option
293 # text. Please add new entries in the option alphabetic order.
296 prompt "ARM system type"
297 default ARCH_VERSATILE if !MMU
298 default ARCH_MULTIPLATFORM if MMU
300 config ARCH_MULTIPLATFORM
301 bool "Allow multiple platforms to be selected"
303 select ARM_PATCH_PHYS_VIRT
306 select MULTI_IRQ_HANDLER
310 config ARCH_INTEGRATOR
311 bool "ARM Ltd. Integrator family"
312 select ARCH_HAS_CPUFREQ
315 select COMMON_CLK_VERSATILE
316 select GENERIC_CLOCKEVENTS
319 select MULTI_IRQ_HANDLER
320 select NEED_MACH_MEMORY_H
321 select PLAT_VERSATILE
323 select VERSATILE_FPGA_IRQ
325 Support for ARM's Integrator platform.
328 bool "ARM Ltd. RealView family"
329 select ARCH_WANT_OPTIONAL_GPIOLIB
331 select ARM_TIMER_SP804
333 select COMMON_CLK_VERSATILE
334 select GENERIC_CLOCKEVENTS
335 select GPIO_PL061 if GPIOLIB
337 select NEED_MACH_MEMORY_H
338 select PLAT_VERSATILE
339 select PLAT_VERSATILE_CLCD
341 This enables support for ARM Ltd RealView boards.
343 config ARCH_VERSATILE
344 bool "ARM Ltd. Versatile family"
345 select ARCH_WANT_OPTIONAL_GPIOLIB
347 select ARM_TIMER_SP804
350 select GENERIC_CLOCKEVENTS
351 select HAVE_MACH_CLKDEV
353 select PLAT_VERSATILE
354 select PLAT_VERSATILE_CLCD
355 select PLAT_VERSATILE_CLOCK
356 select VERSATILE_FPGA_IRQ
358 This enables support for ARM Ltd Versatile board.
362 select ARCH_REQUIRE_GPIOLIB
366 select NEED_MACH_GPIO_H
367 select NEED_MACH_IO_H if PCCARD
369 select PINCTRL_AT91 if USE_OF
371 This enables support for systems based on Atmel
372 AT91RM9200 and AT91SAM9* processors.
375 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
376 select ARCH_REQUIRE_GPIOLIB
382 select GENERIC_CLOCKEVENTS
384 select MULTI_IRQ_HANDLER
387 Support for Cirrus Logic 711x/721x/731x based boards.
390 bool "Cortina Systems Gemini"
391 select ARCH_REQUIRE_GPIOLIB
392 select ARCH_USES_GETTIMEOFFSET
394 select NEED_MACH_GPIO_H
396 Support for the Cortina Systems Gemini family SoCs
400 select ARCH_USES_GETTIMEOFFSET
403 select NEED_MACH_IO_H
404 select NEED_MACH_MEMORY_H
407 This is an evaluation board for the StrongARM processor available
408 from Digital. It has limited hardware on-board, including an
409 Ethernet interface, two PCMCIA sockets, two serial ports and a
414 select ARCH_HAS_HOLES_MEMORYMODEL
415 select ARCH_REQUIRE_GPIOLIB
416 select ARCH_USES_GETTIMEOFFSET
421 select NEED_MACH_MEMORY_H
423 This enables support for the Cirrus EP93xx series of CPUs.
425 config ARCH_FOOTBRIDGE
429 select GENERIC_CLOCKEVENTS
431 select NEED_MACH_IO_H if !MMU
432 select NEED_MACH_MEMORY_H
434 Support for systems based on the DC21285 companion chip
435 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
438 bool "Hilscher NetX based"
442 select GENERIC_CLOCKEVENTS
444 This enables support for systems based on the Hilscher NetX Soc
450 select NEED_MACH_MEMORY_H
451 select NEED_RET_TO_USER
456 Support for Intel's IOP13XX (XScale) family of processors.
461 select ARCH_REQUIRE_GPIOLIB
463 select NEED_MACH_GPIO_H
464 select NEED_RET_TO_USER
468 Support for Intel's 80219 and IOP32X (XScale) family of
474 select ARCH_REQUIRE_GPIOLIB
476 select NEED_MACH_GPIO_H
477 select NEED_RET_TO_USER
481 Support for Intel's IOP33X (XScale) family of processors.
486 select ARCH_HAS_DMA_SET_COHERENT_MASK
487 select ARCH_REQUIRE_GPIOLIB
490 select DMABOUNCE if PCI
491 select GENERIC_CLOCKEVENTS
492 select MIGHT_HAVE_PCI
493 select NEED_MACH_IO_H
494 select USB_EHCI_BIG_ENDIAN_DESC
495 select USB_EHCI_BIG_ENDIAN_MMIO
497 Support for Intel's IXP4XX (XScale) family of processors.
501 select ARCH_REQUIRE_GPIOLIB
503 select GENERIC_CLOCKEVENTS
504 select MIGHT_HAVE_PCI
508 select PLAT_ORION_LEGACY
509 select USB_ARCH_HAS_EHCI
511 Support for the Marvell Dove SoC 88AP510
514 bool "Marvell Kirkwood"
515 select ARCH_HAS_CPUFREQ
516 select ARCH_REQUIRE_GPIOLIB
518 select GENERIC_CLOCKEVENTS
523 select PINCTRL_KIRKWOOD
524 select PLAT_ORION_LEGACY
526 Support for the following Marvell Kirkwood series SoCs:
527 88F6180, 88F6192 and 88F6281.
530 bool "Marvell MV78xx0"
531 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
536 select PLAT_ORION_LEGACY
538 Support for the following Marvell MV78xx0 series SoCs:
544 select ARCH_REQUIRE_GPIOLIB
546 select GENERIC_CLOCKEVENTS
549 select PLAT_ORION_LEGACY
551 Support for the following Marvell Orion 5x series SoCs:
552 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
553 Orion-2 (5281), Orion-1-90 (6183).
556 bool "Marvell PXA168/910/MMP2"
558 select ARCH_REQUIRE_GPIOLIB
560 select GENERIC_ALLOCATOR
561 select GENERIC_CLOCKEVENTS
564 select MULTI_IRQ_HANDLER
565 select NEED_MACH_GPIO_H
570 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
573 bool "Micrel/Kendin KS8695"
574 select ARCH_REQUIRE_GPIOLIB
577 select GENERIC_CLOCKEVENTS
578 select NEED_MACH_MEMORY_H
580 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
581 System-on-Chip devices.
584 bool "Nuvoton W90X900 CPU"
585 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_CLOCKEVENTS
591 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
592 At present, the w90x900 has been renamed nuc900, regarding
593 the ARM series product line, you can login the following
594 link address to know more.
596 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
597 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
601 select ARCH_REQUIRE_GPIOLIB
606 select GENERIC_CLOCKEVENTS
609 select USB_ARCH_HAS_OHCI
612 Support for the NXP LPC32XX family of processors
615 bool "PXA2xx/PXA3xx-based"
617 select ARCH_HAS_CPUFREQ
619 select ARCH_REQUIRE_GPIOLIB
620 select ARM_CPU_SUSPEND if PM
624 select GENERIC_CLOCKEVENTS
627 select MULTI_IRQ_HANDLER
628 select NEED_MACH_GPIO_H
632 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
636 select ARCH_REQUIRE_GPIOLIB
638 select CLKSRC_OF if OF
640 select GENERIC_CLOCKEVENTS
642 Support for Qualcomm MSM/QSD based systems. This runs on the
643 apps processor of the MSM/QSD and depends on a shared memory
644 interface to the modem processor which runs the baseband
645 stack and controls some vital subsystems
646 (clock and power control, etc).
649 bool "Renesas SH-Mobile / R-Mobile"
650 select ARM_PATCH_PHYS_VIRT
652 select GENERIC_CLOCKEVENTS
653 select HAVE_ARM_SCU if SMP
654 select HAVE_ARM_TWD if SMP
656 select HAVE_MACH_CLKDEV
658 select MIGHT_HAVE_CACHE_L2X0
659 select MULTI_IRQ_HANDLER
662 select PM_GENERIC_DOMAINS if PM
665 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
670 select ARCH_MAY_HAVE_PC_FDC
671 select ARCH_SPARSEMEM_ENABLE
672 select ARCH_USES_GETTIMEOFFSET
675 select HAVE_PATA_PLATFORM
677 select NEED_MACH_IO_H
678 select NEED_MACH_MEMORY_H
682 On the Acorn Risc-PC, Linux can support the internal IDE disk and
683 CD-ROM interface, serial and parallel port, and the floppy drive.
687 select ARCH_HAS_CPUFREQ
689 select ARCH_REQUIRE_GPIOLIB
690 select ARCH_SPARSEMEM_ENABLE
695 select GENERIC_CLOCKEVENTS
698 select NEED_MACH_MEMORY_H
701 Support for StrongARM 11x0 based boards.
704 bool "Samsung S3C24XX SoCs"
705 select ARCH_HAS_CPUFREQ
706 select ARCH_REQUIRE_GPIOLIB
708 select CLKSRC_SAMSUNG_PWM
709 select GENERIC_CLOCKEVENTS
712 select HAVE_S3C2410_I2C if I2C
713 select HAVE_S3C2410_WATCHDOG if WATCHDOG
714 select HAVE_S3C_RTC if RTC_CLASS
715 select MULTI_IRQ_HANDLER
716 select NEED_MACH_GPIO_H
717 select NEED_MACH_IO_H
720 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
721 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
722 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
723 Samsung SMDK2410 development board (and derivatives).
726 bool "Samsung S3C64XX"
727 select ARCH_HAS_CPUFREQ
728 select ARCH_REQUIRE_GPIOLIB
731 select CLKSRC_SAMSUNG_PWM
733 select GENERIC_CLOCKEVENTS
736 select HAVE_S3C2410_I2C if I2C
737 select HAVE_S3C2410_WATCHDOG if WATCHDOG
739 select NEED_MACH_GPIO_H
743 select S3C_GPIO_TRACK
745 select SAMSUNG_CLKSRC
746 select SAMSUNG_GPIOLIB_4BIT
747 select SAMSUNG_WDT_RESET
748 select USB_ARCH_HAS_OHCI
750 Samsung S3C64XX series based systems
753 bool "Samsung S5P6440 S5P6450"
755 select CLKSRC_SAMSUNG_PWM
757 select GENERIC_CLOCKEVENTS
760 select HAVE_S3C2410_I2C if I2C
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
762 select HAVE_S3C_RTC if RTC_CLASS
763 select NEED_MACH_GPIO_H
765 select SAMSUNG_WDT_RESET
767 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
771 bool "Samsung S5PC100"
772 select ARCH_REQUIRE_GPIOLIB
774 select CLKSRC_SAMSUNG_PWM
776 select GENERIC_CLOCKEVENTS
779 select HAVE_S3C2410_I2C if I2C
780 select HAVE_S3C2410_WATCHDOG if WATCHDOG
781 select HAVE_S3C_RTC if RTC_CLASS
782 select NEED_MACH_GPIO_H
784 select SAMSUNG_WDT_RESET
786 Samsung S5PC100 series based systems
789 bool "Samsung S5PV210/S5PC110"
790 select ARCH_HAS_CPUFREQ
791 select ARCH_HAS_HOLES_MEMORYMODEL
792 select ARCH_SPARSEMEM_ENABLE
794 select CLKSRC_SAMSUNG_PWM
796 select GENERIC_CLOCKEVENTS
799 select HAVE_S3C2410_I2C if I2C
800 select HAVE_S3C2410_WATCHDOG if WATCHDOG
801 select HAVE_S3C_RTC if RTC_CLASS
802 select NEED_MACH_GPIO_H
803 select NEED_MACH_MEMORY_H
806 Samsung S5PV210/S5PC110 series based systems
809 bool "Samsung EXYNOS"
810 select ARCH_HAS_CPUFREQ
811 select ARCH_HAS_HOLES_MEMORYMODEL
812 select ARCH_REQUIRE_GPIOLIB
813 select ARCH_SPARSEMEM_ENABLE
818 select GENERIC_CLOCKEVENTS
820 select HAVE_S3C2410_I2C if I2C
821 select HAVE_S3C2410_WATCHDOG if WATCHDOG
822 select HAVE_S3C_RTC if RTC_CLASS
823 select NEED_MACH_MEMORY_H
827 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
831 select ARCH_USES_GETTIMEOFFSET
835 select NEED_MACH_MEMORY_H
840 Support for the StrongARM based Digital DNARD machine, also known
841 as "Shark" (<http://www.shark-linux.de/shark.html>).
845 select ARCH_HAS_HOLES_MEMORYMODEL
846 select ARCH_REQUIRE_GPIOLIB
848 select GENERIC_ALLOCATOR
849 select GENERIC_CLOCKEVENTS
850 select GENERIC_IRQ_CHIP
852 select NEED_MACH_GPIO_H
857 Support for TI's DaVinci platform.
862 select ARCH_HAS_CPUFREQ
863 select ARCH_HAS_HOLES_MEMORYMODEL
865 select ARCH_REQUIRE_GPIOLIB
868 select GENERIC_CLOCKEVENTS
869 select GENERIC_IRQ_CHIP
873 select NEED_MACH_IO_H if PCCARD
874 select NEED_MACH_MEMORY_H
876 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
880 menu "Multiple platform selection"
881 depends on ARCH_MULTIPLATFORM
883 comment "CPU Core family selection"
885 config ARCH_MULTI_V4T
886 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
887 depends on !ARCH_MULTI_V6_V7
888 select ARCH_MULTI_V4_V5
889 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
890 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
891 CPU_ARM925T || CPU_ARM940T)
894 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
895 depends on !ARCH_MULTI_V6_V7
896 select ARCH_MULTI_V4_V5
897 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
898 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
899 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
901 config ARCH_MULTI_V4_V5
905 bool "ARMv6 based platforms (ARM11)"
906 select ARCH_MULTI_V6_V7
910 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
912 select ARCH_MULTI_V6_V7
915 config ARCH_MULTI_V6_V7
918 config ARCH_MULTI_CPU_AUTO
919 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
925 # This is sorted alphabetically by mach-* pathname. However, plat-*
926 # Kconfigs may be included either alphabetically (according to the
927 # plat- suffix) or along side the corresponding mach-* source.
929 source "arch/arm/mach-mvebu/Kconfig"
931 source "arch/arm/mach-at91/Kconfig"
933 source "arch/arm/mach-bcm/Kconfig"
935 source "arch/arm/mach-bcm2835/Kconfig"
937 source "arch/arm/mach-clps711x/Kconfig"
939 source "arch/arm/mach-cns3xxx/Kconfig"
941 source "arch/arm/mach-davinci/Kconfig"
943 source "arch/arm/mach-dove/Kconfig"
945 source "arch/arm/mach-ep93xx/Kconfig"
947 source "arch/arm/mach-footbridge/Kconfig"
949 source "arch/arm/mach-gemini/Kconfig"
951 source "arch/arm/mach-highbank/Kconfig"
953 source "arch/arm/mach-integrator/Kconfig"
955 source "arch/arm/mach-iop32x/Kconfig"
957 source "arch/arm/mach-iop33x/Kconfig"
959 source "arch/arm/mach-iop13xx/Kconfig"
961 source "arch/arm/mach-ixp4xx/Kconfig"
963 source "arch/arm/mach-keystone/Kconfig"
965 source "arch/arm/mach-kirkwood/Kconfig"
967 source "arch/arm/mach-ks8695/Kconfig"
969 source "arch/arm/mach-msm/Kconfig"
971 source "arch/arm/mach-mv78xx0/Kconfig"
973 source "arch/arm/mach-imx/Kconfig"
975 source "arch/arm/mach-mxs/Kconfig"
977 source "arch/arm/mach-netx/Kconfig"
979 source "arch/arm/mach-nomadik/Kconfig"
981 source "arch/arm/mach-nspire/Kconfig"
983 source "arch/arm/plat-omap/Kconfig"
985 source "arch/arm/mach-omap1/Kconfig"
987 source "arch/arm/mach-omap2/Kconfig"
989 source "arch/arm/mach-orion5x/Kconfig"
991 source "arch/arm/mach-picoxcell/Kconfig"
993 source "arch/arm/mach-pxa/Kconfig"
994 source "arch/arm/plat-pxa/Kconfig"
996 source "arch/arm/mach-mmp/Kconfig"
998 source "arch/arm/mach-realview/Kconfig"
1000 source "arch/arm/mach-rockchip/Kconfig"
1002 source "arch/arm/mach-sa1100/Kconfig"
1004 source "arch/arm/plat-samsung/Kconfig"
1006 source "arch/arm/mach-socfpga/Kconfig"
1008 source "arch/arm/mach-spear/Kconfig"
1010 source "arch/arm/mach-sti/Kconfig"
1012 source "arch/arm/mach-s3c24xx/Kconfig"
1015 source "arch/arm/mach-s3c64xx/Kconfig"
1018 source "arch/arm/mach-s5p64x0/Kconfig"
1020 source "arch/arm/mach-s5pc100/Kconfig"
1022 source "arch/arm/mach-s5pv210/Kconfig"
1024 source "arch/arm/mach-exynos/Kconfig"
1026 source "arch/arm/mach-shmobile/Kconfig"
1028 source "arch/arm/mach-sunxi/Kconfig"
1030 source "arch/arm/mach-prima2/Kconfig"
1032 source "arch/arm/mach-tegra/Kconfig"
1034 source "arch/arm/mach-u300/Kconfig"
1036 source "arch/arm/mach-ux500/Kconfig"
1038 source "arch/arm/mach-versatile/Kconfig"
1040 source "arch/arm/mach-vexpress/Kconfig"
1041 source "arch/arm/plat-versatile/Kconfig"
1043 source "arch/arm/mach-virt/Kconfig"
1045 source "arch/arm/mach-vt8500/Kconfig"
1047 source "arch/arm/mach-w90x900/Kconfig"
1049 source "arch/arm/mach-zynq/Kconfig"
1051 # Definitions to make life easier
1057 select GENERIC_CLOCKEVENTS
1063 select GENERIC_IRQ_CHIP
1066 config PLAT_ORION_LEGACY
1073 config PLAT_VERSATILE
1076 config ARM_TIMER_SP804
1079 select CLKSRC_OF if OF
1081 source arch/arm/mm/Kconfig
1085 default 16 if ARCH_EP93XX
1089 bool "Enable iWMMXt support" if !CPU_PJ4
1090 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1091 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1093 Enable support for iWMMXt context switching at run time if
1094 running on a CPU that supports it.
1098 depends on CPU_XSCALE
1101 config MULTI_IRQ_HANDLER
1104 Allow each machine to specify it's own IRQ handler at run time.
1107 source "arch/arm/Kconfig-nommu"
1110 config PJ4B_ERRATA_4742
1111 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1112 depends on CPU_PJ4B && MACH_ARMADA_370
1115 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1116 Event (WFE) IDLE states, a specific timing sensitivity exists between
1117 the retiring WFI/WFE instructions and the newly issued subsequent
1118 instructions. This sensitivity can result in a CPU hang scenario.
1120 The software must insert either a Data Synchronization Barrier (DSB)
1121 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1124 config ARM_ERRATA_326103
1125 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1128 Executing a SWP instruction to read-only memory does not set bit 11
1129 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1130 treat the access as a read, preventing a COW from occurring and
1131 causing the faulting task to livelock.
1133 config ARM_ERRATA_411920
1134 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1135 depends on CPU_V6 || CPU_V6K
1137 Invalidation of the Instruction Cache operation can
1138 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1139 It does not affect the MPCore. This option enables the ARM Ltd.
1140 recommended workaround.
1142 config ARM_ERRATA_430973
1143 bool "ARM errata: Stale prediction on replaced interworking branch"
1146 This option enables the workaround for the 430973 Cortex-A8
1147 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1148 interworking branch is replaced with another code sequence at the
1149 same virtual address, whether due to self-modifying code or virtual
1150 to physical address re-mapping, Cortex-A8 does not recover from the
1151 stale interworking branch prediction. This results in Cortex-A8
1152 executing the new code sequence in the incorrect ARM or Thumb state.
1153 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1154 and also flushes the branch target cache at every context switch.
1155 Note that setting specific bits in the ACTLR register may not be
1156 available in non-secure mode.
1158 config ARM_ERRATA_458693
1159 bool "ARM errata: Processor deadlock when a false hazard is created"
1161 depends on !ARCH_MULTIPLATFORM
1163 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1164 erratum. For very specific sequences of memory operations, it is
1165 possible for a hazard condition intended for a cache line to instead
1166 be incorrectly associated with a different cache line. This false
1167 hazard might then cause a processor deadlock. The workaround enables
1168 the L1 caching of the NEON accesses and disables the PLD instruction
1169 in the ACTLR register. Note that setting specific bits in the ACTLR
1170 register may not be available in non-secure mode.
1172 config ARM_ERRATA_460075
1173 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1175 depends on !ARCH_MULTIPLATFORM
1177 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1178 erratum. Any asynchronous access to the L2 cache may encounter a
1179 situation in which recent store transactions to the L2 cache are lost
1180 and overwritten with stale memory contents from external memory. The
1181 workaround disables the write-allocate mode for the L2 cache via the
1182 ACTLR register. Note that setting specific bits in the ACTLR register
1183 may not be available in non-secure mode.
1185 config ARM_ERRATA_742230
1186 bool "ARM errata: DMB operation may be faulty"
1187 depends on CPU_V7 && SMP
1188 depends on !ARCH_MULTIPLATFORM
1190 This option enables the workaround for the 742230 Cortex-A9
1191 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1192 between two write operations may not ensure the correct visibility
1193 ordering of the two writes. This workaround sets a specific bit in
1194 the diagnostic register of the Cortex-A9 which causes the DMB
1195 instruction to behave as a DSB, ensuring the correct behaviour of
1198 config ARM_ERRATA_742231
1199 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1200 depends on CPU_V7 && SMP
1201 depends on !ARCH_MULTIPLATFORM
1203 This option enables the workaround for the 742231 Cortex-A9
1204 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1205 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1206 accessing some data located in the same cache line, may get corrupted
1207 data due to bad handling of the address hazard when the line gets
1208 replaced from one of the CPUs at the same time as another CPU is
1209 accessing it. This workaround sets specific bits in the diagnostic
1210 register of the Cortex-A9 which reduces the linefill issuing
1211 capabilities of the processor.
1213 config PL310_ERRATA_588369
1214 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1215 depends on CACHE_L2X0
1217 The PL310 L2 cache controller implements three types of Clean &
1218 Invalidate maintenance operations: by Physical Address
1219 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1220 They are architecturally defined to behave as the execution of a
1221 clean operation followed immediately by an invalidate operation,
1222 both performing to the same memory location. This functionality
1223 is not correctly implemented in PL310 as clean lines are not
1224 invalidated as a result of these operations.
1226 config ARM_ERRATA_643719
1227 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1228 depends on CPU_V7 && SMP
1230 This option enables the workaround for the 643719 Cortex-A9 (prior to
1231 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1232 register returns zero when it should return one. The workaround
1233 corrects this value, ensuring cache maintenance operations which use
1234 it behave as intended and avoiding data corruption.
1236 config ARM_ERRATA_720789
1237 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1240 This option enables the workaround for the 720789 Cortex-A9 (prior to
1241 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1242 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1243 As a consequence of this erratum, some TLB entries which should be
1244 invalidated are not, resulting in an incoherency in the system page
1245 tables. The workaround changes the TLB flushing routines to invalidate
1246 entries regardless of the ASID.
1248 config PL310_ERRATA_727915
1249 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1250 depends on CACHE_L2X0
1252 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1253 operation (offset 0x7FC). This operation runs in background so that
1254 PL310 can handle normal accesses while it is in progress. Under very
1255 rare circumstances, due to this erratum, write data can be lost when
1256 PL310 treats a cacheable write transaction during a Clean &
1257 Invalidate by Way operation.
1259 config ARM_ERRATA_743622
1260 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1262 depends on !ARCH_MULTIPLATFORM
1264 This option enables the workaround for the 743622 Cortex-A9
1265 (r2p*) erratum. Under very rare conditions, a faulty
1266 optimisation in the Cortex-A9 Store Buffer may lead to data
1267 corruption. This workaround sets a specific bit in the diagnostic
1268 register of the Cortex-A9 which disables the Store Buffer
1269 optimisation, preventing the defect from occurring. This has no
1270 visible impact on the overall performance or power consumption of the
1273 config ARM_ERRATA_751472
1274 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1276 depends on !ARCH_MULTIPLATFORM
1278 This option enables the workaround for the 751472 Cortex-A9 (prior
1279 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1280 completion of a following broadcasted operation if the second
1281 operation is received by a CPU before the ICIALLUIS has completed,
1282 potentially leading to corrupted entries in the cache or TLB.
1284 config PL310_ERRATA_753970
1285 bool "PL310 errata: cache sync operation may be faulty"
1286 depends on CACHE_PL310
1288 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1290 Under some condition the effect of cache sync operation on
1291 the store buffer still remains when the operation completes.
1292 This means that the store buffer is always asked to drain and
1293 this prevents it from merging any further writes. The workaround
1294 is to replace the normal offset of cache sync operation (0x730)
1295 by another offset targeting an unmapped PL310 register 0x740.
1296 This has the same effect as the cache sync operation: store buffer
1297 drain and waiting for all buffers empty.
1299 config ARM_ERRATA_754322
1300 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1303 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1304 r3p*) erratum. A speculative memory access may cause a page table walk
1305 which starts prior to an ASID switch but completes afterwards. This
1306 can populate the micro-TLB with a stale entry which may be hit with
1307 the new ASID. This workaround places two dsb instructions in the mm
1308 switching code so that no page table walks can cross the ASID switch.
1310 config ARM_ERRATA_754327
1311 bool "ARM errata: no automatic Store Buffer drain"
1312 depends on CPU_V7 && SMP
1314 This option enables the workaround for the 754327 Cortex-A9 (prior to
1315 r2p0) erratum. The Store Buffer does not have any automatic draining
1316 mechanism and therefore a livelock may occur if an external agent
1317 continuously polls a memory location waiting to observe an update.
1318 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1319 written polling loops from denying visibility of updates to memory.
1321 config ARM_ERRATA_364296
1322 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1325 This options enables the workaround for the 364296 ARM1136
1326 r0p2 erratum (possible cache data corruption with
1327 hit-under-miss enabled). It sets the undocumented bit 31 in
1328 the auxiliary control register and the FI bit in the control
1329 register, thus disabling hit-under-miss without putting the
1330 processor into full low interrupt latency mode. ARM11MPCore
1333 config ARM_ERRATA_764369
1334 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1335 depends on CPU_V7 && SMP
1337 This option enables the workaround for erratum 764369
1338 affecting Cortex-A9 MPCore with two or more processors (all
1339 current revisions). Under certain timing circumstances, a data
1340 cache line maintenance operation by MVA targeting an Inner
1341 Shareable memory region may fail to proceed up to either the
1342 Point of Coherency or to the Point of Unification of the
1343 system. This workaround adds a DSB instruction before the
1344 relevant cache maintenance functions and sets a specific bit
1345 in the diagnostic control register of the SCU.
1347 config PL310_ERRATA_769419
1348 bool "PL310 errata: no automatic Store Buffer drain"
1349 depends on CACHE_L2X0
1351 On revisions of the PL310 prior to r3p2, the Store Buffer does
1352 not automatically drain. This can cause normal, non-cacheable
1353 writes to be retained when the memory system is idle, leading
1354 to suboptimal I/O performance for drivers using coherent DMA.
1355 This option adds a write barrier to the cpu_idle loop so that,
1356 on systems with an outer cache, the store buffer is drained
1359 config ARM_ERRATA_775420
1360 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1363 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1364 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1365 operation aborts with MMU exception, it might cause the processor
1366 to deadlock. This workaround puts DSB before executing ISB if
1367 an abort may occur on cache maintenance.
1369 config ARM_ERRATA_798181
1370 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1371 depends on CPU_V7 && SMP
1373 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1374 adequately shooting down all use of the old entries. This
1375 option enables the Linux kernel workaround for this erratum
1376 which sends an IPI to the CPUs that are running the same ASID
1377 as the one being invalidated.
1379 config ARM_ERRATA_773022
1380 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1383 This option enables the workaround for the 773022 Cortex-A15
1384 (up to r0p4) erratum. In certain rare sequences of code, the
1385 loop buffer may deliver incorrect instructions. This
1386 workaround disables the loop buffer to avoid the erratum.
1390 source "arch/arm/common/Kconfig"
1400 Find out whether you have ISA slots on your motherboard. ISA is the
1401 name of a bus system, i.e. the way the CPU talks to the other stuff
1402 inside your box. Other bus systems are PCI, EISA, MicroChannel
1403 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1404 newer boards don't support it. If you have ISA, say Y, otherwise N.
1406 # Select ISA DMA controller support
1411 # Select ISA DMA interface
1416 bool "PCI support" if MIGHT_HAVE_PCI
1418 Find out whether you have a PCI motherboard. PCI is the name of a
1419 bus system, i.e. the way the CPU talks to the other stuff inside
1420 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1421 VESA. If you have PCI, say Y, otherwise N.
1427 config PCI_NANOENGINE
1428 bool "BSE nanoEngine PCI support"
1429 depends on SA1100_NANOENGINE
1431 Enable PCI on the BSE nanoEngine board.
1436 # Select the host bridge type
1437 config PCI_HOST_VIA82C505
1439 depends on PCI && ARCH_SHARK
1442 config PCI_HOST_ITE8152
1444 depends on PCI && MACH_ARMCORE
1448 source "drivers/pci/Kconfig"
1449 source "drivers/pci/pcie/Kconfig"
1451 source "drivers/pcmcia/Kconfig"
1455 menu "Kernel Features"
1460 This option should be selected by machines which have an SMP-
1463 The only effect of this option is to make the SMP-related
1464 options available to the user for configuration.
1467 bool "Symmetric Multi-Processing"
1468 depends on CPU_V6K || CPU_V7
1469 depends on GENERIC_CLOCKEVENTS
1471 depends on MMU || ARM_MPU
1472 select USE_GENERIC_SMP_HELPERS
1474 This enables support for systems with more than one CPU. If you have
1475 a system with only one CPU, like most personal computers, say N. If
1476 you have a system with more than one CPU, say Y.
1478 If you say N here, the kernel will run on single and multiprocessor
1479 machines, but will use only one CPU of a multiprocessor machine. If
1480 you say Y here, the kernel will run on many, but not all, single
1481 processor machines. On a single processor machine, the kernel will
1482 run faster if you say N here.
1484 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1485 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1486 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1488 If you don't know what to do here, say N.
1491 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1492 depends on SMP && !XIP_KERNEL && MMU
1495 SMP kernels contain instructions which fail on non-SMP processors.
1496 Enabling this option allows the kernel to modify itself to make
1497 these instructions safe. Disabling it allows about 1K of space
1500 If you don't know what to do here, say Y.
1502 config ARM_CPU_TOPOLOGY
1503 bool "Support cpu topology definition"
1504 depends on SMP && CPU_V7
1507 Support ARM cpu topology definition. The MPIDR register defines
1508 affinity between processors which is then used to describe the cpu
1509 topology of an ARM System.
1512 bool "Multi-core scheduler support"
1513 depends on ARM_CPU_TOPOLOGY
1515 Multi-core scheduler support improves the CPU scheduler's decision
1516 making when dealing with multi-core CPU chips at a cost of slightly
1517 increased overhead in some places. If unsure say N here.
1520 bool "SMT scheduler support"
1521 depends on ARM_CPU_TOPOLOGY
1523 Improves the CPU scheduler's decision making when dealing with
1524 MultiThreading at a cost of slightly increased overhead in some
1525 places. If unsure say N here.
1530 This option enables support for the ARM system coherency unit
1532 config HAVE_ARM_ARCH_TIMER
1533 bool "Architected timer support"
1535 select ARM_ARCH_TIMER
1537 This option enables support for the ARM architected timer
1542 select CLKSRC_OF if OF
1544 This options enables support for the ARM timer and watchdog unit
1547 bool "Multi-Cluster Power Management"
1548 depends on CPU_V7 && SMP
1550 This option provides the common power management infrastructure
1551 for (multi-)cluster based systems, such as big.LITTLE based
1555 bool "big.LITTLE support (Experimental)"
1556 depends on CPU_V7 && SMP
1559 This option enables support selections for the big.LITTLE
1560 system architecture.
1563 bool "big.LITTLE switcher support"
1564 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1566 select ARM_CPU_SUSPEND
1568 The big.LITTLE "switcher" provides the core functionality to
1569 transparently handle transition between a cluster of A15's
1570 and a cluster of A7's in a big.LITTLE system.
1572 config BL_SWITCHER_DUMMY_IF
1573 tristate "Simple big.LITTLE switcher user interface"
1574 depends on BL_SWITCHER && DEBUG_KERNEL
1576 This is a simple and dummy char dev interface to control
1577 the big.LITTLE switcher core code. It is meant for
1578 debugging purposes only.
1581 prompt "Memory split"
1584 Select the desired split between kernel and user memory.
1586 If you are not absolutely sure what you are doing, leave this
1590 bool "3G/1G user/kernel split"
1592 bool "2G/2G user/kernel split"
1594 bool "1G/3G user/kernel split"
1599 default 0x40000000 if VMSPLIT_1G
1600 default 0x80000000 if VMSPLIT_2G
1604 int "Maximum number of CPUs (2-32)"
1610 bool "Support for hot-pluggable CPUs"
1613 Say Y here to experiment with turning CPUs off and on. CPUs
1614 can be controlled through /sys/devices/system/cpu.
1617 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1620 Say Y here if you want Linux to communicate with system firmware
1621 implementing the PSCI specification for CPU-centric power
1622 management operations described in ARM document number ARM DEN
1623 0022A ("Power State Coordination Interface System Software on
1626 # The GPIO number here must be sorted by descending number. In case of
1627 # a multiplatform kernel, we just want the highest value required by the
1628 # selected platforms.
1631 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1632 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1633 default 392 if ARCH_U8500
1634 default 352 if ARCH_VT8500
1635 default 288 if ARCH_SUNXI
1636 default 264 if MACH_H4700
1639 Maximum number of GPIOs in the system.
1641 If unsure, leave the default value.
1643 source kernel/Kconfig.preempt
1647 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1648 ARCH_S5PV210 || ARCH_EXYNOS4
1649 default AT91_TIMER_HZ if ARCH_AT91
1650 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1654 depends on HZ_FIXED = 0
1655 prompt "Timer frequency"
1679 default HZ_FIXED if HZ_FIXED != 0
1680 default 100 if HZ_100
1681 default 200 if HZ_200
1682 default 250 if HZ_250
1683 default 300 if HZ_300
1684 default 500 if HZ_500
1688 def_bool HIGH_RES_TIMERS
1691 def_bool HIGH_RES_TIMERS
1693 config THUMB2_KERNEL
1694 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1695 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1696 default y if CPU_THUMBONLY
1698 select ARM_ASM_UNIFIED
1701 By enabling this option, the kernel will be compiled in
1702 Thumb-2 mode. A compiler/assembler that understand the unified
1703 ARM-Thumb syntax is needed.
1707 config THUMB2_AVOID_R_ARM_THM_JUMP11
1708 bool "Work around buggy Thumb-2 short branch relocations in gas"
1709 depends on THUMB2_KERNEL && MODULES
1712 Various binutils versions can resolve Thumb-2 branches to
1713 locally-defined, preemptible global symbols as short-range "b.n"
1714 branch instructions.
1716 This is a problem, because there's no guarantee the final
1717 destination of the symbol, or any candidate locations for a
1718 trampoline, are within range of the branch. For this reason, the
1719 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1720 relocation in modules at all, and it makes little sense to add
1723 The symptom is that the kernel fails with an "unsupported
1724 relocation" error when loading some modules.
1726 Until fixed tools are available, passing
1727 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1728 code which hits this problem, at the cost of a bit of extra runtime
1729 stack usage in some cases.
1731 The problem is described in more detail at:
1732 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1734 Only Thumb-2 kernels are affected.
1736 Unless you are sure your tools don't have this problem, say Y.
1738 config ARM_ASM_UNIFIED
1742 bool "Use the ARM EABI to compile the kernel"
1744 This option allows for the kernel to be compiled using the latest
1745 ARM ABI (aka EABI). This is only useful if you are using a user
1746 space environment that is also compiled with EABI.
1748 Since there are major incompatibilities between the legacy ABI and
1749 EABI, especially with regard to structure member alignment, this
1750 option also changes the kernel syscall calling convention to
1751 disambiguate both ABIs and allow for backward compatibility support
1752 (selected with CONFIG_OABI_COMPAT).
1754 To use this you need GCC version 4.0.0 or later.
1757 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1758 depends on AEABI && !THUMB2_KERNEL
1761 This option preserves the old syscall interface along with the
1762 new (ARM EABI) one. It also provides a compatibility layer to
1763 intercept syscalls that have structure arguments which layout
1764 in memory differs between the legacy ABI and the new ARM EABI
1765 (only for non "thumb" binaries). This option adds a tiny
1766 overhead to all syscalls and produces a slightly larger kernel.
1767 If you know you'll be using only pure EABI user space then you
1768 can say N here. If this option is not selected and you attempt
1769 to execute a legacy ABI binary then the result will be
1770 UNPREDICTABLE (in fact it can be predicted that it won't work
1771 at all). If in doubt say Y.
1773 config ARCH_HAS_HOLES_MEMORYMODEL
1776 config ARCH_SPARSEMEM_ENABLE
1779 config ARCH_SPARSEMEM_DEFAULT
1780 def_bool ARCH_SPARSEMEM_ENABLE
1782 config ARCH_SELECT_MEMORY_MODEL
1783 def_bool ARCH_SPARSEMEM_ENABLE
1785 config HAVE_ARCH_PFN_VALID
1786 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1789 bool "High Memory Support"
1792 The address space of ARM processors is only 4 Gigabytes large
1793 and it has to accommodate user address space, kernel address
1794 space as well as some memory mapped IO. That means that, if you
1795 have a large amount of physical memory and/or IO, not all of the
1796 memory can be "permanently mapped" by the kernel. The physical
1797 memory that is not permanently mapped is called "high memory".
1799 Depending on the selected kernel/user memory split, minimum
1800 vmalloc space and actual amount of RAM, you may not need this
1801 option which should result in a slightly faster kernel.
1806 bool "Allocate 2nd-level pagetables from highmem"
1809 config HW_PERF_EVENTS
1810 bool "Enable hardware performance counter support for perf events"
1811 depends on PERF_EVENTS
1814 Enable hardware performance counter support for perf events. If
1815 disabled, perf events will use software events only.
1817 config SYS_SUPPORTS_HUGETLBFS
1821 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1825 config ARCH_WANT_GENERAL_HUGETLB
1830 config FORCE_MAX_ZONEORDER
1831 int "Maximum zone order" if ARCH_SHMOBILE
1832 range 11 64 if ARCH_SHMOBILE
1833 default "12" if SOC_AM33XX
1834 default "9" if SA1111
1837 The kernel memory allocator divides physically contiguous memory
1838 blocks into "zones", where each zone is a power of two number of
1839 pages. This option selects the largest power of two that the kernel
1840 keeps in the memory allocator. If you need to allocate very large
1841 blocks of physically contiguous memory, then you may need to
1842 increase this value.
1844 This config option is actually maximum order plus one. For example,
1845 a value of 11 means that the largest free memory block is 2^10 pages.
1847 config ALIGNMENT_TRAP
1849 depends on CPU_CP15_MMU
1850 default y if !ARCH_EBSA110
1851 select HAVE_PROC_CPU if PROC_FS
1853 ARM processors cannot fetch/store information which is not
1854 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1855 address divisible by 4. On 32-bit ARM processors, these non-aligned
1856 fetch/store instructions will be emulated in software if you say
1857 here, which has a severe performance impact. This is necessary for
1858 correct operation of some network protocols. With an IP-only
1859 configuration it is safe to say N, otherwise say Y.
1861 config UACCESS_WITH_MEMCPY
1862 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1864 default y if CPU_FEROCEON
1866 Implement faster copy_to_user and clear_user methods for CPU
1867 cores where a 8-word STM instruction give significantly higher
1868 memory write throughput than a sequence of individual 32bit stores.
1870 A possible side effect is a slight increase in scheduling latency
1871 between threads sharing the same address space if they invoke
1872 such copy operations with large buffers.
1874 However, if the CPU data cache is using a write-allocate mode,
1875 this option is unlikely to provide any performance gain.
1879 prompt "Enable seccomp to safely compute untrusted bytecode"
1881 This kernel feature is useful for number crunching applications
1882 that may need to compute untrusted bytecode during their
1883 execution. By using pipes or other transports made available to
1884 the process as file descriptors supporting the read/write
1885 syscalls, it's possible to isolate those applications in
1886 their own address space using seccomp. Once seccomp is
1887 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1888 and the task is only allowed to execute a few safe syscalls
1889 defined by each seccomp mode.
1891 config CC_STACKPROTECTOR
1892 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1894 This option turns on the -fstack-protector GCC feature. This
1895 feature puts, at the beginning of functions, a canary value on
1896 the stack just before the return address, and validates
1897 the value just before actually returning. Stack based buffer
1898 overflows (that need to overwrite this return address) now also
1899 overwrite the canary, which gets detected and the attack is then
1900 neutralized via a kernel panic.
1901 This feature requires gcc version 4.2 or above.
1908 bool "Xen guest support on ARM (EXPERIMENTAL)"
1909 depends on ARM && AEABI && OF
1910 depends on CPU_V7 && !CPU_V6
1911 depends on !GENERIC_ATOMIC64
1914 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1921 bool "Flattened Device Tree support"
1924 select OF_EARLY_FLATTREE
1926 Include support for flattened device tree machine descriptions.
1929 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1932 This is the traditional way of passing data to the kernel at boot
1933 time. If you are solely relying on the flattened device tree (or
1934 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1935 to remove ATAGS support from your kernel binary. If unsure,
1938 config DEPRECATED_PARAM_STRUCT
1939 bool "Provide old way to pass kernel parameters"
1942 This was deprecated in 2001 and announced to live on for 5 years.
1943 Some old boot loaders still use this way.
1945 # Compressed boot loader in ROM. Yes, we really want to ask about
1946 # TEXT and BSS so we preserve their values in the config files.
1947 config ZBOOT_ROM_TEXT
1948 hex "Compressed ROM boot loader base address"
1951 The physical address at which the ROM-able zImage is to be
1952 placed in the target. Platforms which normally make use of
1953 ROM-able zImage formats normally set this to a suitable
1954 value in their defconfig file.
1956 If ZBOOT_ROM is not enabled, this has no effect.
1958 config ZBOOT_ROM_BSS
1959 hex "Compressed ROM boot loader BSS address"
1962 The base address of an area of read/write memory in the target
1963 for the ROM-able zImage which must be available while the
1964 decompressor is running. It must be large enough to hold the
1965 entire decompressed kernel plus an additional 128 KiB.
1966 Platforms which normally make use of ROM-able zImage formats
1967 normally set this to a suitable value in their defconfig file.
1969 If ZBOOT_ROM is not enabled, this has no effect.
1972 bool "Compressed boot loader in ROM/flash"
1973 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1975 Say Y here if you intend to execute your compressed kernel image
1976 (zImage) directly from ROM or flash. If unsure, say N.
1979 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1980 depends on ZBOOT_ROM && ARCH_SH7372
1981 default ZBOOT_ROM_NONE
1983 Include experimental SD/MMC loading code in the ROM-able zImage.
1984 With this enabled it is possible to write the ROM-able zImage
1985 kernel image to an MMC or SD card and boot the kernel straight
1986 from the reset vector. At reset the processor Mask ROM will load
1987 the first part of the ROM-able zImage which in turn loads the
1988 rest the kernel image to RAM.
1990 config ZBOOT_ROM_NONE
1991 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1993 Do not load image from SD or MMC
1995 config ZBOOT_ROM_MMCIF
1996 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1998 Load image from MMCIF hardware block.
2000 config ZBOOT_ROM_SH_MOBILE_SDHI
2001 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2003 Load image from SDHI hardware block
2007 config ARM_APPENDED_DTB
2008 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2009 depends on OF && !ZBOOT_ROM
2011 With this option, the boot code will look for a device tree binary
2012 (DTB) appended to zImage
2013 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2015 This is meant as a backward compatibility convenience for those
2016 systems with a bootloader that can't be upgraded to accommodate
2017 the documented boot protocol using a device tree.
2019 Beware that there is very little in terms of protection against
2020 this option being confused by leftover garbage in memory that might
2021 look like a DTB header after a reboot if no actual DTB is appended
2022 to zImage. Do not leave this option active in a production kernel
2023 if you don't intend to always append a DTB. Proper passing of the
2024 location into r2 of a bootloader provided DTB is always preferable
2027 config ARM_ATAG_DTB_COMPAT
2028 bool "Supplement the appended DTB with traditional ATAG information"
2029 depends on ARM_APPENDED_DTB
2031 Some old bootloaders can't be updated to a DTB capable one, yet
2032 they provide ATAGs with memory configuration, the ramdisk address,
2033 the kernel cmdline string, etc. Such information is dynamically
2034 provided by the bootloader and can't always be stored in a static
2035 DTB. To allow a device tree enabled kernel to be used with such
2036 bootloaders, this option allows zImage to extract the information
2037 from the ATAG list and store it at run time into the appended DTB.
2040 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2041 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2043 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2044 bool "Use bootloader kernel arguments if available"
2046 Uses the command-line options passed by the boot loader instead of
2047 the device tree bootargs property. If the boot loader doesn't provide
2048 any, the device tree bootargs property will be used.
2050 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2051 bool "Extend with bootloader kernel arguments"
2053 The command-line arguments provided by the boot loader will be
2054 appended to the the device tree bootargs property.
2059 string "Default kernel command string"
2062 On some architectures (EBSA110 and CATS), there is currently no way
2063 for the boot loader to pass arguments to the kernel. For these
2064 architectures, you should supply some command-line options at build
2065 time by entering them here. As a minimum, you should specify the
2066 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2069 prompt "Kernel command line type" if CMDLINE != ""
2070 default CMDLINE_FROM_BOOTLOADER
2073 config CMDLINE_FROM_BOOTLOADER
2074 bool "Use bootloader kernel arguments if available"
2076 Uses the command-line options passed by the boot loader. If
2077 the boot loader doesn't provide any, the default kernel command
2078 string provided in CMDLINE will be used.
2080 config CMDLINE_EXTEND
2081 bool "Extend bootloader kernel arguments"
2083 The command-line arguments provided by the boot loader will be
2084 appended to the default kernel command string.
2086 config CMDLINE_FORCE
2087 bool "Always use the default kernel command string"
2089 Always use the default kernel command string, even if the boot
2090 loader passes other arguments to the kernel.
2091 This is useful if you cannot or don't want to change the
2092 command-line options your boot loader passes to the kernel.
2096 bool "Kernel Execute-In-Place from ROM"
2097 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2099 Execute-In-Place allows the kernel to run from non-volatile storage
2100 directly addressable by the CPU, such as NOR flash. This saves RAM
2101 space since the text section of the kernel is not loaded from flash
2102 to RAM. Read-write sections, such as the data section and stack,
2103 are still copied to RAM. The XIP kernel is not compressed since
2104 it has to run directly from flash, so it will take more space to
2105 store it. The flash address used to link the kernel object files,
2106 and for storing it, is configuration dependent. Therefore, if you
2107 say Y here, you must know the proper physical address where to
2108 store the kernel image depending on your own flash memory usage.
2110 Also note that the make target becomes "make xipImage" rather than
2111 "make zImage" or "make Image". The final kernel binary to put in
2112 ROM memory will be arch/arm/boot/xipImage.
2116 config XIP_PHYS_ADDR
2117 hex "XIP Kernel Physical Location"
2118 depends on XIP_KERNEL
2119 default "0x00080000"
2121 This is the physical address in your flash memory the kernel will
2122 be linked for and stored to. This address is dependent on your
2126 bool "Kexec system call (EXPERIMENTAL)"
2127 depends on (!SMP || PM_SLEEP_SMP)
2129 kexec is a system call that implements the ability to shutdown your
2130 current kernel, and to start another kernel. It is like a reboot
2131 but it is independent of the system firmware. And like a reboot
2132 you can start any kernel with it, not just Linux.
2134 It is an ongoing process to be certain the hardware in a machine
2135 is properly shutdown, so do not be surprised if this code does not
2136 initially work for you.
2139 bool "Export atags in procfs"
2140 depends on ATAGS && KEXEC
2143 Should the atags used to boot the kernel be exported in an "atags"
2144 file in procfs. Useful with kexec.
2147 bool "Build kdump crash kernel (EXPERIMENTAL)"
2149 Generate crash dump after being started by kexec. This should
2150 be normally only set in special crash dump kernels which are
2151 loaded in the main kernel with kexec-tools into a specially
2152 reserved region and then later executed after a crash by
2153 kdump/kexec. The crash dump kernel must be compiled to a
2154 memory address not used by the main kernel
2156 For more details see Documentation/kdump/kdump.txt
2158 config AUTO_ZRELADDR
2159 bool "Auto calculation of the decompressed kernel image address"
2160 depends on !ZBOOT_ROM
2162 ZRELADDR is the physical address where the decompressed kernel
2163 image will be placed. If AUTO_ZRELADDR is selected, the address
2164 will be determined at run-time by masking the current IP with
2165 0xf8000000. This assumes the zImage being placed in the first 128MB
2166 from start of memory.
2170 menu "CPU Power Management"
2173 source "drivers/cpufreq/Kconfig"
2176 source "drivers/cpuidle/Kconfig"
2180 menu "Floating point emulation"
2182 comment "At least one emulation must be selected"
2185 bool "NWFPE math emulation"
2186 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2188 Say Y to include the NWFPE floating point emulator in the kernel.
2189 This is necessary to run most binaries. Linux does not currently
2190 support floating point hardware so you need to say Y here even if
2191 your machine has an FPA or floating point co-processor podule.
2193 You may say N here if you are going to load the Acorn FPEmulator
2194 early in the bootup.
2197 bool "Support extended precision"
2198 depends on FPE_NWFPE
2200 Say Y to include 80-bit support in the kernel floating-point
2201 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2202 Note that gcc does not generate 80-bit operations by default,
2203 so in most cases this option only enlarges the size of the
2204 floating point emulator without any good reason.
2206 You almost surely want to say N here.
2209 bool "FastFPE math emulation (EXPERIMENTAL)"
2210 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2212 Say Y here to include the FAST floating point emulator in the kernel.
2213 This is an experimental much faster emulator which now also has full
2214 precision for the mantissa. It does not support any exceptions.
2215 It is very simple, and approximately 3-6 times faster than NWFPE.
2217 It should be sufficient for most programs. It may be not suitable
2218 for scientific calculations, but you have to check this for yourself.
2219 If you do not feel you need a faster FP emulation you should better
2223 bool "VFP-format floating point maths"
2224 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2226 Say Y to include VFP support code in the kernel. This is needed
2227 if your hardware includes a VFP unit.
2229 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2230 release notes and additional status information.
2232 Say N if your target does not have VFP hardware.
2240 bool "Advanced SIMD (NEON) Extension support"
2241 depends on VFPv3 && CPU_V7
2243 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2246 config KERNEL_MODE_NEON
2247 bool "Support for NEON in kernel mode"
2248 depends on NEON && AEABI
2250 Say Y to include support for NEON in kernel mode.
2254 menu "Userspace binary formats"
2256 source "fs/Kconfig.binfmt"
2259 tristate "RISC OS personality"
2262 Say Y here to include the kernel code necessary if you want to run
2263 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2264 experimental; if this sounds frightening, say N and sleep in peace.
2265 You can also say M here to compile this support as a module (which
2266 will be called arthur).
2270 menu "Power management options"
2272 source "kernel/power/Kconfig"
2274 config ARCH_SUSPEND_POSSIBLE
2275 depends on !ARCH_S5PC100
2276 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2277 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2280 config ARM_CPU_SUSPEND
2285 source "net/Kconfig"
2287 source "drivers/Kconfig"
2291 source "arch/arm/Kconfig.debug"
2293 source "security/Kconfig"
2295 source "crypto/Kconfig"
2297 source "lib/Kconfig"
2299 source "arch/arm/kvm/Kconfig"