4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_KERNEL_THREAD
16 select GENERIC_KERNEL_EXECVE
17 select GENERIC_PCI_IOMAP
18 select GENERIC_SMP_IDLE_THREAD
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_TRACEHOOK
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_CONTIGUOUS if MMU
32 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36 select HAVE_GENERIC_DMA_COHERENT
37 select HAVE_GENERIC_HARDIRQS
38 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_KERNEL_GZIP
42 select HAVE_KERNEL_LZMA
43 select HAVE_KERNEL_LZO
45 select HAVE_KPROBES if !XIP_KERNEL
46 select HAVE_KRETPROBES if (HAVE_KPROBES)
48 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
49 select HAVE_PERF_EVENTS
50 select HAVE_REGS_AND_STACK_ACCESS_API
51 select HAVE_SYSCALL_TRACEPOINTS
54 select PERF_USE_VMALLOC
56 select SYS_SUPPORTS_APM_EMULATION
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select MODULES_USE_ELF_REL
60 The ARM series is a line of low-power-consumption RISC chip designs
61 licensed by ARM Ltd and targeted at embedded applications and
62 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
63 manufactured, but legacy ARM-based PC hardware remains popular in
64 Europe. There is an ARM Linux project with a web page at
65 <http://www.arm.linux.org.uk/>.
67 config ARM_HAS_SG_CHAIN
70 config NEED_SG_DMA_LENGTH
73 config ARM_DMA_USE_IOMMU
75 select ARM_HAS_SG_CHAIN
76 select NEED_SG_DMA_LENGTH
84 config SYS_SUPPORTS_APM_EMULATION
92 select GENERIC_ALLOCATOR
103 The Extended Industry Standard Architecture (EISA) bus was
104 developed as an open alternative to the IBM MicroChannel bus.
106 The EISA bus provided some of the features of the IBM MicroChannel
107 bus while maintaining backward compatibility with cards made for
108 the older ISA bus. The EISA bus saw limited use between 1988 and
109 1995 when it was made obsolete by the PCI bus.
111 Say Y here if you are building a kernel for an EISA-based machine.
118 config STACKTRACE_SUPPORT
122 config HAVE_LATENCYTOP_SUPPORT
127 config LOCKDEP_SUPPORT
131 config TRACE_IRQFLAGS_SUPPORT
135 config RWSEM_GENERIC_SPINLOCK
139 config RWSEM_XCHGADD_ALGORITHM
142 config ARCH_HAS_ILOG2_U32
145 config ARCH_HAS_ILOG2_U64
148 config ARCH_HAS_CPUFREQ
151 Internal node to signify that the ARCH has CPUFREQ support
152 and that the relevant menu configurations are displayed for
155 config GENERIC_HWEIGHT
159 config GENERIC_CALIBRATE_DELAY
163 config ARCH_MAY_HAVE_PC_FDC
169 config NEED_DMA_MAP_STATE
172 config ARCH_HAS_DMA_SET_COHERENT_MASK
175 config GENERIC_ISA_DMA
181 config NEED_RET_TO_USER
189 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
190 default DRAM_BASE if REMAP_VECTORS_TO_RAM
193 The base address of exception vectors.
195 config ARM_PATCH_PHYS_VIRT
196 bool "Patch physical to virtual translations at runtime" if EMBEDDED
198 depends on !XIP_KERNEL && MMU
199 depends on !ARCH_REALVIEW || !SPARSEMEM
201 Patch phys-to-virt and virt-to-phys translation functions at
202 boot and module load time according to the position of the
203 kernel in system memory.
205 This can only be used with non-XIP MMU kernels where the base
206 of physical memory is at a 16MB boundary.
208 Only disable this option if you know that you do not require
209 this feature (eg, building a kernel for a single machine) and
210 you need to shrink the kernel to the minimal size.
212 config NEED_MACH_GPIO_H
215 Select this when mach/gpio.h is required to provide special
216 definitions for this platform. The need for mach/gpio.h should
217 be avoided when possible.
219 config NEED_MACH_IO_H
222 Select this when mach/io.h is required to provide special
223 definitions for this platform. The need for mach/io.h should
224 be avoided when possible.
226 config NEED_MACH_MEMORY_H
229 Select this when mach/memory.h is required to provide special
230 definitions for this platform. The need for mach/memory.h should
231 be avoided when possible.
234 hex "Physical address of main memory" if MMU
235 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
236 default DRAM_BASE if !MMU
238 Please provide the physical address corresponding to the
239 location of main memory in your system.
245 source "init/Kconfig"
247 source "kernel/Kconfig.freezer"
252 bool "MMU-based Paged Memory Management Support"
255 Select if you want MMU-based virtualised addressing space
256 support by paged memory management. If unsure, say 'Y'.
259 # The "ARM system type" choice list is ordered alphabetically by option
260 # text. Please add new entries in the option alphabetic order.
263 prompt "ARM system type"
264 default ARCH_MULTIPLATFORM
266 config ARCH_MULTIPLATFORM
267 bool "Allow multiple platforms to be selected"
269 select ARM_PATCH_PHYS_VIRT
272 select MULTI_IRQ_HANDLER
276 config ARCH_INTEGRATOR
277 bool "ARM Ltd. Integrator family"
278 select ARCH_HAS_CPUFREQ
281 select COMMON_CLK_VERSATILE
282 select GENERIC_CLOCKEVENTS
285 select MULTI_IRQ_HANDLER
286 select NEED_MACH_MEMORY_H
287 select PLAT_VERSATILE
288 select PLAT_VERSATILE_FPGA_IRQ
291 Support for ARM's Integrator platform.
294 bool "ARM Ltd. RealView family"
295 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select ARM_TIMER_SP804
299 select COMMON_CLK_VERSATILE
300 select GENERIC_CLOCKEVENTS
301 select GPIO_PL061 if GPIOLIB
303 select NEED_MACH_MEMORY_H
304 select PLAT_VERSATILE
305 select PLAT_VERSATILE_CLCD
307 This enables support for ARM Ltd RealView boards.
309 config ARCH_VERSATILE
310 bool "ARM Ltd. Versatile family"
311 select ARCH_WANT_OPTIONAL_GPIOLIB
313 select ARM_TIMER_SP804
316 select GENERIC_CLOCKEVENTS
317 select HAVE_MACH_CLKDEV
319 select PLAT_VERSATILE
320 select PLAT_VERSATILE_CLCD
321 select PLAT_VERSATILE_CLOCK
322 select PLAT_VERSATILE_FPGA_IRQ
324 This enables support for ARM Ltd Versatile board.
328 select ARCH_REQUIRE_GPIOLIB
332 select NEED_MACH_GPIO_H
333 select NEED_MACH_IO_H if PCCARD
335 select PINCTRL_AT91 if USE_OF
337 This enables support for systems based on Atmel
338 AT91RM9200 and AT91SAM9* processors.
341 bool "Broadcom BCM2835 family"
342 select ARCH_WANT_OPTIONAL_GPIOLIB
344 select ARM_ERRATA_411920
345 select ARM_TIMER_SP804
349 select GENERIC_CLOCKEVENTS
350 select MULTI_IRQ_HANDLER
354 This enables support for the Broadcom BCM2835 SoC. This SoC is
355 use in the Raspberry Pi, and Roku 2 devices.
358 bool "Cavium Networks CNS3XXX family"
361 select GENERIC_CLOCKEVENTS
362 select MIGHT_HAVE_CACHE_L2X0
363 select MIGHT_HAVE_PCI
364 select PCI_DOMAINS if PCI
366 Support for Cavium Networks CNS3XXX platform.
369 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
370 select ARCH_REQUIRE_GPIOLIB
371 select ARCH_USES_GETTIMEOFFSET
375 select NEED_MACH_MEMORY_H
377 Support for Cirrus Logic 711x/721x/731x based boards.
380 bool "Cortina Systems Gemini"
381 select ARCH_REQUIRE_GPIOLIB
382 select ARCH_USES_GETTIMEOFFSET
385 Support for the Cortina Systems Gemini family SoCs
389 select ARCH_REQUIRE_GPIOLIB
391 select GENERIC_CLOCKEVENTS
392 select GENERIC_IRQ_CHIP
393 select MIGHT_HAVE_CACHE_L2X0
399 Support for CSR SiRFprimaII/Marco/Polo platforms
403 select ARCH_USES_GETTIMEOFFSET
406 select NEED_MACH_IO_H
407 select NEED_MACH_MEMORY_H
410 This is an evaluation board for the StrongARM processor available
411 from Digital. It has limited hardware on-board, including an
412 Ethernet interface, two PCMCIA sockets, two serial ports and a
417 select ARCH_HAS_HOLES_MEMORYMODEL
418 select ARCH_REQUIRE_GPIOLIB
419 select ARCH_USES_GETTIMEOFFSET
424 select NEED_MACH_MEMORY_H
426 This enables support for the Cirrus EP93xx series of CPUs.
428 config ARCH_FOOTBRIDGE
432 select GENERIC_CLOCKEVENTS
434 select NEED_MACH_IO_H if !MMU
435 select NEED_MACH_MEMORY_H
437 Support for systems based on the DC21285 companion chip
438 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
441 bool "Freescale MXC/iMX-based"
442 select ARCH_REQUIRE_GPIOLIB
445 select GENERIC_CLOCKEVENTS
446 select GENERIC_IRQ_CHIP
447 select MULTI_IRQ_HANDLER
451 Support for Freescale MXC/iMX-based family of processors
454 bool "Freescale MXS-based"
455 select ARCH_REQUIRE_GPIOLIB
459 select GENERIC_CLOCKEVENTS
460 select HAVE_CLK_PREPARE
461 select MULTI_IRQ_HANDLER
466 Support for Freescale MXS-based family of processors
469 bool "Hilscher NetX based"
473 select GENERIC_CLOCKEVENTS
475 This enables support for systems based on the Hilscher NetX Soc
478 bool "Hynix HMS720x-based"
479 select ARCH_USES_GETTIMEOFFSET
483 This enables support for systems based on the Hynix HMS720x
488 select ARCH_SUPPORTS_MSI
490 select NEED_MACH_MEMORY_H
491 select NEED_RET_TO_USER
496 Support for Intel's IOP13XX (XScale) family of processors.
501 select ARCH_REQUIRE_GPIOLIB
503 select NEED_MACH_GPIO_H
504 select NEED_RET_TO_USER
508 Support for Intel's 80219 and IOP32X (XScale) family of
514 select ARCH_REQUIRE_GPIOLIB
516 select NEED_MACH_GPIO_H
517 select NEED_RET_TO_USER
521 Support for Intel's IOP33X (XScale) family of processors.
526 select ARCH_HAS_DMA_SET_COHERENT_MASK
527 select ARCH_REQUIRE_GPIOLIB
530 select DMABOUNCE if PCI
531 select GENERIC_CLOCKEVENTS
532 select MIGHT_HAVE_PCI
533 select NEED_MACH_IO_H
535 Support for Intel's IXP4XX (XScale) family of processors.
539 select ARCH_REQUIRE_GPIOLIB
541 select GENERIC_CLOCKEVENTS
542 select MIGHT_HAVE_PCI
543 select PLAT_ORION_LEGACY
544 select USB_ARCH_HAS_EHCI
546 Support for the Marvell Dove SoC 88AP510
549 bool "Marvell Kirkwood"
550 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_CLOCKEVENTS
554 select PLAT_ORION_LEGACY
556 Support for the following Marvell Kirkwood series SoCs:
557 88F6180, 88F6192 and 88F6281.
560 bool "Marvell MV78xx0"
561 select ARCH_REQUIRE_GPIOLIB
563 select GENERIC_CLOCKEVENTS
565 select PLAT_ORION_LEGACY
567 Support for the following Marvell MV78xx0 series SoCs:
573 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_CLOCKEVENTS
577 select PLAT_ORION_LEGACY
579 Support for the following Marvell Orion 5x series SoCs:
580 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
581 Orion-2 (5281), Orion-1-90 (6183).
584 bool "Marvell PXA168/910/MMP2"
586 select ARCH_REQUIRE_GPIOLIB
588 select GENERIC_ALLOCATOR
589 select GENERIC_CLOCKEVENTS
592 select NEED_MACH_GPIO_H
596 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
599 bool "Micrel/Kendin KS8695"
600 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
604 select NEED_MACH_MEMORY_H
606 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
607 System-on-Chip devices.
610 bool "Nuvoton W90X900 CPU"
611 select ARCH_REQUIRE_GPIOLIB
615 select GENERIC_CLOCKEVENTS
617 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
618 At present, the w90x900 has been renamed nuc900, regarding
619 the ARM series product line, you can login the following
620 link address to know more.
622 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
623 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
627 select ARCH_REQUIRE_GPIOLIB
632 select GENERIC_CLOCKEVENTS
635 select USB_ARCH_HAS_OHCI
638 Support for the NXP LPC32XX family of processors
642 select ARCH_HAS_CPUFREQ
646 select GENERIC_CLOCKEVENTS
650 select MIGHT_HAVE_CACHE_L2X0
653 This enables support for NVIDIA Tegra based systems (Tegra APX,
654 Tegra 6xx and Tegra 2 series).
657 bool "PXA2xx/PXA3xx-based"
659 select ARCH_HAS_CPUFREQ
661 select ARCH_REQUIRE_GPIOLIB
662 select ARM_CPU_SUSPEND if PM
666 select GENERIC_CLOCKEVENTS
669 select MULTI_IRQ_HANDLER
670 select NEED_MACH_GPIO_H
674 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
678 select ARCH_REQUIRE_GPIOLIB
680 select GENERIC_CLOCKEVENTS
683 Support for Qualcomm MSM/QSD based systems. This runs on the
684 apps processor of the MSM/QSD and depends on a shared memory
685 interface to the modem processor which runs the baseband
686 stack and controls some vital subsystems
687 (clock and power control, etc).
690 bool "Renesas SH-Mobile / R-Mobile"
692 select GENERIC_CLOCKEVENTS
694 select HAVE_MACH_CLKDEV
696 select MIGHT_HAVE_CACHE_L2X0
697 select MULTI_IRQ_HANDLER
698 select NEED_MACH_MEMORY_H
700 select PM_GENERIC_DOMAINS if PM
703 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
708 select ARCH_MAY_HAVE_PC_FDC
709 select ARCH_SPARSEMEM_ENABLE
710 select ARCH_USES_GETTIMEOFFSET
713 select HAVE_PATA_PLATFORM
715 select NEED_MACH_IO_H
716 select NEED_MACH_MEMORY_H
719 On the Acorn Risc-PC, Linux can support the internal IDE disk and
720 CD-ROM interface, serial and parallel port, and the floppy drive.
724 select ARCH_HAS_CPUFREQ
726 select ARCH_REQUIRE_GPIOLIB
727 select ARCH_SPARSEMEM_ENABLE
732 select GENERIC_CLOCKEVENTS
735 select NEED_MACH_GPIO_H
736 select NEED_MACH_MEMORY_H
739 Support for StrongARM 11x0 based boards.
742 bool "Samsung S3C24XX SoCs"
743 select ARCH_HAS_CPUFREQ
744 select ARCH_USES_GETTIMEOFFSET
748 select HAVE_S3C2410_I2C if I2C
749 select HAVE_S3C2410_WATCHDOG if WATCHDOG
750 select HAVE_S3C_RTC if RTC_CLASS
751 select NEED_MACH_GPIO_H
752 select NEED_MACH_IO_H
754 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
755 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
756 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
757 Samsung SMDK2410 development board (and derivatives).
760 bool "Samsung S3C64XX"
761 select ARCH_HAS_CPUFREQ
762 select ARCH_REQUIRE_GPIOLIB
763 select ARCH_USES_GETTIMEOFFSET
768 select HAVE_S3C2410_I2C if I2C
769 select HAVE_S3C2410_WATCHDOG if WATCHDOG
771 select NEED_MACH_GPIO_H
775 select S3C_GPIO_TRACK
776 select SAMSUNG_CLKSRC
777 select SAMSUNG_GPIOLIB_4BIT
778 select SAMSUNG_IRQ_VIC_TIMER
779 select USB_ARCH_HAS_OHCI
781 Samsung S3C64XX series based systems
784 bool "Samsung S5P6440 S5P6450"
788 select GENERIC_CLOCKEVENTS
791 select HAVE_S3C2410_I2C if I2C
792 select HAVE_S3C2410_WATCHDOG if WATCHDOG
793 select HAVE_S3C_RTC if RTC_CLASS
794 select NEED_MACH_GPIO_H
796 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
800 bool "Samsung S5PC100"
801 select ARCH_USES_GETTIMEOFFSET
806 select HAVE_S3C2410_I2C if I2C
807 select HAVE_S3C2410_WATCHDOG if WATCHDOG
808 select HAVE_S3C_RTC if RTC_CLASS
809 select NEED_MACH_GPIO_H
811 Samsung S5PC100 series based systems
814 bool "Samsung S5PV210/S5PC110"
815 select ARCH_HAS_CPUFREQ
816 select ARCH_HAS_HOLES_MEMORYMODEL
817 select ARCH_SPARSEMEM_ENABLE
821 select GENERIC_CLOCKEVENTS
824 select HAVE_S3C2410_I2C if I2C
825 select HAVE_S3C2410_WATCHDOG if WATCHDOG
826 select HAVE_S3C_RTC if RTC_CLASS
827 select NEED_MACH_GPIO_H
828 select NEED_MACH_MEMORY_H
830 Samsung S5PV210/S5PC110 series based systems
833 bool "Samsung EXYNOS"
834 select ARCH_HAS_CPUFREQ
835 select ARCH_HAS_HOLES_MEMORYMODEL
836 select ARCH_SPARSEMEM_ENABLE
839 select GENERIC_CLOCKEVENTS
842 select HAVE_S3C2410_I2C if I2C
843 select HAVE_S3C2410_WATCHDOG if WATCHDOG
844 select HAVE_S3C_RTC if RTC_CLASS
845 select NEED_MACH_GPIO_H
846 select NEED_MACH_MEMORY_H
848 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
852 select ARCH_USES_GETTIMEOFFSET
856 select NEED_MACH_MEMORY_H
860 Support for the StrongARM based Digital DNARD machine, also known
861 as "Shark" (<http://www.shark-linux.de/shark.html>).
864 bool "ST-Ericsson U300 Series"
866 select ARCH_REQUIRE_GPIOLIB
868 select ARM_PATCH_PHYS_VIRT
874 select GENERIC_CLOCKEVENTS
879 Support for ST-Ericsson U300 series mobile platforms.
882 bool "ST-Ericsson U8500 Series"
884 select ARCH_HAS_CPUFREQ
885 select ARCH_REQUIRE_GPIOLIB
889 select GENERIC_CLOCKEVENTS
891 select MIGHT_HAVE_CACHE_L2X0
893 Support for ST-Ericsson's Ux500 architecture
896 bool "STMicroelectronics Nomadik"
897 select ARCH_REQUIRE_GPIOLIB
902 select GENERIC_CLOCKEVENTS
903 select MIGHT_HAVE_CACHE_L2X0
905 select PINCTRL_STN8815
907 Support for the Nomadik platform by ST-Ericsson
911 select ARCH_REQUIRE_GPIOLIB
916 select GENERIC_CLOCKEVENTS
919 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
923 select ARCH_HAS_HOLES_MEMORYMODEL
924 select ARCH_REQUIRE_GPIOLIB
926 select GENERIC_ALLOCATOR
927 select GENERIC_CLOCKEVENTS
928 select GENERIC_IRQ_CHIP
930 select NEED_MACH_GPIO_H
933 Support for TI's DaVinci platform.
938 select ARCH_HAS_CPUFREQ
939 select ARCH_HAS_HOLES_MEMORYMODEL
940 select ARCH_REQUIRE_GPIOLIB
942 select GENERIC_CLOCKEVENTS
944 select NEED_MACH_GPIO_H
946 Support for TI's OMAP platform (OMAP1/2/3/4).
949 bool "VIA/WonderMedia 85xx"
950 select ARCH_HAS_CPUFREQ
951 select ARCH_REQUIRE_GPIOLIB
955 select GENERIC_CLOCKEVENTS
960 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
963 bool "Xilinx Zynq ARM Cortex A9 Platform"
967 select GENERIC_CLOCKEVENTS
969 select MIGHT_HAVE_CACHE_L2X0
972 Support for Xilinx Zynq ARM Cortex A9 Platform
975 menu "Multiple platform selection"
976 depends on ARCH_MULTIPLATFORM
978 comment "CPU Core family selection"
981 bool "ARMv4 based platforms (FA526, StrongARM)"
982 depends on !ARCH_MULTI_V6_V7
983 select ARCH_MULTI_V4_V5
985 config ARCH_MULTI_V4T
986 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
987 depends on !ARCH_MULTI_V6_V7
988 select ARCH_MULTI_V4_V5
991 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
992 depends on !ARCH_MULTI_V6_V7
993 select ARCH_MULTI_V4_V5
995 config ARCH_MULTI_V4_V5
999 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
1000 select ARCH_MULTI_V6_V7
1003 config ARCH_MULTI_V7
1004 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1006 select ARCH_MULTI_V6_V7
1007 select ARCH_VEXPRESS
1010 config ARCH_MULTI_V6_V7
1013 config ARCH_MULTI_CPU_AUTO
1014 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1015 select ARCH_MULTI_V5
1020 # This is sorted alphabetically by mach-* pathname. However, plat-*
1021 # Kconfigs may be included either alphabetically (according to the
1022 # plat- suffix) or along side the corresponding mach-* source.
1024 source "arch/arm/mach-mvebu/Kconfig"
1026 source "arch/arm/mach-at91/Kconfig"
1028 source "arch/arm/mach-clps711x/Kconfig"
1030 source "arch/arm/mach-cns3xxx/Kconfig"
1032 source "arch/arm/mach-davinci/Kconfig"
1034 source "arch/arm/mach-dove/Kconfig"
1036 source "arch/arm/mach-ep93xx/Kconfig"
1038 source "arch/arm/mach-footbridge/Kconfig"
1040 source "arch/arm/mach-gemini/Kconfig"
1042 source "arch/arm/mach-h720x/Kconfig"
1044 source "arch/arm/mach-highbank/Kconfig"
1046 source "arch/arm/mach-integrator/Kconfig"
1048 source "arch/arm/mach-iop32x/Kconfig"
1050 source "arch/arm/mach-iop33x/Kconfig"
1052 source "arch/arm/mach-iop13xx/Kconfig"
1054 source "arch/arm/mach-ixp4xx/Kconfig"
1056 source "arch/arm/mach-kirkwood/Kconfig"
1058 source "arch/arm/mach-ks8695/Kconfig"
1060 source "arch/arm/mach-msm/Kconfig"
1062 source "arch/arm/mach-mv78xx0/Kconfig"
1064 source "arch/arm/plat-mxc/Kconfig"
1066 source "arch/arm/mach-mxs/Kconfig"
1068 source "arch/arm/mach-netx/Kconfig"
1070 source "arch/arm/mach-nomadik/Kconfig"
1071 source "arch/arm/plat-nomadik/Kconfig"
1073 source "arch/arm/plat-omap/Kconfig"
1075 source "arch/arm/mach-omap1/Kconfig"
1077 source "arch/arm/mach-omap2/Kconfig"
1079 source "arch/arm/mach-orion5x/Kconfig"
1081 source "arch/arm/mach-picoxcell/Kconfig"
1083 source "arch/arm/mach-pxa/Kconfig"
1084 source "arch/arm/plat-pxa/Kconfig"
1086 source "arch/arm/mach-mmp/Kconfig"
1088 source "arch/arm/mach-realview/Kconfig"
1090 source "arch/arm/mach-sa1100/Kconfig"
1092 source "arch/arm/plat-samsung/Kconfig"
1093 source "arch/arm/plat-s3c24xx/Kconfig"
1095 source "arch/arm/mach-socfpga/Kconfig"
1097 source "arch/arm/plat-spear/Kconfig"
1099 source "arch/arm/mach-s3c24xx/Kconfig"
1101 source "arch/arm/mach-s3c2412/Kconfig"
1102 source "arch/arm/mach-s3c2440/Kconfig"
1106 source "arch/arm/mach-s3c64xx/Kconfig"
1109 source "arch/arm/mach-s5p64x0/Kconfig"
1111 source "arch/arm/mach-s5pc100/Kconfig"
1113 source "arch/arm/mach-s5pv210/Kconfig"
1115 source "arch/arm/mach-exynos/Kconfig"
1117 source "arch/arm/mach-shmobile/Kconfig"
1119 source "arch/arm/mach-prima2/Kconfig"
1121 source "arch/arm/mach-tegra/Kconfig"
1123 source "arch/arm/mach-u300/Kconfig"
1125 source "arch/arm/mach-ux500/Kconfig"
1127 source "arch/arm/mach-versatile/Kconfig"
1129 source "arch/arm/mach-vexpress/Kconfig"
1130 source "arch/arm/plat-versatile/Kconfig"
1132 source "arch/arm/mach-w90x900/Kconfig"
1134 # Definitions to make life easier
1140 select GENERIC_CLOCKEVENTS
1146 select GENERIC_IRQ_CHIP
1149 config PLAT_ORION_LEGACY
1156 config PLAT_VERSATILE
1159 config ARM_TIMER_SP804
1162 select HAVE_SCHED_CLOCK
1164 source arch/arm/mm/Kconfig
1168 default 16 if ARCH_EP93XX
1172 bool "Enable iWMMXt support"
1173 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1174 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1176 Enable support for iWMMXt context switching at run time if
1177 running on a CPU that supports it.
1181 depends on CPU_XSCALE
1184 config MULTI_IRQ_HANDLER
1187 Allow each machine to specify it's own IRQ handler at run time.
1190 source "arch/arm/Kconfig-nommu"
1193 config ARM_ERRATA_326103
1194 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1197 Executing a SWP instruction to read-only memory does not set bit 11
1198 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1199 treat the access as a read, preventing a COW from occurring and
1200 causing the faulting task to livelock.
1202 config ARM_ERRATA_411920
1203 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1204 depends on CPU_V6 || CPU_V6K
1206 Invalidation of the Instruction Cache operation can
1207 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1208 It does not affect the MPCore. This option enables the ARM Ltd.
1209 recommended workaround.
1211 config ARM_ERRATA_430973
1212 bool "ARM errata: Stale prediction on replaced interworking branch"
1215 This option enables the workaround for the 430973 Cortex-A8
1216 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1217 interworking branch is replaced with another code sequence at the
1218 same virtual address, whether due to self-modifying code or virtual
1219 to physical address re-mapping, Cortex-A8 does not recover from the
1220 stale interworking branch prediction. This results in Cortex-A8
1221 executing the new code sequence in the incorrect ARM or Thumb state.
1222 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1223 and also flushes the branch target cache at every context switch.
1224 Note that setting specific bits in the ACTLR register may not be
1225 available in non-secure mode.
1227 config ARM_ERRATA_458693
1228 bool "ARM errata: Processor deadlock when a false hazard is created"
1231 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1232 erratum. For very specific sequences of memory operations, it is
1233 possible for a hazard condition intended for a cache line to instead
1234 be incorrectly associated with a different cache line. This false
1235 hazard might then cause a processor deadlock. The workaround enables
1236 the L1 caching of the NEON accesses and disables the PLD instruction
1237 in the ACTLR register. Note that setting specific bits in the ACTLR
1238 register may not be available in non-secure mode.
1240 config ARM_ERRATA_460075
1241 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1244 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1245 erratum. Any asynchronous access to the L2 cache may encounter a
1246 situation in which recent store transactions to the L2 cache are lost
1247 and overwritten with stale memory contents from external memory. The
1248 workaround disables the write-allocate mode for the L2 cache via the
1249 ACTLR register. Note that setting specific bits in the ACTLR register
1250 may not be available in non-secure mode.
1252 config ARM_ERRATA_742230
1253 bool "ARM errata: DMB operation may be faulty"
1254 depends on CPU_V7 && SMP
1256 This option enables the workaround for the 742230 Cortex-A9
1257 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1258 between two write operations may not ensure the correct visibility
1259 ordering of the two writes. This workaround sets a specific bit in
1260 the diagnostic register of the Cortex-A9 which causes the DMB
1261 instruction to behave as a DSB, ensuring the correct behaviour of
1264 config ARM_ERRATA_742231
1265 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1266 depends on CPU_V7 && SMP
1268 This option enables the workaround for the 742231 Cortex-A9
1269 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1270 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1271 accessing some data located in the same cache line, may get corrupted
1272 data due to bad handling of the address hazard when the line gets
1273 replaced from one of the CPUs at the same time as another CPU is
1274 accessing it. This workaround sets specific bits in the diagnostic
1275 register of the Cortex-A9 which reduces the linefill issuing
1276 capabilities of the processor.
1278 config PL310_ERRATA_588369
1279 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1280 depends on CACHE_L2X0
1282 The PL310 L2 cache controller implements three types of Clean &
1283 Invalidate maintenance operations: by Physical Address
1284 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1285 They are architecturally defined to behave as the execution of a
1286 clean operation followed immediately by an invalidate operation,
1287 both performing to the same memory location. This functionality
1288 is not correctly implemented in PL310 as clean lines are not
1289 invalidated as a result of these operations.
1291 config ARM_ERRATA_720789
1292 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1295 This option enables the workaround for the 720789 Cortex-A9 (prior to
1296 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1297 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1298 As a consequence of this erratum, some TLB entries which should be
1299 invalidated are not, resulting in an incoherency in the system page
1300 tables. The workaround changes the TLB flushing routines to invalidate
1301 entries regardless of the ASID.
1303 config PL310_ERRATA_727915
1304 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1305 depends on CACHE_L2X0
1307 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1308 operation (offset 0x7FC). This operation runs in background so that
1309 PL310 can handle normal accesses while it is in progress. Under very
1310 rare circumstances, due to this erratum, write data can be lost when
1311 PL310 treats a cacheable write transaction during a Clean &
1312 Invalidate by Way operation.
1314 config ARM_ERRATA_743622
1315 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1318 This option enables the workaround for the 743622 Cortex-A9
1319 (r2p*) erratum. Under very rare conditions, a faulty
1320 optimisation in the Cortex-A9 Store Buffer may lead to data
1321 corruption. This workaround sets a specific bit in the diagnostic
1322 register of the Cortex-A9 which disables the Store Buffer
1323 optimisation, preventing the defect from occurring. This has no
1324 visible impact on the overall performance or power consumption of the
1327 config ARM_ERRATA_751472
1328 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1331 This option enables the workaround for the 751472 Cortex-A9 (prior
1332 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1333 completion of a following broadcasted operation if the second
1334 operation is received by a CPU before the ICIALLUIS has completed,
1335 potentially leading to corrupted entries in the cache or TLB.
1337 config PL310_ERRATA_753970
1338 bool "PL310 errata: cache sync operation may be faulty"
1339 depends on CACHE_PL310
1341 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1343 Under some condition the effect of cache sync operation on
1344 the store buffer still remains when the operation completes.
1345 This means that the store buffer is always asked to drain and
1346 this prevents it from merging any further writes. The workaround
1347 is to replace the normal offset of cache sync operation (0x730)
1348 by another offset targeting an unmapped PL310 register 0x740.
1349 This has the same effect as the cache sync operation: store buffer
1350 drain and waiting for all buffers empty.
1352 config ARM_ERRATA_754322
1353 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1356 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1357 r3p*) erratum. A speculative memory access may cause a page table walk
1358 which starts prior to an ASID switch but completes afterwards. This
1359 can populate the micro-TLB with a stale entry which may be hit with
1360 the new ASID. This workaround places two dsb instructions in the mm
1361 switching code so that no page table walks can cross the ASID switch.
1363 config ARM_ERRATA_754327
1364 bool "ARM errata: no automatic Store Buffer drain"
1365 depends on CPU_V7 && SMP
1367 This option enables the workaround for the 754327 Cortex-A9 (prior to
1368 r2p0) erratum. The Store Buffer does not have any automatic draining
1369 mechanism and therefore a livelock may occur if an external agent
1370 continuously polls a memory location waiting to observe an update.
1371 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1372 written polling loops from denying visibility of updates to memory.
1374 config ARM_ERRATA_364296
1375 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1376 depends on CPU_V6 && !SMP
1378 This options enables the workaround for the 364296 ARM1136
1379 r0p2 erratum (possible cache data corruption with
1380 hit-under-miss enabled). It sets the undocumented bit 31 in
1381 the auxiliary control register and the FI bit in the control
1382 register, thus disabling hit-under-miss without putting the
1383 processor into full low interrupt latency mode. ARM11MPCore
1386 config ARM_ERRATA_764369
1387 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1388 depends on CPU_V7 && SMP
1390 This option enables the workaround for erratum 764369
1391 affecting Cortex-A9 MPCore with two or more processors (all
1392 current revisions). Under certain timing circumstances, a data
1393 cache line maintenance operation by MVA targeting an Inner
1394 Shareable memory region may fail to proceed up to either the
1395 Point of Coherency or to the Point of Unification of the
1396 system. This workaround adds a DSB instruction before the
1397 relevant cache maintenance functions and sets a specific bit
1398 in the diagnostic control register of the SCU.
1400 config PL310_ERRATA_769419
1401 bool "PL310 errata: no automatic Store Buffer drain"
1402 depends on CACHE_L2X0
1404 On revisions of the PL310 prior to r3p2, the Store Buffer does
1405 not automatically drain. This can cause normal, non-cacheable
1406 writes to be retained when the memory system is idle, leading
1407 to suboptimal I/O performance for drivers using coherent DMA.
1408 This option adds a write barrier to the cpu_idle loop so that,
1409 on systems with an outer cache, the store buffer is drained
1412 config ARM_ERRATA_775420
1413 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1416 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1417 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1418 operation aborts with MMU exception, it might cause the processor
1419 to deadlock. This workaround puts DSB before executing ISB if
1420 an abort may occur on cache maintenance.
1424 source "arch/arm/common/Kconfig"
1434 Find out whether you have ISA slots on your motherboard. ISA is the
1435 name of a bus system, i.e. the way the CPU talks to the other stuff
1436 inside your box. Other bus systems are PCI, EISA, MicroChannel
1437 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1438 newer boards don't support it. If you have ISA, say Y, otherwise N.
1440 # Select ISA DMA controller support
1445 # Select ISA DMA interface
1450 bool "PCI support" if MIGHT_HAVE_PCI
1452 Find out whether you have a PCI motherboard. PCI is the name of a
1453 bus system, i.e. the way the CPU talks to the other stuff inside
1454 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1455 VESA. If you have PCI, say Y, otherwise N.
1461 config PCI_NANOENGINE
1462 bool "BSE nanoEngine PCI support"
1463 depends on SA1100_NANOENGINE
1465 Enable PCI on the BSE nanoEngine board.
1470 # Select the host bridge type
1471 config PCI_HOST_VIA82C505
1473 depends on PCI && ARCH_SHARK
1476 config PCI_HOST_ITE8152
1478 depends on PCI && MACH_ARMCORE
1482 source "drivers/pci/Kconfig"
1484 source "drivers/pcmcia/Kconfig"
1488 menu "Kernel Features"
1493 This option should be selected by machines which have an SMP-
1496 The only effect of this option is to make the SMP-related
1497 options available to the user for configuration.
1500 bool "Symmetric Multi-Processing"
1501 depends on CPU_V6K || CPU_V7
1502 depends on GENERIC_CLOCKEVENTS
1505 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1506 select USE_GENERIC_SMP_HELPERS
1508 This enables support for systems with more than one CPU. If you have
1509 a system with only one CPU, like most personal computers, say N. If
1510 you have a system with more than one CPU, say Y.
1512 If you say N here, the kernel will run on single and multiprocessor
1513 machines, but will use only one CPU of a multiprocessor machine. If
1514 you say Y here, the kernel will run on many, but not all, single
1515 processor machines. On a single processor machine, the kernel will
1516 run faster if you say N here.
1518 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1519 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1520 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1522 If you don't know what to do here, say N.
1525 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1526 depends on EXPERIMENTAL
1527 depends on SMP && !XIP_KERNEL
1530 SMP kernels contain instructions which fail on non-SMP processors.
1531 Enabling this option allows the kernel to modify itself to make
1532 these instructions safe. Disabling it allows about 1K of space
1535 If you don't know what to do here, say Y.
1537 config ARM_CPU_TOPOLOGY
1538 bool "Support cpu topology definition"
1539 depends on SMP && CPU_V7
1542 Support ARM cpu topology definition. The MPIDR register defines
1543 affinity between processors which is then used to describe the cpu
1544 topology of an ARM System.
1547 bool "Multi-core scheduler support"
1548 depends on ARM_CPU_TOPOLOGY
1550 Multi-core scheduler support improves the CPU scheduler's decision
1551 making when dealing with multi-core CPU chips at a cost of slightly
1552 increased overhead in some places. If unsure say N here.
1555 bool "SMT scheduler support"
1556 depends on ARM_CPU_TOPOLOGY
1558 Improves the CPU scheduler's decision making when dealing with
1559 MultiThreading at a cost of slightly increased overhead in some
1560 places. If unsure say N here.
1565 This option enables support for the ARM system coherency unit
1567 config ARM_ARCH_TIMER
1568 bool "Architected timer support"
1571 This option enables support for the ARM architected timer
1577 This options enables support for the ARM timer and watchdog unit
1580 prompt "Memory split"
1583 Select the desired split between kernel and user memory.
1585 If you are not absolutely sure what you are doing, leave this
1589 bool "3G/1G user/kernel split"
1591 bool "2G/2G user/kernel split"
1593 bool "1G/3G user/kernel split"
1598 default 0x40000000 if VMSPLIT_1G
1599 default 0x80000000 if VMSPLIT_2G
1603 int "Maximum number of CPUs (2-32)"
1609 bool "Support for hot-pluggable CPUs"
1610 depends on SMP && HOTPLUG
1612 Say Y here to experiment with turning CPUs off and on. CPUs
1613 can be controlled through /sys/devices/system/cpu.
1616 bool "Use local timer interrupts"
1619 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1621 Enable support for local timers on SMP platforms, rather then the
1622 legacy IPI broadcast method. Local timers allows the system
1623 accounting to be spread across the timer interval, preventing a
1624 "thundering herd" at every timer tick.
1628 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1629 default 355 if ARCH_U8500
1630 default 264 if MACH_H4700
1631 default 512 if SOC_OMAP5
1632 default 288 if ARCH_VT8500
1635 Maximum number of GPIOs in the system.
1637 If unsure, leave the default value.
1639 source kernel/Kconfig.preempt
1643 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1644 ARCH_S5PV210 || ARCH_EXYNOS4
1645 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1646 default AT91_TIMER_HZ if ARCH_AT91
1647 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1650 config THUMB2_KERNEL
1651 bool "Compile the kernel in Thumb-2 mode"
1652 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1654 select ARM_ASM_UNIFIED
1657 By enabling this option, the kernel will be compiled in
1658 Thumb-2 mode. A compiler/assembler that understand the unified
1659 ARM-Thumb syntax is needed.
1663 config THUMB2_AVOID_R_ARM_THM_JUMP11
1664 bool "Work around buggy Thumb-2 short branch relocations in gas"
1665 depends on THUMB2_KERNEL && MODULES
1668 Various binutils versions can resolve Thumb-2 branches to
1669 locally-defined, preemptible global symbols as short-range "b.n"
1670 branch instructions.
1672 This is a problem, because there's no guarantee the final
1673 destination of the symbol, or any candidate locations for a
1674 trampoline, are within range of the branch. For this reason, the
1675 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1676 relocation in modules at all, and it makes little sense to add
1679 The symptom is that the kernel fails with an "unsupported
1680 relocation" error when loading some modules.
1682 Until fixed tools are available, passing
1683 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1684 code which hits this problem, at the cost of a bit of extra runtime
1685 stack usage in some cases.
1687 The problem is described in more detail at:
1688 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1690 Only Thumb-2 kernels are affected.
1692 Unless you are sure your tools don't have this problem, say Y.
1694 config ARM_ASM_UNIFIED
1698 bool "Use the ARM EABI to compile the kernel"
1700 This option allows for the kernel to be compiled using the latest
1701 ARM ABI (aka EABI). This is only useful if you are using a user
1702 space environment that is also compiled with EABI.
1704 Since there are major incompatibilities between the legacy ABI and
1705 EABI, especially with regard to structure member alignment, this
1706 option also changes the kernel syscall calling convention to
1707 disambiguate both ABIs and allow for backward compatibility support
1708 (selected with CONFIG_OABI_COMPAT).
1710 To use this you need GCC version 4.0.0 or later.
1713 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1714 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1717 This option preserves the old syscall interface along with the
1718 new (ARM EABI) one. It also provides a compatibility layer to
1719 intercept syscalls that have structure arguments which layout
1720 in memory differs between the legacy ABI and the new ARM EABI
1721 (only for non "thumb" binaries). This option adds a tiny
1722 overhead to all syscalls and produces a slightly larger kernel.
1723 If you know you'll be using only pure EABI user space then you
1724 can say N here. If this option is not selected and you attempt
1725 to execute a legacy ABI binary then the result will be
1726 UNPREDICTABLE (in fact it can be predicted that it won't work
1727 at all). If in doubt say Y.
1729 config ARCH_HAS_HOLES_MEMORYMODEL
1732 config ARCH_SPARSEMEM_ENABLE
1735 config ARCH_SPARSEMEM_DEFAULT
1736 def_bool ARCH_SPARSEMEM_ENABLE
1738 config ARCH_SELECT_MEMORY_MODEL
1739 def_bool ARCH_SPARSEMEM_ENABLE
1741 config HAVE_ARCH_PFN_VALID
1742 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1745 bool "High Memory Support"
1748 The address space of ARM processors is only 4 Gigabytes large
1749 and it has to accommodate user address space, kernel address
1750 space as well as some memory mapped IO. That means that, if you
1751 have a large amount of physical memory and/or IO, not all of the
1752 memory can be "permanently mapped" by the kernel. The physical
1753 memory that is not permanently mapped is called "high memory".
1755 Depending on the selected kernel/user memory split, minimum
1756 vmalloc space and actual amount of RAM, you may not need this
1757 option which should result in a slightly faster kernel.
1762 bool "Allocate 2nd-level pagetables from highmem"
1765 config HW_PERF_EVENTS
1766 bool "Enable hardware performance counter support for perf events"
1767 depends on PERF_EVENTS
1770 Enable hardware performance counter support for perf events. If
1771 disabled, perf events will use software events only.
1775 config FORCE_MAX_ZONEORDER
1776 int "Maximum zone order" if ARCH_SHMOBILE
1777 range 11 64 if ARCH_SHMOBILE
1778 default "12" if SOC_AM33XX
1779 default "9" if SA1111
1782 The kernel memory allocator divides physically contiguous memory
1783 blocks into "zones", where each zone is a power of two number of
1784 pages. This option selects the largest power of two that the kernel
1785 keeps in the memory allocator. If you need to allocate very large
1786 blocks of physically contiguous memory, then you may need to
1787 increase this value.
1789 This config option is actually maximum order plus one. For example,
1790 a value of 11 means that the largest free memory block is 2^10 pages.
1792 config ALIGNMENT_TRAP
1794 depends on CPU_CP15_MMU
1795 default y if !ARCH_EBSA110
1796 select HAVE_PROC_CPU if PROC_FS
1798 ARM processors cannot fetch/store information which is not
1799 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1800 address divisible by 4. On 32-bit ARM processors, these non-aligned
1801 fetch/store instructions will be emulated in software if you say
1802 here, which has a severe performance impact. This is necessary for
1803 correct operation of some network protocols. With an IP-only
1804 configuration it is safe to say N, otherwise say Y.
1806 config UACCESS_WITH_MEMCPY
1807 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1809 default y if CPU_FEROCEON
1811 Implement faster copy_to_user and clear_user methods for CPU
1812 cores where a 8-word STM instruction give significantly higher
1813 memory write throughput than a sequence of individual 32bit stores.
1815 A possible side effect is a slight increase in scheduling latency
1816 between threads sharing the same address space if they invoke
1817 such copy operations with large buffers.
1819 However, if the CPU data cache is using a write-allocate mode,
1820 this option is unlikely to provide any performance gain.
1824 prompt "Enable seccomp to safely compute untrusted bytecode"
1826 This kernel feature is useful for number crunching applications
1827 that may need to compute untrusted bytecode during their
1828 execution. By using pipes or other transports made available to
1829 the process as file descriptors supporting the read/write
1830 syscalls, it's possible to isolate those applications in
1831 their own address space using seccomp. Once seccomp is
1832 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1833 and the task is only allowed to execute a few safe syscalls
1834 defined by each seccomp mode.
1836 config CC_STACKPROTECTOR
1837 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1838 depends on EXPERIMENTAL
1840 This option turns on the -fstack-protector GCC feature. This
1841 feature puts, at the beginning of functions, a canary value on
1842 the stack just before the return address, and validates
1843 the value just before actually returning. Stack based buffer
1844 overflows (that need to overwrite this return address) now also
1845 overwrite the canary, which gets detected and the attack is then
1846 neutralized via a kernel panic.
1847 This feature requires gcc version 4.2 or above.
1854 bool "Xen guest support on ARM (EXPERIMENTAL)"
1855 depends on EXPERIMENTAL && ARM && OF
1856 depends on CPU_V7 && !CPU_V6
1858 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1865 bool "Flattened Device Tree support"
1868 select OF_EARLY_FLATTREE
1870 Include support for flattened device tree machine descriptions.
1873 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1876 This is the traditional way of passing data to the kernel at boot
1877 time. If you are solely relying on the flattened device tree (or
1878 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1879 to remove ATAGS support from your kernel binary. If unsure,
1882 config DEPRECATED_PARAM_STRUCT
1883 bool "Provide old way to pass kernel parameters"
1886 This was deprecated in 2001 and announced to live on for 5 years.
1887 Some old boot loaders still use this way.
1889 # Compressed boot loader in ROM. Yes, we really want to ask about
1890 # TEXT and BSS so we preserve their values in the config files.
1891 config ZBOOT_ROM_TEXT
1892 hex "Compressed ROM boot loader base address"
1895 The physical address at which the ROM-able zImage is to be
1896 placed in the target. Platforms which normally make use of
1897 ROM-able zImage formats normally set this to a suitable
1898 value in their defconfig file.
1900 If ZBOOT_ROM is not enabled, this has no effect.
1902 config ZBOOT_ROM_BSS
1903 hex "Compressed ROM boot loader BSS address"
1906 The base address of an area of read/write memory in the target
1907 for the ROM-able zImage which must be available while the
1908 decompressor is running. It must be large enough to hold the
1909 entire decompressed kernel plus an additional 128 KiB.
1910 Platforms which normally make use of ROM-able zImage formats
1911 normally set this to a suitable value in their defconfig file.
1913 If ZBOOT_ROM is not enabled, this has no effect.
1916 bool "Compressed boot loader in ROM/flash"
1917 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1919 Say Y here if you intend to execute your compressed kernel image
1920 (zImage) directly from ROM or flash. If unsure, say N.
1923 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1924 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1925 default ZBOOT_ROM_NONE
1927 Include experimental SD/MMC loading code in the ROM-able zImage.
1928 With this enabled it is possible to write the ROM-able zImage
1929 kernel image to an MMC or SD card and boot the kernel straight
1930 from the reset vector. At reset the processor Mask ROM will load
1931 the first part of the ROM-able zImage which in turn loads the
1932 rest the kernel image to RAM.
1934 config ZBOOT_ROM_NONE
1935 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1937 Do not load image from SD or MMC
1939 config ZBOOT_ROM_MMCIF
1940 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1942 Load image from MMCIF hardware block.
1944 config ZBOOT_ROM_SH_MOBILE_SDHI
1945 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1947 Load image from SDHI hardware block
1951 config ARM_APPENDED_DTB
1952 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1953 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1955 With this option, the boot code will look for a device tree binary
1956 (DTB) appended to zImage
1957 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1959 This is meant as a backward compatibility convenience for those
1960 systems with a bootloader that can't be upgraded to accommodate
1961 the documented boot protocol using a device tree.
1963 Beware that there is very little in terms of protection against
1964 this option being confused by leftover garbage in memory that might
1965 look like a DTB header after a reboot if no actual DTB is appended
1966 to zImage. Do not leave this option active in a production kernel
1967 if you don't intend to always append a DTB. Proper passing of the
1968 location into r2 of a bootloader provided DTB is always preferable
1971 config ARM_ATAG_DTB_COMPAT
1972 bool "Supplement the appended DTB with traditional ATAG information"
1973 depends on ARM_APPENDED_DTB
1975 Some old bootloaders can't be updated to a DTB capable one, yet
1976 they provide ATAGs with memory configuration, the ramdisk address,
1977 the kernel cmdline string, etc. Such information is dynamically
1978 provided by the bootloader and can't always be stored in a static
1979 DTB. To allow a device tree enabled kernel to be used with such
1980 bootloaders, this option allows zImage to extract the information
1981 from the ATAG list and store it at run time into the appended DTB.
1984 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1985 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1987 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1988 bool "Use bootloader kernel arguments if available"
1990 Uses the command-line options passed by the boot loader instead of
1991 the device tree bootargs property. If the boot loader doesn't provide
1992 any, the device tree bootargs property will be used.
1994 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1995 bool "Extend with bootloader kernel arguments"
1997 The command-line arguments provided by the boot loader will be
1998 appended to the the device tree bootargs property.
2003 string "Default kernel command string"
2006 On some architectures (EBSA110 and CATS), there is currently no way
2007 for the boot loader to pass arguments to the kernel. For these
2008 architectures, you should supply some command-line options at build
2009 time by entering them here. As a minimum, you should specify the
2010 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2013 prompt "Kernel command line type" if CMDLINE != ""
2014 default CMDLINE_FROM_BOOTLOADER
2017 config CMDLINE_FROM_BOOTLOADER
2018 bool "Use bootloader kernel arguments if available"
2020 Uses the command-line options passed by the boot loader. If
2021 the boot loader doesn't provide any, the default kernel command
2022 string provided in CMDLINE will be used.
2024 config CMDLINE_EXTEND
2025 bool "Extend bootloader kernel arguments"
2027 The command-line arguments provided by the boot loader will be
2028 appended to the default kernel command string.
2030 config CMDLINE_FORCE
2031 bool "Always use the default kernel command string"
2033 Always use the default kernel command string, even if the boot
2034 loader passes other arguments to the kernel.
2035 This is useful if you cannot or don't want to change the
2036 command-line options your boot loader passes to the kernel.
2040 bool "Kernel Execute-In-Place from ROM"
2041 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2043 Execute-In-Place allows the kernel to run from non-volatile storage
2044 directly addressable by the CPU, such as NOR flash. This saves RAM
2045 space since the text section of the kernel is not loaded from flash
2046 to RAM. Read-write sections, such as the data section and stack,
2047 are still copied to RAM. The XIP kernel is not compressed since
2048 it has to run directly from flash, so it will take more space to
2049 store it. The flash address used to link the kernel object files,
2050 and for storing it, is configuration dependent. Therefore, if you
2051 say Y here, you must know the proper physical address where to
2052 store the kernel image depending on your own flash memory usage.
2054 Also note that the make target becomes "make xipImage" rather than
2055 "make zImage" or "make Image". The final kernel binary to put in
2056 ROM memory will be arch/arm/boot/xipImage.
2060 config XIP_PHYS_ADDR
2061 hex "XIP Kernel Physical Location"
2062 depends on XIP_KERNEL
2063 default "0x00080000"
2065 This is the physical address in your flash memory the kernel will
2066 be linked for and stored to. This address is dependent on your
2070 bool "Kexec system call (EXPERIMENTAL)"
2071 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2073 kexec is a system call that implements the ability to shutdown your
2074 current kernel, and to start another kernel. It is like a reboot
2075 but it is independent of the system firmware. And like a reboot
2076 you can start any kernel with it, not just Linux.
2078 It is an ongoing process to be certain the hardware in a machine
2079 is properly shutdown, so do not be surprised if this code does not
2080 initially work for you. It may help to enable device hotplugging
2084 bool "Export atags in procfs"
2085 depends on ATAGS && KEXEC
2088 Should the atags used to boot the kernel be exported in an "atags"
2089 file in procfs. Useful with kexec.
2092 bool "Build kdump crash kernel (EXPERIMENTAL)"
2093 depends on EXPERIMENTAL
2095 Generate crash dump after being started by kexec. This should
2096 be normally only set in special crash dump kernels which are
2097 loaded in the main kernel with kexec-tools into a specially
2098 reserved region and then later executed after a crash by
2099 kdump/kexec. The crash dump kernel must be compiled to a
2100 memory address not used by the main kernel
2102 For more details see Documentation/kdump/kdump.txt
2104 config AUTO_ZRELADDR
2105 bool "Auto calculation of the decompressed kernel image address"
2106 depends on !ZBOOT_ROM && !ARCH_U300
2108 ZRELADDR is the physical address where the decompressed kernel
2109 image will be placed. If AUTO_ZRELADDR is selected, the address
2110 will be determined at run-time by masking the current IP with
2111 0xf8000000. This assumes the zImage being placed in the first 128MB
2112 from start of memory.
2116 menu "CPU Power Management"
2120 source "drivers/cpufreq/Kconfig"
2123 tristate "CPUfreq driver for i.MX CPUs"
2124 depends on ARCH_MXC && CPU_FREQ
2125 select CPU_FREQ_TABLE
2127 This enables the CPUfreq driver for i.MX CPUs.
2129 config CPU_FREQ_SA1100
2132 config CPU_FREQ_SA1110
2135 config CPU_FREQ_INTEGRATOR
2136 tristate "CPUfreq driver for ARM Integrator CPUs"
2137 depends on ARCH_INTEGRATOR && CPU_FREQ
2140 This enables the CPUfreq driver for ARM Integrator CPUs.
2142 For details, take a look at <file:Documentation/cpu-freq>.
2148 depends on CPU_FREQ && ARCH_PXA && PXA25x
2150 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2151 select CPU_FREQ_TABLE
2156 Internal configuration node for common cpufreq on Samsung SoC
2158 config CPU_FREQ_S3C24XX
2159 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2160 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2163 This enables the CPUfreq driver for the Samsung S3C24XX family
2166 For details, take a look at <file:Documentation/cpu-freq>.
2170 config CPU_FREQ_S3C24XX_PLL
2171 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2172 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2174 Compile in support for changing the PLL frequency from the
2175 S3C24XX series CPUfreq driver. The PLL takes time to settle
2176 after a frequency change, so by default it is not enabled.
2178 This also means that the PLL tables for the selected CPU(s) will
2179 be built which may increase the size of the kernel image.
2181 config CPU_FREQ_S3C24XX_DEBUG
2182 bool "Debug CPUfreq Samsung driver core"
2183 depends on CPU_FREQ_S3C24XX
2185 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2187 config CPU_FREQ_S3C24XX_IODEBUG
2188 bool "Debug CPUfreq Samsung driver IO timing"
2189 depends on CPU_FREQ_S3C24XX
2191 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2193 config CPU_FREQ_S3C24XX_DEBUGFS
2194 bool "Export debugfs for CPUFreq"
2195 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2197 Export status information via debugfs.
2201 source "drivers/cpuidle/Kconfig"
2205 menu "Floating point emulation"
2207 comment "At least one emulation must be selected"
2210 bool "NWFPE math emulation"
2211 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2213 Say Y to include the NWFPE floating point emulator in the kernel.
2214 This is necessary to run most binaries. Linux does not currently
2215 support floating point hardware so you need to say Y here even if
2216 your machine has an FPA or floating point co-processor podule.
2218 You may say N here if you are going to load the Acorn FPEmulator
2219 early in the bootup.
2222 bool "Support extended precision"
2223 depends on FPE_NWFPE
2225 Say Y to include 80-bit support in the kernel floating-point
2226 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2227 Note that gcc does not generate 80-bit operations by default,
2228 so in most cases this option only enlarges the size of the
2229 floating point emulator without any good reason.
2231 You almost surely want to say N here.
2234 bool "FastFPE math emulation (EXPERIMENTAL)"
2235 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2237 Say Y here to include the FAST floating point emulator in the kernel.
2238 This is an experimental much faster emulator which now also has full
2239 precision for the mantissa. It does not support any exceptions.
2240 It is very simple, and approximately 3-6 times faster than NWFPE.
2242 It should be sufficient for most programs. It may be not suitable
2243 for scientific calculations, but you have to check this for yourself.
2244 If you do not feel you need a faster FP emulation you should better
2248 bool "VFP-format floating point maths"
2249 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2251 Say Y to include VFP support code in the kernel. This is needed
2252 if your hardware includes a VFP unit.
2254 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2255 release notes and additional status information.
2257 Say N if your target does not have VFP hardware.
2265 bool "Advanced SIMD (NEON) Extension support"
2266 depends on VFPv3 && CPU_V7
2268 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2273 menu "Userspace binary formats"
2275 source "fs/Kconfig.binfmt"
2278 tristate "RISC OS personality"
2281 Say Y here to include the kernel code necessary if you want to run
2282 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2283 experimental; if this sounds frightening, say N and sleep in peace.
2284 You can also say M here to compile this support as a module (which
2285 will be called arthur).
2289 menu "Power management options"
2291 source "kernel/power/Kconfig"
2293 config ARCH_SUSPEND_POSSIBLE
2294 depends on !ARCH_S5PC100
2295 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2296 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2299 config ARM_CPU_SUSPEND
2304 source "net/Kconfig"
2306 source "drivers/Kconfig"
2310 source "arch/arm/Kconfig.debug"
2312 source "security/Kconfig"
2314 source "crypto/Kconfig"
2316 source "lib/Kconfig"