4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
15 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_ARCH_TRACEHOOK
18 select HAVE_KPROBES if !XIP_KERNEL
19 select HAVE_KRETPROBES if (HAVE_KPROBES)
20 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
21 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
22 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
23 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
24 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
25 select HAVE_GENERIC_DMA_COHERENT
26 select HAVE_KERNEL_GZIP
27 select HAVE_KERNEL_LZO
28 select HAVE_KERNEL_LZMA
31 select HAVE_PERF_EVENTS
32 select PERF_USE_VMALLOC
33 select HAVE_REGS_AND_STACK_ACCESS_API
34 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_GENERIC_HARDIRQS
37 select HARDIRQS_SW_RESEND
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_PROBE
41 select HARDIRQS_SW_RESEND
42 select CPU_PM if (SUSPEND || CPU_IDLE)
43 select GENERIC_PCI_IOMAP
45 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 The ARM series is a line of low-power-consumption RISC chip designs
50 licensed by ARM Ltd and targeted at embedded applications and
51 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
52 manufactured, but legacy ARM-based PC hardware remains popular in
53 Europe. There is an ARM Linux project with a web page at
54 <http://www.arm.linux.org.uk/>.
56 config ARM_HAS_SG_CHAIN
59 config NEED_SG_DMA_LENGTH
62 config ARM_DMA_USE_IOMMU
63 select NEED_SG_DMA_LENGTH
64 select ARM_HAS_SG_CHAIN
73 config SYS_SUPPORTS_APM_EMULATION
81 select GENERIC_ALLOCATOR
92 The Extended Industry Standard Architecture (EISA) bus was
93 developed as an open alternative to the IBM MicroChannel bus.
95 The EISA bus provided some of the features of the IBM MicroChannel
96 bus while maintaining backward compatibility with cards made for
97 the older ISA bus. The EISA bus saw limited use between 1988 and
98 1995 when it was made obsolete by the PCI bus.
100 Say Y here if you are building a kernel for an EISA-based machine.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config GENERIC_LOCKBREAK
127 depends on SMP && PREEMPT
129 config RWSEM_GENERIC_SPINLOCK
133 config RWSEM_XCHGADD_ALGORITHM
136 config ARCH_HAS_ILOG2_U32
139 config ARCH_HAS_ILOG2_U64
142 config ARCH_HAS_CPUFREQ
145 Internal node to signify that the ARCH has CPUFREQ support
146 and that the relevant menu configurations are displayed for
149 config GENERIC_HWEIGHT
153 config GENERIC_CALIBRATE_DELAY
157 config ARCH_MAY_HAVE_PC_FDC
163 config NEED_DMA_MAP_STATE
166 config ARCH_HAS_DMA_SET_COHERENT_MASK
169 config GENERIC_ISA_DMA
175 config NEED_RET_TO_USER
183 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
184 default DRAM_BASE if REMAP_VECTORS_TO_RAM
187 The base address of exception vectors.
189 config ARM_PATCH_PHYS_VIRT
190 bool "Patch physical to virtual translations at runtime" if EMBEDDED
192 depends on !XIP_KERNEL && MMU
193 depends on !ARCH_REALVIEW || !SPARSEMEM
195 Patch phys-to-virt and virt-to-phys translation functions at
196 boot and module load time according to the position of the
197 kernel in system memory.
199 This can only be used with non-XIP MMU kernels where the base
200 of physical memory is at a 16MB boundary.
202 Only disable this option if you know that you do not require
203 this feature (eg, building a kernel for a single machine) and
204 you need to shrink the kernel to the minimal size.
206 config NEED_MACH_IO_H
209 Select this when mach/io.h is required to provide special
210 definitions for this platform. The need for mach/io.h should
211 be avoided when possible.
213 config NEED_MACH_MEMORY_H
216 Select this when mach/memory.h is required to provide special
217 definitions for this platform. The need for mach/memory.h should
218 be avoided when possible.
221 hex "Physical address of main memory" if MMU
222 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
223 default DRAM_BASE if !MMU
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
232 source "init/Kconfig"
234 source "kernel/Kconfig.freezer"
239 bool "MMU-based Paged Memory Management Support"
242 Select if you want MMU-based virtualised addressing space
243 support by paged memory management. If unsure, say 'Y'.
246 # The "ARM system type" choice list is ordered alphabetically by option
247 # text. Please add new entries in the option alphabetic order.
250 prompt "ARM system type"
251 default ARCH_VERSATILE
253 config ARCH_INTEGRATOR
254 bool "ARM Ltd. Integrator family"
256 select ARCH_HAS_CPUFREQ
258 select HAVE_MACH_CLKDEV
261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_FPGA_IRQ
264 select NEED_MACH_MEMORY_H
266 select MULTI_IRQ_HANDLER
268 Support for ARM's Integrator platform.
271 bool "ARM Ltd. RealView family"
274 select HAVE_MACH_CLKDEV
276 select GENERIC_CLOCKEVENTS
277 select ARCH_WANT_OPTIONAL_GPIOLIB
278 select PLAT_VERSATILE
279 select PLAT_VERSATILE_CLCD
280 select ARM_TIMER_SP804
281 select GPIO_PL061 if GPIOLIB
282 select NEED_MACH_MEMORY_H
284 This enables support for ARM Ltd RealView boards.
286 config ARCH_VERSATILE
287 bool "ARM Ltd. Versatile family"
291 select HAVE_MACH_CLKDEV
293 select GENERIC_CLOCKEVENTS
294 select ARCH_WANT_OPTIONAL_GPIOLIB
295 select PLAT_VERSATILE
296 select PLAT_VERSATILE_CLCD
297 select PLAT_VERSATILE_FPGA_IRQ
298 select ARM_TIMER_SP804
300 This enables support for ARM Ltd Versatile board.
303 bool "ARM Ltd. Versatile Express family"
304 select ARCH_WANT_OPTIONAL_GPIOLIB
306 select ARM_TIMER_SP804
308 select HAVE_MACH_CLKDEV
309 select GENERIC_CLOCKEVENTS
311 select HAVE_PATA_PLATFORM
314 select PLAT_VERSATILE
315 select PLAT_VERSATILE_CLCD
317 This enables support for the ARM Ltd Versatile Express boards.
321 select ARCH_REQUIRE_GPIOLIB
325 select NEED_MACH_IO_H if PCCARD
327 This enables support for systems based on Atmel
328 AT91RM9200 and AT91SAM9* processors.
331 bool "Broadcom BCMRING"
335 select ARM_TIMER_SP804
337 select GENERIC_CLOCKEVENTS
338 select ARCH_WANT_OPTIONAL_GPIOLIB
340 Support for Broadcom's BCMRing platform.
343 bool "Calxeda Highbank-based"
344 select ARCH_WANT_OPTIONAL_GPIOLIB
347 select ARM_TIMER_SP804
351 select GENERIC_CLOCKEVENTS
357 Support for the Calxeda Highbank SoC based boards.
360 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
362 select ARCH_USES_GETTIMEOFFSET
363 select NEED_MACH_MEMORY_H
365 Support for Cirrus Logic 711x/721x/731x based boards.
368 bool "Cavium Networks CNS3XXX family"
370 select GENERIC_CLOCKEVENTS
372 select MIGHT_HAVE_CACHE_L2X0
373 select MIGHT_HAVE_PCI
374 select PCI_DOMAINS if PCI
376 Support for Cavium Networks CNS3XXX platform.
379 bool "Cortina Systems Gemini"
381 select ARCH_REQUIRE_GPIOLIB
382 select ARCH_USES_GETTIMEOFFSET
384 Support for the Cortina Systems Gemini family SoCs
387 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
390 select GENERIC_CLOCKEVENTS
392 select GENERIC_IRQ_CHIP
393 select MIGHT_HAVE_CACHE_L2X0
399 Support for CSR SiRFSoC ARM Cortex A9 Platform
406 select ARCH_USES_GETTIMEOFFSET
407 select NEED_MACH_IO_H
408 select NEED_MACH_MEMORY_H
410 This is an evaluation board for the StrongARM processor available
411 from Digital. It has limited hardware on-board, including an
412 Ethernet interface, two PCMCIA sockets, two serial ports and a
421 select ARCH_REQUIRE_GPIOLIB
422 select ARCH_HAS_HOLES_MEMORYMODEL
423 select ARCH_USES_GETTIMEOFFSET
424 select NEED_MACH_MEMORY_H
426 This enables support for the Cirrus EP93xx series of CPUs.
428 config ARCH_FOOTBRIDGE
432 select GENERIC_CLOCKEVENTS
434 select NEED_MACH_IO_H if !MMU
435 select NEED_MACH_MEMORY_H
437 Support for systems based on the DC21285 companion chip
438 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
441 bool "Freescale MXC/iMX-based"
442 select GENERIC_CLOCKEVENTS
443 select ARCH_REQUIRE_GPIOLIB
446 select GENERIC_IRQ_CHIP
447 select MULTI_IRQ_HANDLER
449 Support for Freescale MXC/iMX-based family of processors
452 bool "Freescale MXS-based"
453 select GENERIC_CLOCKEVENTS
454 select ARCH_REQUIRE_GPIOLIB
458 select HAVE_CLK_PREPARE
462 Support for Freescale MXS-based family of processors
465 bool "Hilscher NetX based"
469 select GENERIC_CLOCKEVENTS
471 This enables support for systems based on the Hilscher NetX Soc
474 bool "Hynix HMS720x-based"
477 select ARCH_USES_GETTIMEOFFSET
479 This enables support for systems based on the Hynix HMS720x
487 select ARCH_SUPPORTS_MSI
489 select NEED_MACH_IO_H
490 select NEED_MACH_MEMORY_H
491 select NEED_RET_TO_USER
493 Support for Intel's IOP13XX (XScale) family of processors.
499 select NEED_MACH_IO_H
500 select NEED_RET_TO_USER
503 select ARCH_REQUIRE_GPIOLIB
505 Support for Intel's 80219 and IOP32X (XScale) family of
512 select NEED_MACH_IO_H
513 select NEED_RET_TO_USER
516 select ARCH_REQUIRE_GPIOLIB
518 Support for Intel's IOP33X (XScale) family of processors.
523 select ARCH_HAS_DMA_SET_COHERENT_MASK
526 select ARCH_REQUIRE_GPIOLIB
527 select GENERIC_CLOCKEVENTS
528 select MIGHT_HAVE_PCI
529 select NEED_MACH_IO_H
530 select DMABOUNCE if PCI
532 Support for Intel's IXP4XX (XScale) family of processors.
538 select ARCH_REQUIRE_GPIOLIB
539 select GENERIC_CLOCKEVENTS
542 Support for the Marvell Dove SoC 88AP510
545 bool "Marvell Kirkwood"
548 select ARCH_REQUIRE_GPIOLIB
549 select GENERIC_CLOCKEVENTS
552 Support for the following Marvell Kirkwood series SoCs:
553 88F6180, 88F6192 and 88F6281.
559 select ARCH_REQUIRE_GPIOLIB
562 select USB_ARCH_HAS_OHCI
564 select GENERIC_CLOCKEVENTS
567 Support for the NXP LPC32XX family of processors
570 bool "Marvell MV78xx0"
573 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
575 select NEED_MACH_IO_H
578 Support for the following Marvell MV78xx0 series SoCs:
586 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
590 Support for the following Marvell Orion 5x series SoCs:
591 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
592 Orion-2 (5281), Orion-1-90 (6183).
595 bool "Marvell PXA168/910/MMP2"
597 select ARCH_REQUIRE_GPIOLIB
599 select GENERIC_CLOCKEVENTS
604 select GENERIC_ALLOCATOR
606 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
609 bool "Micrel/Kendin KS8695"
611 select ARCH_REQUIRE_GPIOLIB
612 select ARCH_USES_GETTIMEOFFSET
613 select NEED_MACH_MEMORY_H
615 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
616 System-on-Chip devices.
619 bool "Nuvoton W90X900 CPU"
621 select ARCH_REQUIRE_GPIOLIB
624 select GENERIC_CLOCKEVENTS
626 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
627 At present, the w90x900 has been renamed nuc900, regarding
628 the ARM series product line, you can login the following
629 link address to know more.
631 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
632 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
638 select GENERIC_CLOCKEVENTS
642 select MIGHT_HAVE_CACHE_L2X0
643 select ARCH_HAS_CPUFREQ
645 This enables support for NVIDIA Tegra based systems (Tegra APX,
646 Tegra 6xx and Tegra 2 series).
648 config ARCH_PICOXCELL
649 bool "Picochip picoXcell"
650 select ARCH_REQUIRE_GPIOLIB
651 select ARM_PATCH_PHYS_VIRT
655 select GENERIC_CLOCKEVENTS
662 This enables support for systems based on the Picochip picoXcell
663 family of Femtocell devices. The picoxcell support requires device tree
667 bool "Philips Nexperia PNX4008 Mobile"
670 select ARCH_USES_GETTIMEOFFSET
672 This enables support for Philips PNX4008 mobile platform.
675 bool "PXA2xx/PXA3xx-based"
678 select ARCH_HAS_CPUFREQ
681 select ARCH_REQUIRE_GPIOLIB
682 select GENERIC_CLOCKEVENTS
687 select MULTI_IRQ_HANDLER
688 select ARM_CPU_SUSPEND if PM
691 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
696 select GENERIC_CLOCKEVENTS
697 select ARCH_REQUIRE_GPIOLIB
700 Support for Qualcomm MSM/QSD based systems. This runs on the
701 apps processor of the MSM/QSD and depends on a shared memory
702 interface to the modem processor which runs the baseband
703 stack and controls some vital subsystems
704 (clock and power control, etc).
707 bool "Renesas SH-Mobile / R-Mobile"
710 select HAVE_MACH_CLKDEV
712 select GENERIC_CLOCKEVENTS
713 select MIGHT_HAVE_CACHE_L2X0
716 select MULTI_IRQ_HANDLER
717 select PM_GENERIC_DOMAINS if PM
718 select NEED_MACH_MEMORY_H
720 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
726 select ARCH_MAY_HAVE_PC_FDC
727 select HAVE_PATA_PLATFORM
730 select ARCH_SPARSEMEM_ENABLE
731 select ARCH_USES_GETTIMEOFFSET
733 select NEED_MACH_IO_H
734 select NEED_MACH_MEMORY_H
736 On the Acorn Risc-PC, Linux can support the internal IDE disk and
737 CD-ROM interface, serial and parallel port, and the floppy drive.
744 select ARCH_SPARSEMEM_ENABLE
746 select ARCH_HAS_CPUFREQ
748 select GENERIC_CLOCKEVENTS
750 select ARCH_REQUIRE_GPIOLIB
752 select NEED_MACH_MEMORY_H
755 Support for StrongARM 11x0 based boards.
758 bool "Samsung S3C24XX SoCs"
760 select ARCH_HAS_CPUFREQ
763 select ARCH_USES_GETTIMEOFFSET
764 select HAVE_S3C2410_I2C if I2C
765 select HAVE_S3C_RTC if RTC_CLASS
766 select HAVE_S3C2410_WATCHDOG if WATCHDOG
767 select NEED_MACH_IO_H
769 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
770 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
771 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
772 Samsung SMDK2410 development board (and derivatives).
775 bool "Samsung S3C64XX"
783 select ARCH_USES_GETTIMEOFFSET
784 select ARCH_HAS_CPUFREQ
785 select ARCH_REQUIRE_GPIOLIB
786 select SAMSUNG_CLKSRC
787 select SAMSUNG_IRQ_VIC_TIMER
788 select S3C_GPIO_TRACK
790 select USB_ARCH_HAS_OHCI
791 select SAMSUNG_GPIOLIB_4BIT
792 select HAVE_S3C2410_I2C if I2C
793 select HAVE_S3C2410_WATCHDOG if WATCHDOG
795 Samsung S3C64XX series based systems
798 bool "Samsung S5P6440 S5P6450"
804 select HAVE_S3C2410_WATCHDOG if WATCHDOG
805 select GENERIC_CLOCKEVENTS
806 select HAVE_S3C2410_I2C if I2C
807 select HAVE_S3C_RTC if RTC_CLASS
809 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
813 bool "Samsung S5PC100"
818 select ARCH_USES_GETTIMEOFFSET
819 select HAVE_S3C2410_I2C if I2C
820 select HAVE_S3C_RTC if RTC_CLASS
821 select HAVE_S3C2410_WATCHDOG if WATCHDOG
823 Samsung S5PC100 series based systems
826 bool "Samsung S5PV210/S5PC110"
828 select ARCH_SPARSEMEM_ENABLE
829 select ARCH_HAS_HOLES_MEMORYMODEL
834 select ARCH_HAS_CPUFREQ
835 select GENERIC_CLOCKEVENTS
836 select HAVE_S3C2410_I2C if I2C
837 select HAVE_S3C_RTC if RTC_CLASS
838 select HAVE_S3C2410_WATCHDOG if WATCHDOG
839 select NEED_MACH_MEMORY_H
841 Samsung S5PV210/S5PC110 series based systems
844 bool "SAMSUNG EXYNOS"
846 select ARCH_SPARSEMEM_ENABLE
847 select ARCH_HAS_HOLES_MEMORYMODEL
851 select ARCH_HAS_CPUFREQ
852 select GENERIC_CLOCKEVENTS
853 select HAVE_S3C_RTC if RTC_CLASS
854 select HAVE_S3C2410_I2C if I2C
855 select HAVE_S3C2410_WATCHDOG if WATCHDOG
856 select NEED_MACH_MEMORY_H
858 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
867 select ARCH_USES_GETTIMEOFFSET
868 select NEED_MACH_MEMORY_H
870 Support for the StrongARM based Digital DNARD machine, also known
871 as "Shark" (<http://www.shark-linux.de/shark.html>).
874 bool "ST-Ericsson U300 Series"
880 select ARM_PATCH_PHYS_VIRT
882 select GENERIC_CLOCKEVENTS
884 select HAVE_MACH_CLKDEV
886 select ARCH_REQUIRE_GPIOLIB
888 Support for ST-Ericsson U300 series mobile platforms.
891 bool "ST-Ericsson U8500 Series"
895 select GENERIC_CLOCKEVENTS
897 select ARCH_REQUIRE_GPIOLIB
898 select ARCH_HAS_CPUFREQ
900 select MIGHT_HAVE_CACHE_L2X0
902 Support for ST-Ericsson's Ux500 architecture
905 bool "STMicroelectronics Nomadik"
910 select GENERIC_CLOCKEVENTS
912 select MIGHT_HAVE_CACHE_L2X0
913 select ARCH_REQUIRE_GPIOLIB
915 Support for the Nomadik platform by ST-Ericsson
919 select GENERIC_CLOCKEVENTS
920 select ARCH_REQUIRE_GPIOLIB
924 select GENERIC_ALLOCATOR
925 select GENERIC_IRQ_CHIP
926 select ARCH_HAS_HOLES_MEMORYMODEL
928 Support for TI's DaVinci platform.
933 select ARCH_REQUIRE_GPIOLIB
934 select ARCH_HAS_CPUFREQ
936 select GENERIC_CLOCKEVENTS
937 select ARCH_HAS_HOLES_MEMORYMODEL
939 Support for TI's OMAP platform (OMAP1/2/3/4).
944 select ARCH_REQUIRE_GPIOLIB
948 select GENERIC_CLOCKEVENTS
951 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
954 bool "VIA/WonderMedia 85xx"
957 select ARCH_HAS_CPUFREQ
958 select GENERIC_CLOCKEVENTS
959 select ARCH_REQUIRE_GPIOLIB
962 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
965 bool "Xilinx Zynq ARM Cortex A9 Platform"
967 select GENERIC_CLOCKEVENTS
972 select MIGHT_HAVE_CACHE_L2X0
975 Support for Xilinx Zynq ARM Cortex A9 Platform
979 # This is sorted alphabetically by mach-* pathname. However, plat-*
980 # Kconfigs may be included either alphabetically (according to the
981 # plat- suffix) or along side the corresponding mach-* source.
983 source "arch/arm/mach-at91/Kconfig"
985 source "arch/arm/mach-bcmring/Kconfig"
987 source "arch/arm/mach-clps711x/Kconfig"
989 source "arch/arm/mach-cns3xxx/Kconfig"
991 source "arch/arm/mach-davinci/Kconfig"
993 source "arch/arm/mach-dove/Kconfig"
995 source "arch/arm/mach-ep93xx/Kconfig"
997 source "arch/arm/mach-footbridge/Kconfig"
999 source "arch/arm/mach-gemini/Kconfig"
1001 source "arch/arm/mach-h720x/Kconfig"
1003 source "arch/arm/mach-integrator/Kconfig"
1005 source "arch/arm/mach-iop32x/Kconfig"
1007 source "arch/arm/mach-iop33x/Kconfig"
1009 source "arch/arm/mach-iop13xx/Kconfig"
1011 source "arch/arm/mach-ixp4xx/Kconfig"
1013 source "arch/arm/mach-kirkwood/Kconfig"
1015 source "arch/arm/mach-ks8695/Kconfig"
1017 source "arch/arm/mach-lpc32xx/Kconfig"
1019 source "arch/arm/mach-msm/Kconfig"
1021 source "arch/arm/mach-mv78xx0/Kconfig"
1023 source "arch/arm/plat-mxc/Kconfig"
1025 source "arch/arm/mach-mxs/Kconfig"
1027 source "arch/arm/mach-netx/Kconfig"
1029 source "arch/arm/mach-nomadik/Kconfig"
1030 source "arch/arm/plat-nomadik/Kconfig"
1032 source "arch/arm/plat-omap/Kconfig"
1034 source "arch/arm/mach-omap1/Kconfig"
1036 source "arch/arm/mach-omap2/Kconfig"
1038 source "arch/arm/mach-orion5x/Kconfig"
1040 source "arch/arm/mach-pxa/Kconfig"
1041 source "arch/arm/plat-pxa/Kconfig"
1043 source "arch/arm/mach-mmp/Kconfig"
1045 source "arch/arm/mach-realview/Kconfig"
1047 source "arch/arm/mach-sa1100/Kconfig"
1049 source "arch/arm/plat-samsung/Kconfig"
1050 source "arch/arm/plat-s3c24xx/Kconfig"
1052 source "arch/arm/plat-spear/Kconfig"
1054 source "arch/arm/mach-s3c24xx/Kconfig"
1056 source "arch/arm/mach-s3c2412/Kconfig"
1057 source "arch/arm/mach-s3c2440/Kconfig"
1061 source "arch/arm/mach-s3c64xx/Kconfig"
1064 source "arch/arm/mach-s5p64x0/Kconfig"
1066 source "arch/arm/mach-s5pc100/Kconfig"
1068 source "arch/arm/mach-s5pv210/Kconfig"
1070 source "arch/arm/mach-exynos/Kconfig"
1072 source "arch/arm/mach-shmobile/Kconfig"
1074 source "arch/arm/mach-tegra/Kconfig"
1076 source "arch/arm/mach-u300/Kconfig"
1078 source "arch/arm/mach-ux500/Kconfig"
1080 source "arch/arm/mach-versatile/Kconfig"
1082 source "arch/arm/mach-vexpress/Kconfig"
1083 source "arch/arm/plat-versatile/Kconfig"
1085 source "arch/arm/mach-vt8500/Kconfig"
1087 source "arch/arm/mach-w90x900/Kconfig"
1089 # Definitions to make life easier
1095 select GENERIC_CLOCKEVENTS
1100 select GENERIC_IRQ_CHIP
1106 config PLAT_VERSATILE
1109 config ARM_TIMER_SP804
1112 select HAVE_SCHED_CLOCK
1114 source arch/arm/mm/Kconfig
1118 default 16 if ARCH_EP93XX
1122 bool "Enable iWMMXt support"
1123 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1124 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1126 Enable support for iWMMXt context switching at run time if
1127 running on a CPU that supports it.
1131 depends on CPU_XSCALE
1135 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1136 (!ARCH_OMAP3 || OMAP3_EMU)
1140 config MULTI_IRQ_HANDLER
1143 Allow each machine to specify it's own IRQ handler at run time.
1146 source "arch/arm/Kconfig-nommu"
1149 config ARM_ERRATA_326103
1150 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1153 Executing a SWP instruction to read-only memory does not set bit 11
1154 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1155 treat the access as a read, preventing a COW from occurring and
1156 causing the faulting task to livelock.
1158 config ARM_ERRATA_411920
1159 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1160 depends on CPU_V6 || CPU_V6K
1162 Invalidation of the Instruction Cache operation can
1163 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1164 It does not affect the MPCore. This option enables the ARM Ltd.
1165 recommended workaround.
1167 config ARM_ERRATA_430973
1168 bool "ARM errata: Stale prediction on replaced interworking branch"
1171 This option enables the workaround for the 430973 Cortex-A8
1172 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1173 interworking branch is replaced with another code sequence at the
1174 same virtual address, whether due to self-modifying code or virtual
1175 to physical address re-mapping, Cortex-A8 does not recover from the
1176 stale interworking branch prediction. This results in Cortex-A8
1177 executing the new code sequence in the incorrect ARM or Thumb state.
1178 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1179 and also flushes the branch target cache at every context switch.
1180 Note that setting specific bits in the ACTLR register may not be
1181 available in non-secure mode.
1183 config ARM_ERRATA_458693
1184 bool "ARM errata: Processor deadlock when a false hazard is created"
1187 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1188 erratum. For very specific sequences of memory operations, it is
1189 possible for a hazard condition intended for a cache line to instead
1190 be incorrectly associated with a different cache line. This false
1191 hazard might then cause a processor deadlock. The workaround enables
1192 the L1 caching of the NEON accesses and disables the PLD instruction
1193 in the ACTLR register. Note that setting specific bits in the ACTLR
1194 register may not be available in non-secure mode.
1196 config ARM_ERRATA_460075
1197 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1200 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1201 erratum. Any asynchronous access to the L2 cache may encounter a
1202 situation in which recent store transactions to the L2 cache are lost
1203 and overwritten with stale memory contents from external memory. The
1204 workaround disables the write-allocate mode for the L2 cache via the
1205 ACTLR register. Note that setting specific bits in the ACTLR register
1206 may not be available in non-secure mode.
1208 config ARM_ERRATA_742230
1209 bool "ARM errata: DMB operation may be faulty"
1210 depends on CPU_V7 && SMP
1212 This option enables the workaround for the 742230 Cortex-A9
1213 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1214 between two write operations may not ensure the correct visibility
1215 ordering of the two writes. This workaround sets a specific bit in
1216 the diagnostic register of the Cortex-A9 which causes the DMB
1217 instruction to behave as a DSB, ensuring the correct behaviour of
1220 config ARM_ERRATA_742231
1221 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1222 depends on CPU_V7 && SMP
1224 This option enables the workaround for the 742231 Cortex-A9
1225 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1226 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1227 accessing some data located in the same cache line, may get corrupted
1228 data due to bad handling of the address hazard when the line gets
1229 replaced from one of the CPUs at the same time as another CPU is
1230 accessing it. This workaround sets specific bits in the diagnostic
1231 register of the Cortex-A9 which reduces the linefill issuing
1232 capabilities of the processor.
1234 config PL310_ERRATA_588369
1235 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1236 depends on CACHE_L2X0
1238 The PL310 L2 cache controller implements three types of Clean &
1239 Invalidate maintenance operations: by Physical Address
1240 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1241 They are architecturally defined to behave as the execution of a
1242 clean operation followed immediately by an invalidate operation,
1243 both performing to the same memory location. This functionality
1244 is not correctly implemented in PL310 as clean lines are not
1245 invalidated as a result of these operations.
1247 config ARM_ERRATA_720789
1248 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1251 This option enables the workaround for the 720789 Cortex-A9 (prior to
1252 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1253 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1254 As a consequence of this erratum, some TLB entries which should be
1255 invalidated are not, resulting in an incoherency in the system page
1256 tables. The workaround changes the TLB flushing routines to invalidate
1257 entries regardless of the ASID.
1259 config PL310_ERRATA_727915
1260 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1261 depends on CACHE_L2X0
1263 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1264 operation (offset 0x7FC). This operation runs in background so that
1265 PL310 can handle normal accesses while it is in progress. Under very
1266 rare circumstances, due to this erratum, write data can be lost when
1267 PL310 treats a cacheable write transaction during a Clean &
1268 Invalidate by Way operation.
1270 config ARM_ERRATA_743622
1271 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1274 This option enables the workaround for the 743622 Cortex-A9
1275 (r2p*) erratum. Under very rare conditions, a faulty
1276 optimisation in the Cortex-A9 Store Buffer may lead to data
1277 corruption. This workaround sets a specific bit in the diagnostic
1278 register of the Cortex-A9 which disables the Store Buffer
1279 optimisation, preventing the defect from occurring. This has no
1280 visible impact on the overall performance or power consumption of the
1283 config ARM_ERRATA_751472
1284 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1287 This option enables the workaround for the 751472 Cortex-A9 (prior
1288 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1289 completion of a following broadcasted operation if the second
1290 operation is received by a CPU before the ICIALLUIS has completed,
1291 potentially leading to corrupted entries in the cache or TLB.
1293 config PL310_ERRATA_753970
1294 bool "PL310 errata: cache sync operation may be faulty"
1295 depends on CACHE_PL310
1297 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1299 Under some condition the effect of cache sync operation on
1300 the store buffer still remains when the operation completes.
1301 This means that the store buffer is always asked to drain and
1302 this prevents it from merging any further writes. The workaround
1303 is to replace the normal offset of cache sync operation (0x730)
1304 by another offset targeting an unmapped PL310 register 0x740.
1305 This has the same effect as the cache sync operation: store buffer
1306 drain and waiting for all buffers empty.
1308 config ARM_ERRATA_754322
1309 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1312 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1313 r3p*) erratum. A speculative memory access may cause a page table walk
1314 which starts prior to an ASID switch but completes afterwards. This
1315 can populate the micro-TLB with a stale entry which may be hit with
1316 the new ASID. This workaround places two dsb instructions in the mm
1317 switching code so that no page table walks can cross the ASID switch.
1319 config ARM_ERRATA_754327
1320 bool "ARM errata: no automatic Store Buffer drain"
1321 depends on CPU_V7 && SMP
1323 This option enables the workaround for the 754327 Cortex-A9 (prior to
1324 r2p0) erratum. The Store Buffer does not have any automatic draining
1325 mechanism and therefore a livelock may occur if an external agent
1326 continuously polls a memory location waiting to observe an update.
1327 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1328 written polling loops from denying visibility of updates to memory.
1330 config ARM_ERRATA_364296
1331 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1332 depends on CPU_V6 && !SMP
1334 This options enables the workaround for the 364296 ARM1136
1335 r0p2 erratum (possible cache data corruption with
1336 hit-under-miss enabled). It sets the undocumented bit 31 in
1337 the auxiliary control register and the FI bit in the control
1338 register, thus disabling hit-under-miss without putting the
1339 processor into full low interrupt latency mode. ARM11MPCore
1342 config ARM_ERRATA_764369
1343 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1344 depends on CPU_V7 && SMP
1346 This option enables the workaround for erratum 764369
1347 affecting Cortex-A9 MPCore with two or more processors (all
1348 current revisions). Under certain timing circumstances, a data
1349 cache line maintenance operation by MVA targeting an Inner
1350 Shareable memory region may fail to proceed up to either the
1351 Point of Coherency or to the Point of Unification of the
1352 system. This workaround adds a DSB instruction before the
1353 relevant cache maintenance functions and sets a specific bit
1354 in the diagnostic control register of the SCU.
1356 config PL310_ERRATA_769419
1357 bool "PL310 errata: no automatic Store Buffer drain"
1358 depends on CACHE_L2X0
1360 On revisions of the PL310 prior to r3p2, the Store Buffer does
1361 not automatically drain. This can cause normal, non-cacheable
1362 writes to be retained when the memory system is idle, leading
1363 to suboptimal I/O performance for drivers using coherent DMA.
1364 This option adds a write barrier to the cpu_idle loop so that,
1365 on systems with an outer cache, the store buffer is drained
1370 source "arch/arm/common/Kconfig"
1380 Find out whether you have ISA slots on your motherboard. ISA is the
1381 name of a bus system, i.e. the way the CPU talks to the other stuff
1382 inside your box. Other bus systems are PCI, EISA, MicroChannel
1383 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1384 newer boards don't support it. If you have ISA, say Y, otherwise N.
1386 # Select ISA DMA controller support
1391 # Select ISA DMA interface
1396 bool "PCI support" if MIGHT_HAVE_PCI
1398 Find out whether you have a PCI motherboard. PCI is the name of a
1399 bus system, i.e. the way the CPU talks to the other stuff inside
1400 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1401 VESA. If you have PCI, say Y, otherwise N.
1407 config PCI_NANOENGINE
1408 bool "BSE nanoEngine PCI support"
1409 depends on SA1100_NANOENGINE
1411 Enable PCI on the BSE nanoEngine board.
1416 # Select the host bridge type
1417 config PCI_HOST_VIA82C505
1419 depends on PCI && ARCH_SHARK
1422 config PCI_HOST_ITE8152
1424 depends on PCI && MACH_ARMCORE
1428 source "drivers/pci/Kconfig"
1430 source "drivers/pcmcia/Kconfig"
1434 menu "Kernel Features"
1439 This option should be selected by machines which have an SMP-
1442 The only effect of this option is to make the SMP-related
1443 options available to the user for configuration.
1446 bool "Symmetric Multi-Processing"
1447 depends on CPU_V6K || CPU_V7
1448 depends on GENERIC_CLOCKEVENTS
1451 select USE_GENERIC_SMP_HELPERS
1452 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1454 This enables support for systems with more than one CPU. If you have
1455 a system with only one CPU, like most personal computers, say N. If
1456 you have a system with more than one CPU, say Y.
1458 If you say N here, the kernel will run on single and multiprocessor
1459 machines, but will use only one CPU of a multiprocessor machine. If
1460 you say Y here, the kernel will run on many, but not all, single
1461 processor machines. On a single processor machine, the kernel will
1462 run faster if you say N here.
1464 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1465 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1466 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1468 If you don't know what to do here, say N.
1471 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1472 depends on EXPERIMENTAL
1473 depends on SMP && !XIP_KERNEL
1476 SMP kernels contain instructions which fail on non-SMP processors.
1477 Enabling this option allows the kernel to modify itself to make
1478 these instructions safe. Disabling it allows about 1K of space
1481 If you don't know what to do here, say Y.
1483 config ARM_CPU_TOPOLOGY
1484 bool "Support cpu topology definition"
1485 depends on SMP && CPU_V7
1488 Support ARM cpu topology definition. The MPIDR register defines
1489 affinity between processors which is then used to describe the cpu
1490 topology of an ARM System.
1493 bool "Multi-core scheduler support"
1494 depends on ARM_CPU_TOPOLOGY
1496 Multi-core scheduler support improves the CPU scheduler's decision
1497 making when dealing with multi-core CPU chips at a cost of slightly
1498 increased overhead in some places. If unsure say N here.
1501 bool "SMT scheduler support"
1502 depends on ARM_CPU_TOPOLOGY
1504 Improves the CPU scheduler's decision making when dealing with
1505 MultiThreading at a cost of slightly increased overhead in some
1506 places. If unsure say N here.
1511 This option enables support for the ARM system coherency unit
1513 config ARM_ARCH_TIMER
1514 bool "Architected timer support"
1517 This option enables support for the ARM architected timer
1523 This options enables support for the ARM timer and watchdog unit
1526 prompt "Memory split"
1529 Select the desired split between kernel and user memory.
1531 If you are not absolutely sure what you are doing, leave this
1535 bool "3G/1G user/kernel split"
1537 bool "2G/2G user/kernel split"
1539 bool "1G/3G user/kernel split"
1544 default 0x40000000 if VMSPLIT_1G
1545 default 0x80000000 if VMSPLIT_2G
1549 int "Maximum number of CPUs (2-32)"
1555 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1556 depends on SMP && HOTPLUG && EXPERIMENTAL
1558 Say Y here to experiment with turning CPUs off and on. CPUs
1559 can be controlled through /sys/devices/system/cpu.
1562 bool "Use local timer interrupts"
1565 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1567 Enable support for local timers on SMP platforms, rather then the
1568 legacy IPI broadcast method. Local timers allows the system
1569 accounting to be spread across the timer interval, preventing a
1570 "thundering herd" at every timer tick.
1574 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1575 default 355 if ARCH_U8500
1576 default 264 if MACH_H4700
1579 Maximum number of GPIOs in the system.
1581 If unsure, leave the default value.
1583 source kernel/Kconfig.preempt
1587 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1588 ARCH_S5PV210 || ARCH_EXYNOS4
1589 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1590 default AT91_TIMER_HZ if ARCH_AT91
1591 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1594 config THUMB2_KERNEL
1595 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1596 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1598 select ARM_ASM_UNIFIED
1601 By enabling this option, the kernel will be compiled in
1602 Thumb-2 mode. A compiler/assembler that understand the unified
1603 ARM-Thumb syntax is needed.
1607 config THUMB2_AVOID_R_ARM_THM_JUMP11
1608 bool "Work around buggy Thumb-2 short branch relocations in gas"
1609 depends on THUMB2_KERNEL && MODULES
1612 Various binutils versions can resolve Thumb-2 branches to
1613 locally-defined, preemptible global symbols as short-range "b.n"
1614 branch instructions.
1616 This is a problem, because there's no guarantee the final
1617 destination of the symbol, or any candidate locations for a
1618 trampoline, are within range of the branch. For this reason, the
1619 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1620 relocation in modules at all, and it makes little sense to add
1623 The symptom is that the kernel fails with an "unsupported
1624 relocation" error when loading some modules.
1626 Until fixed tools are available, passing
1627 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1628 code which hits this problem, at the cost of a bit of extra runtime
1629 stack usage in some cases.
1631 The problem is described in more detail at:
1632 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1634 Only Thumb-2 kernels are affected.
1636 Unless you are sure your tools don't have this problem, say Y.
1638 config ARM_ASM_UNIFIED
1642 bool "Use the ARM EABI to compile the kernel"
1644 This option allows for the kernel to be compiled using the latest
1645 ARM ABI (aka EABI). This is only useful if you are using a user
1646 space environment that is also compiled with EABI.
1648 Since there are major incompatibilities between the legacy ABI and
1649 EABI, especially with regard to structure member alignment, this
1650 option also changes the kernel syscall calling convention to
1651 disambiguate both ABIs and allow for backward compatibility support
1652 (selected with CONFIG_OABI_COMPAT).
1654 To use this you need GCC version 4.0.0 or later.
1657 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1658 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1661 This option preserves the old syscall interface along with the
1662 new (ARM EABI) one. It also provides a compatibility layer to
1663 intercept syscalls that have structure arguments which layout
1664 in memory differs between the legacy ABI and the new ARM EABI
1665 (only for non "thumb" binaries). This option adds a tiny
1666 overhead to all syscalls and produces a slightly larger kernel.
1667 If you know you'll be using only pure EABI user space then you
1668 can say N here. If this option is not selected and you attempt
1669 to execute a legacy ABI binary then the result will be
1670 UNPREDICTABLE (in fact it can be predicted that it won't work
1671 at all). If in doubt say Y.
1673 config ARCH_HAS_HOLES_MEMORYMODEL
1676 config ARCH_SPARSEMEM_ENABLE
1679 config ARCH_SPARSEMEM_DEFAULT
1680 def_bool ARCH_SPARSEMEM_ENABLE
1682 config ARCH_SELECT_MEMORY_MODEL
1683 def_bool ARCH_SPARSEMEM_ENABLE
1685 config HAVE_ARCH_PFN_VALID
1686 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1689 bool "High Memory Support"
1692 The address space of ARM processors is only 4 Gigabytes large
1693 and it has to accommodate user address space, kernel address
1694 space as well as some memory mapped IO. That means that, if you
1695 have a large amount of physical memory and/or IO, not all of the
1696 memory can be "permanently mapped" by the kernel. The physical
1697 memory that is not permanently mapped is called "high memory".
1699 Depending on the selected kernel/user memory split, minimum
1700 vmalloc space and actual amount of RAM, you may not need this
1701 option which should result in a slightly faster kernel.
1706 bool "Allocate 2nd-level pagetables from highmem"
1709 config HW_PERF_EVENTS
1710 bool "Enable hardware performance counter support for perf events"
1711 depends on PERF_EVENTS && CPU_HAS_PMU
1714 Enable hardware performance counter support for perf events. If
1715 disabled, perf events will use software events only.
1719 config FORCE_MAX_ZONEORDER
1720 int "Maximum zone order" if ARCH_SHMOBILE
1721 range 11 64 if ARCH_SHMOBILE
1722 default "9" if SA1111
1725 The kernel memory allocator divides physically contiguous memory
1726 blocks into "zones", where each zone is a power of two number of
1727 pages. This option selects the largest power of two that the kernel
1728 keeps in the memory allocator. If you need to allocate very large
1729 blocks of physically contiguous memory, then you may need to
1730 increase this value.
1732 This config option is actually maximum order plus one. For example,
1733 a value of 11 means that the largest free memory block is 2^10 pages.
1736 bool "Timer and CPU usage LEDs"
1737 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1738 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1739 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1740 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1741 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1742 ARCH_AT91 || ARCH_DAVINCI || \
1743 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1745 If you say Y here, the LEDs on your machine will be used
1746 to provide useful information about your current system status.
1748 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1749 be able to select which LEDs are active using the options below. If
1750 you are compiling a kernel for the EBSA-110 or the LART however, the
1751 red LED will simply flash regularly to indicate that the system is
1752 still functional. It is safe to say Y here if you have a CATS
1753 system, but the driver will do nothing.
1756 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1757 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1758 || MACH_OMAP_PERSEUS2
1760 depends on !GENERIC_CLOCKEVENTS
1761 default y if ARCH_EBSA110
1763 If you say Y here, one of the system LEDs (the green one on the
1764 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1765 will flash regularly to indicate that the system is still
1766 operational. This is mainly useful to kernel hackers who are
1767 debugging unstable kernels.
1769 The LART uses the same LED for both Timer LED and CPU usage LED
1770 functions. You may choose to use both, but the Timer LED function
1771 will overrule the CPU usage LED.
1774 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1776 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1777 || MACH_OMAP_PERSEUS2
1780 If you say Y here, the red LED will be used to give a good real
1781 time indication of CPU usage, by lighting whenever the idle task
1782 is not currently executing.
1784 The LART uses the same LED for both Timer LED and CPU usage LED
1785 functions. You may choose to use both, but the Timer LED function
1786 will overrule the CPU usage LED.
1788 config ALIGNMENT_TRAP
1790 depends on CPU_CP15_MMU
1791 default y if !ARCH_EBSA110
1792 select HAVE_PROC_CPU if PROC_FS
1794 ARM processors cannot fetch/store information which is not
1795 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1796 address divisible by 4. On 32-bit ARM processors, these non-aligned
1797 fetch/store instructions will be emulated in software if you say
1798 here, which has a severe performance impact. This is necessary for
1799 correct operation of some network protocols. With an IP-only
1800 configuration it is safe to say N, otherwise say Y.
1802 config UACCESS_WITH_MEMCPY
1803 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1804 depends on MMU && EXPERIMENTAL
1805 default y if CPU_FEROCEON
1807 Implement faster copy_to_user and clear_user methods for CPU
1808 cores where a 8-word STM instruction give significantly higher
1809 memory write throughput than a sequence of individual 32bit stores.
1811 A possible side effect is a slight increase in scheduling latency
1812 between threads sharing the same address space if they invoke
1813 such copy operations with large buffers.
1815 However, if the CPU data cache is using a write-allocate mode,
1816 this option is unlikely to provide any performance gain.
1820 prompt "Enable seccomp to safely compute untrusted bytecode"
1822 This kernel feature is useful for number crunching applications
1823 that may need to compute untrusted bytecode during their
1824 execution. By using pipes or other transports made available to
1825 the process as file descriptors supporting the read/write
1826 syscalls, it's possible to isolate those applications in
1827 their own address space using seccomp. Once seccomp is
1828 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1829 and the task is only allowed to execute a few safe syscalls
1830 defined by each seccomp mode.
1832 config CC_STACKPROTECTOR
1833 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1834 depends on EXPERIMENTAL
1836 This option turns on the -fstack-protector GCC feature. This
1837 feature puts, at the beginning of functions, a canary value on
1838 the stack just before the return address, and validates
1839 the value just before actually returning. Stack based buffer
1840 overflows (that need to overwrite this return address) now also
1841 overwrite the canary, which gets detected and the attack is then
1842 neutralized via a kernel panic.
1843 This feature requires gcc version 4.2 or above.
1845 config DEPRECATED_PARAM_STRUCT
1846 bool "Provide old way to pass kernel parameters"
1848 This was deprecated in 2001 and announced to live on for 5 years.
1849 Some old boot loaders still use this way.
1856 bool "Flattened Device Tree support"
1858 select OF_EARLY_FLATTREE
1861 Include support for flattened device tree machine descriptions.
1863 # Compressed boot loader in ROM. Yes, we really want to ask about
1864 # TEXT and BSS so we preserve their values in the config files.
1865 config ZBOOT_ROM_TEXT
1866 hex "Compressed ROM boot loader base address"
1869 The physical address at which the ROM-able zImage is to be
1870 placed in the target. Platforms which normally make use of
1871 ROM-able zImage formats normally set this to a suitable
1872 value in their defconfig file.
1874 If ZBOOT_ROM is not enabled, this has no effect.
1876 config ZBOOT_ROM_BSS
1877 hex "Compressed ROM boot loader BSS address"
1880 The base address of an area of read/write memory in the target
1881 for the ROM-able zImage which must be available while the
1882 decompressor is running. It must be large enough to hold the
1883 entire decompressed kernel plus an additional 128 KiB.
1884 Platforms which normally make use of ROM-able zImage formats
1885 normally set this to a suitable value in their defconfig file.
1887 If ZBOOT_ROM is not enabled, this has no effect.
1890 bool "Compressed boot loader in ROM/flash"
1891 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1893 Say Y here if you intend to execute your compressed kernel image
1894 (zImage) directly from ROM or flash. If unsure, say N.
1897 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1898 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1899 default ZBOOT_ROM_NONE
1901 Include experimental SD/MMC loading code in the ROM-able zImage.
1902 With this enabled it is possible to write the ROM-able zImage
1903 kernel image to an MMC or SD card and boot the kernel straight
1904 from the reset vector. At reset the processor Mask ROM will load
1905 the first part of the ROM-able zImage which in turn loads the
1906 rest the kernel image to RAM.
1908 config ZBOOT_ROM_NONE
1909 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1911 Do not load image from SD or MMC
1913 config ZBOOT_ROM_MMCIF
1914 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1916 Load image from MMCIF hardware block.
1918 config ZBOOT_ROM_SH_MOBILE_SDHI
1919 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1921 Load image from SDHI hardware block
1925 config ARM_APPENDED_DTB
1926 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1927 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1929 With this option, the boot code will look for a device tree binary
1930 (DTB) appended to zImage
1931 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1933 This is meant as a backward compatibility convenience for those
1934 systems with a bootloader that can't be upgraded to accommodate
1935 the documented boot protocol using a device tree.
1937 Beware that there is very little in terms of protection against
1938 this option being confused by leftover garbage in memory that might
1939 look like a DTB header after a reboot if no actual DTB is appended
1940 to zImage. Do not leave this option active in a production kernel
1941 if you don't intend to always append a DTB. Proper passing of the
1942 location into r2 of a bootloader provided DTB is always preferable
1945 config ARM_ATAG_DTB_COMPAT
1946 bool "Supplement the appended DTB with traditional ATAG information"
1947 depends on ARM_APPENDED_DTB
1949 Some old bootloaders can't be updated to a DTB capable one, yet
1950 they provide ATAGs with memory configuration, the ramdisk address,
1951 the kernel cmdline string, etc. Such information is dynamically
1952 provided by the bootloader and can't always be stored in a static
1953 DTB. To allow a device tree enabled kernel to be used with such
1954 bootloaders, this option allows zImage to extract the information
1955 from the ATAG list and store it at run time into the appended DTB.
1958 string "Default kernel command string"
1961 On some architectures (EBSA110 and CATS), there is currently no way
1962 for the boot loader to pass arguments to the kernel. For these
1963 architectures, you should supply some command-line options at build
1964 time by entering them here. As a minimum, you should specify the
1965 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1968 prompt "Kernel command line type" if CMDLINE != ""
1969 default CMDLINE_FROM_BOOTLOADER
1971 config CMDLINE_FROM_BOOTLOADER
1972 bool "Use bootloader kernel arguments if available"
1974 Uses the command-line options passed by the boot loader. If
1975 the boot loader doesn't provide any, the default kernel command
1976 string provided in CMDLINE will be used.
1978 config CMDLINE_EXTEND
1979 bool "Extend bootloader kernel arguments"
1981 The command-line arguments provided by the boot loader will be
1982 appended to the default kernel command string.
1984 config CMDLINE_FORCE
1985 bool "Always use the default kernel command string"
1987 Always use the default kernel command string, even if the boot
1988 loader passes other arguments to the kernel.
1989 This is useful if you cannot or don't want to change the
1990 command-line options your boot loader passes to the kernel.
1994 bool "Kernel Execute-In-Place from ROM"
1995 depends on !ZBOOT_ROM && !ARM_LPAE
1997 Execute-In-Place allows the kernel to run from non-volatile storage
1998 directly addressable by the CPU, such as NOR flash. This saves RAM
1999 space since the text section of the kernel is not loaded from flash
2000 to RAM. Read-write sections, such as the data section and stack,
2001 are still copied to RAM. The XIP kernel is not compressed since
2002 it has to run directly from flash, so it will take more space to
2003 store it. The flash address used to link the kernel object files,
2004 and for storing it, is configuration dependent. Therefore, if you
2005 say Y here, you must know the proper physical address where to
2006 store the kernel image depending on your own flash memory usage.
2008 Also note that the make target becomes "make xipImage" rather than
2009 "make zImage" or "make Image". The final kernel binary to put in
2010 ROM memory will be arch/arm/boot/xipImage.
2014 config XIP_PHYS_ADDR
2015 hex "XIP Kernel Physical Location"
2016 depends on XIP_KERNEL
2017 default "0x00080000"
2019 This is the physical address in your flash memory the kernel will
2020 be linked for and stored to. This address is dependent on your
2024 bool "Kexec system call (EXPERIMENTAL)"
2025 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2027 kexec is a system call that implements the ability to shutdown your
2028 current kernel, and to start another kernel. It is like a reboot
2029 but it is independent of the system firmware. And like a reboot
2030 you can start any kernel with it, not just Linux.
2032 It is an ongoing process to be certain the hardware in a machine
2033 is properly shutdown, so do not be surprised if this code does not
2034 initially work for you. It may help to enable device hotplugging
2038 bool "Export atags in procfs"
2042 Should the atags used to boot the kernel be exported in an "atags"
2043 file in procfs. Useful with kexec.
2046 bool "Build kdump crash kernel (EXPERIMENTAL)"
2047 depends on EXPERIMENTAL
2049 Generate crash dump after being started by kexec. This should
2050 be normally only set in special crash dump kernels which are
2051 loaded in the main kernel with kexec-tools into a specially
2052 reserved region and then later executed after a crash by
2053 kdump/kexec. The crash dump kernel must be compiled to a
2054 memory address not used by the main kernel
2056 For more details see Documentation/kdump/kdump.txt
2058 config AUTO_ZRELADDR
2059 bool "Auto calculation of the decompressed kernel image address"
2060 depends on !ZBOOT_ROM && !ARCH_U300
2062 ZRELADDR is the physical address where the decompressed kernel
2063 image will be placed. If AUTO_ZRELADDR is selected, the address
2064 will be determined at run-time by masking the current IP with
2065 0xf8000000. This assumes the zImage being placed in the first 128MB
2066 from start of memory.
2070 menu "CPU Power Management"
2074 source "drivers/cpufreq/Kconfig"
2077 tristate "CPUfreq driver for i.MX CPUs"
2078 depends on ARCH_MXC && CPU_FREQ
2080 This enables the CPUfreq driver for i.MX CPUs.
2082 config CPU_FREQ_SA1100
2085 config CPU_FREQ_SA1110
2088 config CPU_FREQ_INTEGRATOR
2089 tristate "CPUfreq driver for ARM Integrator CPUs"
2090 depends on ARCH_INTEGRATOR && CPU_FREQ
2093 This enables the CPUfreq driver for ARM Integrator CPUs.
2095 For details, take a look at <file:Documentation/cpu-freq>.
2101 depends on CPU_FREQ && ARCH_PXA && PXA25x
2103 select CPU_FREQ_TABLE
2104 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2109 Internal configuration node for common cpufreq on Samsung SoC
2111 config CPU_FREQ_S3C24XX
2112 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2113 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2116 This enables the CPUfreq driver for the Samsung S3C24XX family
2119 For details, take a look at <file:Documentation/cpu-freq>.
2123 config CPU_FREQ_S3C24XX_PLL
2124 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2125 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2127 Compile in support for changing the PLL frequency from the
2128 S3C24XX series CPUfreq driver. The PLL takes time to settle
2129 after a frequency change, so by default it is not enabled.
2131 This also means that the PLL tables for the selected CPU(s) will
2132 be built which may increase the size of the kernel image.
2134 config CPU_FREQ_S3C24XX_DEBUG
2135 bool "Debug CPUfreq Samsung driver core"
2136 depends on CPU_FREQ_S3C24XX
2138 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2140 config CPU_FREQ_S3C24XX_IODEBUG
2141 bool "Debug CPUfreq Samsung driver IO timing"
2142 depends on CPU_FREQ_S3C24XX
2144 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2146 config CPU_FREQ_S3C24XX_DEBUGFS
2147 bool "Export debugfs for CPUFreq"
2148 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2150 Export status information via debugfs.
2154 source "drivers/cpuidle/Kconfig"
2158 menu "Floating point emulation"
2160 comment "At least one emulation must be selected"
2163 bool "NWFPE math emulation"
2164 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2166 Say Y to include the NWFPE floating point emulator in the kernel.
2167 This is necessary to run most binaries. Linux does not currently
2168 support floating point hardware so you need to say Y here even if
2169 your machine has an FPA or floating point co-processor podule.
2171 You may say N here if you are going to load the Acorn FPEmulator
2172 early in the bootup.
2175 bool "Support extended precision"
2176 depends on FPE_NWFPE
2178 Say Y to include 80-bit support in the kernel floating-point
2179 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2180 Note that gcc does not generate 80-bit operations by default,
2181 so in most cases this option only enlarges the size of the
2182 floating point emulator without any good reason.
2184 You almost surely want to say N here.
2187 bool "FastFPE math emulation (EXPERIMENTAL)"
2188 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2190 Say Y here to include the FAST floating point emulator in the kernel.
2191 This is an experimental much faster emulator which now also has full
2192 precision for the mantissa. It does not support any exceptions.
2193 It is very simple, and approximately 3-6 times faster than NWFPE.
2195 It should be sufficient for most programs. It may be not suitable
2196 for scientific calculations, but you have to check this for yourself.
2197 If you do not feel you need a faster FP emulation you should better
2201 bool "VFP-format floating point maths"
2202 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2204 Say Y to include VFP support code in the kernel. This is needed
2205 if your hardware includes a VFP unit.
2207 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2208 release notes and additional status information.
2210 Say N if your target does not have VFP hardware.
2218 bool "Advanced SIMD (NEON) Extension support"
2219 depends on VFPv3 && CPU_V7
2221 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2226 menu "Userspace binary formats"
2228 source "fs/Kconfig.binfmt"
2231 tristate "RISC OS personality"
2234 Say Y here to include the kernel code necessary if you want to run
2235 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2236 experimental; if this sounds frightening, say N and sleep in peace.
2237 You can also say M here to compile this support as a module (which
2238 will be called arthur).
2242 menu "Power management options"
2244 source "kernel/power/Kconfig"
2246 config ARCH_SUSPEND_POSSIBLE
2247 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2248 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2249 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2252 config ARM_CPU_SUSPEND
2257 source "net/Kconfig"
2259 source "drivers/Kconfig"
2263 source "arch/arm/Kconfig.debug"
2265 source "security/Kconfig"
2267 source "crypto/Kconfig"
2269 source "lib/Kconfig"