2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
16 #include "am33xx.dtsi"
17 #include <dt-bindings/pwm/pwm.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
21 model = "OnRISC Baltos iR 5221";
22 compatible = "vscom,onrisc", "ti,am33xx";
26 cpu0-supply = <&vdd1_reg>;
31 device_type = "memory";
32 reg = <0x80000000 0x10000000>; /* 256 MB */
35 vbat: fixedregulator@0 {
36 compatible = "regulator-fixed";
37 regulator-name = "vbat";
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
43 wl12xx_vmmc: fixedregulator@2 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&wl12xx_gpio>;
46 compatible = "regulator-fixed";
47 regulator-name = "vwl1271";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
51 startup-delay-us = <70000>;
57 mmc2_pins: pinmux_mmc2_pins {
58 pinctrl-single,pins = <
59 AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */
60 AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */
61 AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */
62 AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */
63 AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */
64 AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */
65 AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */
69 wl12xx_gpio: pinmux_wl12xx_gpio {
70 pinctrl-single,pins = <
71 AM33XX_IOPAD(0x9e8, PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
75 tps65910_pins: pinmux_tps65910_pins {
76 pinctrl-single,pins = <
77 AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */
81 tca6416_pins: pinmux_tca6416_pins {
82 pinctrl-single,pins = <
83 AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */
87 i2c1_pins: pinmux_i2c1_pins {
88 pinctrl-single,pins = <
89 AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */
90 AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */
94 dcan1_pins: pinmux_dcan1_pins {
95 pinctrl-single,pins = <
96 AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */
97 AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */
101 uart0_pins: pinmux_uart0_pins {
102 pinctrl-single,pins = <
103 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
104 AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
108 uart1_pins: pinmux_uart1_pins {
109 pinctrl-single,pins = <
110 AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */
111 AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */
112 AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_ctsn */
113 AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn */
114 AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */
115 AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */
116 AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */
117 AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */
121 uart2_pins: pinmux_uart2_pins {
122 pinctrl-single,pins = <
123 AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */
124 AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */
125 AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */
126 AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */
127 AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */
128 AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */
129 AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */
130 AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */
132 AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
136 cpsw_default: cpsw_default {
137 pinctrl-single,pins = <
139 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
140 AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */
141 AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
142 AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
143 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
144 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
145 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
149 AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
150 AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
151 AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
152 AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
153 AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
154 AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
155 AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
156 AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
157 AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
158 AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
159 AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
160 AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
164 cpsw_sleep: cpsw_sleep {
165 pinctrl-single,pins = <
166 /* Slave 1 reset value */
167 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
168 AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
169 AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
170 AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
171 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
172 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
173 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
175 /* Slave 2 reset value*/
176 AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
177 AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
178 AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
179 AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
180 AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
181 AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
182 AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
183 AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
184 AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
185 AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
186 AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
187 AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
191 davinci_mdio_default: davinci_mdio_default {
192 pinctrl-single,pins = <
194 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
195 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
199 davinci_mdio_sleep: davinci_mdio_sleep {
200 pinctrl-single,pins = <
201 /* MDIO reset value */
202 AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
203 AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
207 nandflash_pins_s0: nandflash_pins_s0 {
208 pinctrl-single,pins = <
209 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
210 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
211 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
212 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
213 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
214 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
215 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
216 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
217 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
218 AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
219 AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
220 AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
221 AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
222 AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
223 AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
233 pinctrl-names = "default";
234 pinctrl-0 = <&nandflash_pins_s0>;
235 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
239 compatible = "ti,omap2-nand";
240 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
241 interrupt-parent = <&gpmc>;
242 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
243 <1 IRQ_TYPE_NONE>; /* termcount */
244 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
245 nand-bus-width = <8>;
246 ti,nand-ecc-opt = "bch8";
247 ti,nand-xfer-type = "polled";
249 gpmc,device-nand = "true";
250 gpmc,device-width = <1>;
251 gpmc,sync-clk-ps = <0>;
253 gpmc,cs-rd-off-ns = <44>;
254 gpmc,cs-wr-off-ns = <44>;
255 gpmc,adv-on-ns = <6>;
256 gpmc,adv-rd-off-ns = <34>;
257 gpmc,adv-wr-off-ns = <44>;
259 gpmc,we-off-ns = <40>;
261 gpmc,oe-off-ns = <54>;
262 gpmc,access-ns = <64>;
263 gpmc,rd-cycle-ns = <82>;
264 gpmc,wr-cycle-ns = <82>;
265 gpmc,bus-turnaround-ns = <0>;
266 gpmc,cycle2cycle-delay-ns = <0>;
267 gpmc,clk-activation-ns = <0>;
268 gpmc,wr-access-ns = <40>;
269 gpmc,wr-data-mux-bus-ns = <0>;
271 #address-cells = <1>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&uart0_pins>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&uart1_pins>;
287 dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
288 dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
289 dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
290 rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&uart2_pins>;
298 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
299 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
300 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
301 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&i2c1_pins>;
311 clock-frequency = <400000>;
317 interrupt-parent = <&gpio1>;
318 interrupts = <28 GPIO_ACTIVE_LOW>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&tps65910_pins>;
324 compatible = "at24,24c02";
330 compatible = "ti,tca6416";
334 interrupt-parent = <&gpio0>;
335 interrupts = <20 GPIO_ACTIVE_LOW>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&tca6416_pins>;
371 #include "tps65910.dtsi"
374 vcc1-supply = <&vbat>;
375 vcc2-supply = <&vbat>;
376 vcc3-supply = <&vbat>;
377 vcc4-supply = <&vbat>;
378 vcc5-supply = <&vbat>;
379 vcc6-supply = <&vbat>;
380 vcc7-supply = <&vbat>;
381 vccio-supply = <&vbat>;
383 ti,en-ck32k-xtal = <1>;
386 vrtc_reg: regulator@0 {
390 vio_reg: regulator@1 {
394 vdd1_reg: regulator@2 {
395 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
396 regulator-name = "vdd_mpu";
397 regulator-min-microvolt = <912500>;
398 regulator-max-microvolt = <1312500>;
403 vdd2_reg: regulator@3 {
404 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
405 regulator-name = "vdd_core";
406 regulator-min-microvolt = <912500>;
407 regulator-max-microvolt = <1150000>;
412 vdd3_reg: regulator@4 {
416 vdig1_reg: regulator@5 {
420 vdig2_reg: regulator@6 {
424 vpll_reg: regulator@7 {
428 vdac_reg: regulator@8 {
432 vaux1_reg: regulator@9 {
436 vaux2_reg: regulator@10 {
440 vaux33_reg: regulator@11 {
444 vmmc_reg: regulator@12 {
445 regulator-min-microvolt = <1800000>;
446 regulator-max-microvolt = <3300000>;
453 pinctrl-names = "default", "sleep";
454 pinctrl-0 = <&cpsw_default>;
455 pinctrl-1 = <&cpsw_sleep>;
462 pinctrl-names = "default", "sleep";
463 pinctrl-0 = <&davinci_mdio_default>;
464 pinctrl-1 = <&davinci_mdio_sleep>;
470 phy_id = <&davinci_mdio>, <0>;
472 dual_emac_res_vlan = <1>;
476 phy_id = <&davinci_mdio>, <7>;
477 phy-mode = "rgmii-txid";
478 dual_emac_res_vlan = <2>;
482 rmii-clock-ext = <1>;
486 vmmc-supply = <&vmmc_reg>;
492 vmmc-supply = <&wl12xx_vmmc>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&mmc2_pins>;
499 #address-cells = <1>;
502 compatible = "ti,wl1835";
504 interrupt-parent = <&gpio3>;
505 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&dcan1_pins>;